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Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A.

Browse Source 
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: branches/laksen/armiw@29246 -
This commit is contained in:
Jeppe Johansen 2014-12-10 20:38:23 +00:00
parent dbea8c2507
commit d023c63ad0
19 changed files with 4677 additions and 2075 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2526
compiler/arm/aasmcpu.pas
View File

File diff suppressed because it is too large Load Diff

308
compiler/arm/armatt.inc
View File

@ -1,10 +1,6 @@
{ don't edit, this file is generated from armins.dat }
(
'none',
'abs',
'acs',
'asn',
'atn',
'adc',
'add',
'adf',
@ -17,24 +13,18 @@
'bkpt',
'bx',
'cdp',
'cmf',
'cmfe',
'cmn',
'cmp',
'cmf',
'cmfe',
'stf',
'ldf',
'lfm',
'clz',
'cnf',
'cos',
'cps',
'cpsid',
'cpsie',
'dvf',
'eor',
'exp',
'fdv',
'flt',
'fix',
'fml',
'frd',
'ldc',
'ldm',
'ldrbt',
@ -44,41 +34,31 @@
'ldrsb',
'ldrsh',
'ldrt',
'ldf',
'lfm',
'lgn',
'log',
'mcr',
'mcr2',
'mrc',
'mrc2',
'mcrr',
'mcrr2',
'mrrc',
'mrrc2',
'mla',
'mov',
'mrc',
'mrs',
'msr',
'mnf',
'muf',
'mul',
'mvf',
'mvn',
'vmov',
'nop',
'orr',
'rdf',
'rfs',
'rfc',
'rmf',
'rpw',
'rsb',
'rsc',
'rsf',
'rnd',
'pol',
'sbc',
'sfm',
'sin',
'smlal',
'smull',
'sqt',
'suf',
'stf',
'stm',
'str',
'strb',
@ -89,16 +69,14 @@
'swi',
'swp',
'swpb',
'tan',
'teq',
'tst',
'umlal',
'umull',
'wfs',
'ldrd',
'mcrr',
'mrrc',
'pld',
'pldw',
'qadd',
'qdadd',
'qdsub',
@ -113,6 +91,12 @@
'smlaltt',
'smlawb',
'smlawt',
'vldm',
'vstm',
'vpop',
'vpush',
'vldr',
'vstr',
'smulbb',
'smulbt',
'smultb',
@ -120,6 +104,112 @@
'smulwb',
'smulwt',
'strd',
'ldrht',
'strht',
'ldrsbt',
'strsbt',
'ldrsht',
'strsht',
'fstd',
'fstm',
'fsts',
'bfc',
'bfi',
'clrex',
'ldrex',
'ldrexb',
'ldrexd',
'ldrexh',
'strex',
'strexb',
'strexd',
'strexh',
'mls',
'pkhbt',
'pkhtb',
'pli',
'qadd16',
'qadd8',
'qasx',
'qsax',
'qsub16',
'qsub8',
'rbit',
'rev',
'rev16',
'revsh',
'sadd16',
'sadd8',
'sasx',
'sbfx',
'sel',
'setend',
'sev',
'asr',
'lsr',
'lsl',
'ror',
'rrx',
'umaal',
'shadd16',
'shadd8',
'shasx',
'shsax',
'shsub16',
'shsub8',
'smlad',
'smlald',
'smlsd',
'smlsld',
'smmla',
'smmls',
'smmul',
'smuad',
'smusd',
'srs',
'ssat',
'ssat16',
'ssax',
'ssub16',
'ssub8',
'sxtab',
'sxtab16',
'sxtah',
'ubfx',
'uxtab',
'uxtab16',
'uxtah',
'sxtb',
'sxtb16',
'sxth',
'uxtb',
'uxtb16',
'uxth',
'uadd16',
'uadd8',
'uasx',
'uhadd16',
'uhadd8',
'uhasx',
'uhsax',
'uhsub16',
'uhsub8',
'uqadd16',
'uqadd8',
'uqasx',
'uqsax',
'uqsub16',
'uqsub8',
'usad8',
'usada8',
'usat',
'usat16',
'usax',
'usub16',
'usub8',
'wfe',
'wfi',
'yield',
'fabsd',
'fabss',
'faddd',
@ -168,9 +258,6 @@
'fsitos',
'fsqrtd',
'fsqrts',
'fstd',
'fstm',
'fsts',
'fsubd',
'fsubs',
'ftosid',
@ -181,101 +268,6 @@
'fuitos',
'fmdrr',
'fmrrd',
'bfc',
'bfi',
'clrex',
'ldrex',
'ldrexb',
'ldrexd',
'ldrexh',
'mls',
'pkh',
'pli',
'qadd16',
'qadd8',
'qasx',
'qsax',
'qsub16',
'qsub8',
'rbit',
'rev',
'rev16',
'revsh',
'sadd16',
'sadd8',
'sasx',
'sbfx',
'sel',
'setend',
'sev',
'asr',
'lsr',
'lsl',
'ror',
'shadd16',
'shadd8',
'shasx',
'shsax',
'shsub16',
'shsub8',
'smlad',
'smlald',
'smlsd',
'smlsld',
'smmla',
'smmls',
'smmul',
'smuad',
'smusd',
'srs',
'ssat',
'ssat16',
'ssax',
'ssub16',
'ssub8',
'strex',
'strexb',
'strexd',
'strexh',
'sxtab',
'sxtab16',
'sxtah',
'sxtb',
'sxtb16',
'uxtb',
'uxth',
'sxth',
'uadd16',
'uadd8',
'uasx',
'ubfx',
'uhadd16',
'uhadd8',
'uhasx',
'uhsax',
'uhsub16',
'uhsub8',
'umaal',
'uqadd16',
'uqadd8',
'uqasx',
'uqsax',
'uqsub16',
'uqsub8',
'uqsad8',
'uqsada8',
'usat',
'usat16',
'usax',
'usub16',
'usub8',
'uxtab',
'uxtab16',
'uxtah',
'uxtb16',
'wfe',
'wfi',
'yield',
'pop',
'push',
'sdiv',
@ -306,29 +298,57 @@
'vcmp',
'vcmpe',
'vcvt',
'vcvtr',
'vdiv',
'vldm',
'vldr',
'vmov',
'vmrs',
'vmsr',
'vmul',
'vmla',
'vmls',
'vmul',
'vnmla',
'vnmls',
'vnmul',
'vfma',
'vfms',
'vfnma',
'vfnms',
'vneg',
'vnmul',
'vpop',
'vpush',
'vsqrt',
'vstm',
'vstr',
'vsub',
'dmb',
'isb',
'dsb',
'smc',
'neg',
'svc'
'svc',
'bxj',
'udf',
'tan',
'sqt',
'suf',
'rsf',
'rnd',
'pol',
'rdf',
'rfs',
'rfc',
'rmf',
'rpw',
'mnf',
'muf',
'abs',
'acs',
'asn',
'atn',
'cnf',
'cos',
'dvf',
'exp',
'fdv',
'flt',
'fix',
'fml',
'frd',
'lgn',
'log'
);

20
compiler/arm/armatts.inc
View File

@ -330,5 +330,25 @@ attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE
);

1092
compiler/arm/armins.dat
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File diff suppressed because it is too large Load Diff

2
compiler/arm/armnop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat }
105;
339;

308
compiler/arm/armop.inc
View File

@ -1,10 +1,6 @@
{ don't edit, this file is generated from armins.dat }
(
A_NONE,
A_ABS,
A_ACS,
A_ASN,
A_ATN,
A_ADC,
A_ADD,
A_ADF,
@ -17,24 +13,18 @@ A_BLX,
A_BKPT,
A_BX,
A_CDP,
A_CMF,
A_CMFE,
A_CMN,
A_CMP,
A_CMF,
A_CMFE,
A_STF,
A_LDF,
A_LFM,
A_CLZ,
A_CNF,
A_COS,
A_CPS,
A_CPSID,
A_CPSIE,
A_DVF,
A_EOR,
A_EXP,
A_FDV,
A_FLT,
A_FIX,
A_FML,
A_FRD,
A_LDC,
A_LDM,
A_LDRBT,
@ -44,41 +34,31 @@ A_LDRH,
A_LDRSB,
A_LDRSH,
A_LDRT,
A_LDF,
A_LFM,
A_LGN,
A_LOG,
A_MCR,
A_MCR2,
A_MRC,
A_MRC2,
A_MCRR,
A_MCRR2,
A_MRRC,
A_MRRC2,
A_MLA,
A_MOV,
A_MRC,
A_MRS,
A_MSR,
A_MNF,
A_MUF,
A_MUL,
A_MVF,
A_MVN,
A_VMOV,
A_NOP,
A_ORR,
A_RDF,
A_RFS,
A_RFC,
A_RMF,
A_RPW,
A_RSB,
A_RSC,
A_RSF,
A_RND,
A_POL,
A_SBC,
A_SFM,
A_SIN,
A_SMLAL,
A_SMULL,
A_SQT,
A_SUF,
A_STF,
A_STM,
A_STR,
A_STRB,
@ -89,16 +69,14 @@ A_SUB,
A_SWI,
A_SWP,
A_SWPB,
A_TAN,
A_TEQ,
A_TST,
A_UMLAL,
A_UMULL,
A_WFS,
A_LDRD,
A_MCRR,
A_MRRC,
A_PLD,
A_PLDW,
A_QADD,
A_QDADD,
A_QDSUB,
@ -113,6 +91,12 @@ A_SMLALTB,
A_SMLALTT,
A_SMLAWB,
A_SMLAWT,
A_VLDM,
A_VSTM,
A_VPOP,
A_VPUSH,
A_VLDR,
A_VSTR,
A_SMULBB,
A_SMULBT,
A_SMULTB,
@ -120,6 +104,112 @@ A_SMULTT,
A_SMULWB,
A_SMULWT,
A_STRD,
A_LDRHT,
A_STRHT,
A_LDRSBT,
A_STRSBT,
A_LDRSHT,
A_STRSHT,
A_FSTD,
A_FSTM,
A_FSTS,
A_BFC,
A_BFI,
A_CLREX,
A_LDREX,
A_LDREXB,
A_LDREXD,
A_LDREXH,
A_STREX,
A_STREXB,
A_STREXD,
A_STREXH,
A_MLS,
A_PKHBT,
A_PKHTB,
A_PLI,
A_QADD16,
A_QADD8,
A_QASX,
A_QSAX,
A_QSUB16,
A_QSUB8,
A_RBIT,
A_REV,
A_REV16,
A_REVSH,
A_SADD16,
A_SADD8,
A_SASX,
A_SBFX,
A_SEL,
A_SETEND,
A_SEV,
A_ASR,
A_LSR,
A_LSL,
A_ROR,
A_RRX,
A_UMAAL,
A_SHADD16,
A_SHADD8,
A_SHASX,
A_SHSAX,
A_SHSUB16,
A_SHSUB8,
A_SMLAD,
A_SMLALD,
A_SMLSD,
A_SMLSLD,
A_SMMLA,
A_SMMLS,
A_SMMUL,
A_SMUAD,
A_SMUSD,
A_SRS,
A_SSAT,
A_SSAT16,
A_SSAX,
A_SSUB16,
A_SSUB8,
A_SXTAB,
A_SXTAB16,
A_SXTAH,
A_UBFX,
A_UXTAB,
A_UXTAB16,
A_UXTAH,
A_SXTB,
A_SXTB16,
A_SXTH,
A_UXTB,
A_UXTB16,
A_UXTH,
A_UADD16,
A_UADD8,
A_UASX,
A_UHADD16,
A_UHADD8,
A_UHASX,
A_UHSAX,
A_UHSUB16,
A_UHSUB8,
A_UQADD16,
A_UQADD8,
A_UQASX,
A_UQSAX,
A_UQSUB16,
A_UQSUB8,
A_USAD8,
A_USADA8,
A_USAT,
A_USAT16,
A_USAX,
A_USUB16,
A_USUB8,
A_WFE,
A_WFI,
A_YIELD,
A_FABSD,
A_FABSS,
A_FADDD,
@ -168,9 +258,6 @@ A_FSITOD,
A_FSITOS,
A_FSQRTD,
A_FSQRTS,
A_FSTD,
A_FSTM,
A_FSTS,
A_FSUBD,
A_FSUBS,
A_FTOSID,
@ -181,101 +268,6 @@ A_FUITOD,
A_FUITOS,
A_FMDRR,
A_FMRRD,
A_BFC,
A_BFI,
A_CLREX,
A_LDREX,
A_LDREXB,
A_LDREXD,
A_LDREXH,
A_MLS,
A_PKH,
A_PLI,
A_QADD16,
A_QADD8,
A_QASX,
A_QSAX,
A_QSUB16,
A_QSUB8,
A_RBIT,
A_REV,
A_REV16,
A_REVSH,
A_SADD16,
A_SADD8,
A_SASX,
A_SBFX,
A_SEL,
A_SETEND,
A_SEV,
A_ASR,
A_LSR,
A_LSL,
A_ROR,
A_SHADD16,
A_SHADD8,
A_SHASX,
A_SHSAX,
A_SHSUB16,
A_SHSUB8,
A_SMLAD,
A_SMLALD,
A_SMLSD,
A_SMLSLD,
A_SMMLA,
A_SMMLS,
A_SMMUL,
A_SMUAD,
A_SMUSD,
A_SRS,
A_SSAT,
A_SSAT16,
A_SSAX,
A_SSUB16,
A_SSUB8,
A_STREX,
A_STREXB,
A_STREXD,
A_STREXH,
A_SXTAB,
A_SXTAB16,
A_SXTAH,
A_SXTB,
A_SXTB16,
A_UXTB,
A_UXTH,
A_SXTH,
A_UADD16,
A_UADD8,
A_UASX,
A_UBFX,
A_UHADD16,
A_UHADD8,
A_UHASX,
A_UHSAX,
A_UHSUB16,
A_UHSUB8,
A_UMAAL,
A_UQADD16,
A_UQADD8,
A_UQASX,
A_UQSAX,
A_UQSUB16,
A_UQSUB8,
A_UQSAD8,
A_UQSADA8,
A_USAT,
A_USAT16,
A_USAX,
A_USUB16,
A_USUB8,
A_UXTAB,
A_UXTAB16,
A_UXTAH,
A_UXTB16,
A_WFE,
A_WFI,
A_YIELD,
A_POP,
A_PUSH,
A_SDIV,
@ -306,29 +298,57 @@ A_VADD,
A_VCMP,
A_VCMPE,
A_VCVT,
A_VCVTR,
A_VDIV,
A_VLDM,
A_VLDR,
A_VMOV,
A_VMRS,
A_VMSR,
A_VMUL,
A_VMLA,
A_VMLS,
A_VMUL,
A_VNMLA,
A_VNMLS,
A_VNMUL,
A_VFMA,
A_VFMS,
A_VFNMA,
A_VFNMS,
A_VNEG,
A_VNMUL,
A_VPOP,
A_VPUSH,
A_VSQRT,
A_VSTM,
A_VSTR,
A_VSUB,
A_DMB,
A_ISB,
A_DSB,
A_SMC,
A_NEG,
A_SVC
A_SVC,
A_BXJ,
A_UDF,
A_TAN,
A_SQT,
A_SUF,
A_RSF,
A_RND,
A_POL,
A_RDF,
A_RFS,
A_RFC,
A_RMF,
A_RPW,
A_MNF,
A_MUF,
A_ABS,
A_ACS,
A_ASN,
A_ATN,
A_CNF,
A_COS,
A_DVF,
A_EXP,
A_FDV,
A_FLT,
A_FIX,
A_FML,
A_FRD,
A_LGN,
A_LOG
);

8
compiler/arm/armreg.dat
View File

@ -87,7 +87,7 @@ S28,$04,$06,$0E,s28,0,0
S29,$04,$06,$2E,s29,0,0
D14,$04,$07,$0E,d14,0,0
S30,$04,$06,$0F,s30,0,0
S31,$04,$06,$2F,s21,0,0
S31,$04,$06,$2F,s31,0,0
D15,$04,$07,$0F,d15,0,0
D16,$04,$07,$10,d16,0,0
D17,$04,$07,$11,d17,0,0
@ -145,4 +145,8 @@ BASEPRI,$05,$00,$1F,basepri,0,0
BASEPRI_MAX,$05,$00,$20,basepri_max,0,0
FAULTMASK,$05,$00,$21,faultmask,0,0
CONTROL,$05,$00,$22,control,0,0
; VFP registers
FPSID,$05,$00,$23,fpsid,0,0
MVFR1,$05,$00,$24,mvfr1,0,0
MVFR0,$05,$00,$25,mvfr0,0,0
FPEXC,$05,$00,$26,fpexc,0,0

2398
compiler/arm/armtab.inc
View File

File diff suppressed because it is too large Load Diff

36
compiler/arm/cpubase.pas
View File

@ -130,6 +130,10 @@ unit cpubase;
PF_S,
{ floating point size }
PF_D,PF_E,PF_P,PF_EP,
{ exchange }
PF_X,
{ rounding }
PF_R,
{ load/store }
PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T,
{ multiple load/store address modes }
@ -138,10 +142,18 @@ unit cpubase;
PF_IAD,PF_DBD,PF_FDD,PF_EAD,
PF_IAS,PF_DBS,PF_FDS,PF_EAS,
PF_IAX,PF_DBX,PF_FDX,PF_EAX,
{ FPv4 postfixes }
PF_32,PF_64,PF_F32,PF_F64,
PF_F32S32,PF_F32U32,
PF_S32F32,PF_U32F32
{ VFP postfixes }
PF_8,PF_16,PF_32,PF_64,
PF_I8,PF_I16,PF_I32,PF_I64,
PF_S8,PF_S16,PF_S32,PF_S64,
PF_U8,PF_U16,PF_U32,PF_U64,
PF_P8, // polynomial
PF_F32,PF_F64,
PF_F32F64,PF_F64F32,
PF_F32S16,PF_F32U16,PF_S16F32,PF_U16F32,
PF_F64S16,PF_F64U16,PF_S16F64,PF_U16F64,
PF_F32S32,PF_F32U32,PF_S32F32,PF_U32F32,
PF_F64S32,PF_F64U32,PF_S32F64,PF_U32F64
);
TOpPostfixes = set of TOpPostfix;
@ -157,14 +169,24 @@ unit cpubase;
oppostfix2str : array[TOpPostfix] of string[8] = ('',
's',
'd','e','p','ep',
'x',
'r',
'b','sb','bt','h','sh','t',
'ia','ib','da','db','fd','fa','ed','ea',
'iad','dbd','fdd','ead',
'ias','dbs','fds','eas',
'iax','dbx','fdx','eax',
'.32','.64','.f32','.f64',
'.f32.s32','.f32.u32',
'.s32.f32','.u32.f32');
'.8','.16','.32','.64',
'.i8','.i16','.i32','.i64',
'.s8','.s16','.s32','.s64',
'.u8','.u16','.u32','.u64',
'.p8',
'.f32','.f64',
'.f32.f64','.f64.f32',
'.f32.s16','.f32.u16','.s16.f32','.u16.f32',
'.f64.s16','.f64.u16','.s16.f64','.u16.f64',
'.f32.s32','.f32.u32','.s32.f32','.u32.f32',
'.f64.s32','.f64.u32','.s32.f64','.u32.f64');
roundingmode2str : array[TRoundingMode] of string[1] = ('',
'p','m','z');

4
compiler/arm/rarmcon.inc
View File

@ -123,3 +123,7 @@ NR_BASEPRI = tregister($0500001F);
NR_BASEPRI_MAX = tregister($05000020);
NR_FAULTMASK = tregister($05000021);
NR_CONTROL = tregister($05000022);
NR_FPSID = tregister($05000023);
NR_MVFR1 = tregister($05000024);
NR_MVFR0 = tregister($05000025);
NR_FPEXC = tregister($05000026);

4
compiler/arm/rarmdwa.inc
View File

@ -122,4 +122,8 @@
0,
0,
0,
0,
0,
0,
0,
0

2
compiler/arm/rarmnor.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armreg.dat }
124
128

6
compiler/arm/rarmnum.inc
View File

@ -122,4 +122,8 @@ tregister($0500001E),
tregister($0500001F),
tregister($05000020),
tregister($05000021),
tregister($05000022)
tregister($05000022),
tregister($05000023),
tregister($05000024),
tregister($05000025),
tregister($05000026)

6
compiler/arm/rarmrni.inc
View File

@ -122,4 +122,8 @@
120,
121,
122,
123
123,
124,
125,
126,
127

6
compiler/arm/rarmsri.inc
View File

@ -65,11 +65,15 @@
23,
24,
122,
127,
90,
124,
114,
113,
111,
117,
126,
125,
109,
119,
118,
@ -104,7 +108,6 @@
53,
28,
55,
71,
56,
58,
59,
@ -116,6 +119,7 @@
68,
29,
70,
71,
31,
32,
34,

4
compiler/arm/rarmsta.inc
View File

@ -122,4 +122,8 @@
0,
0,
0,
0,
0,
0,
0,
0

8
compiler/arm/rarmstd.inc
View File

@ -70,7 +70,7 @@
's29',
'd14',
's30',
's21',
's31',
'd15',
'd16',
'd17',
@ -122,4 +122,8 @@
'basepri',
'basepri_max',
'faultmask',
'control'
'control',
'fpsid',
'mvfr1',
'mvfr0',
'fpexc'

4
compiler/arm/rarmsup.inc
View File

@ -123,3 +123,7 @@ RS_BASEPRI = $1F;
RS_BASEPRI_MAX = $20;
RS_FAULTMASK = $21;
RS_CONTROL = $22;
RS_FPSID = $23;
RS_MVFR1 = $24;
RS_MVFR0 = $25;
RS_FPEXC = $26;

10
compiler/utils/mkarmins.pp
View File

@ -186,7 +186,7 @@ var
opcode,
codes,
flags : string;
optypes : array[1..4] of string;
optypes : array[1..6] of string;
begin
writeln('Narm Instruction Table Converter Version ',Version);
insns:=0;
@ -298,6 +298,8 @@ begin
optypes[2]:='';
optypes[3]:='';
optypes[4]:='';
optypes[5]:='';
optypes[6]:='';
codes:='';
flags:='';
skip:=false;
@ -324,8 +326,8 @@ begin
else
break;
until false;
for j:=1 to 4-ops do
optypes[4-j+1]:='ot_none';
for j:=1 to 6-ops do
optypes[6-j+1]:='ot_none';
{ codes }
skipspace;
j:=0;
@ -385,7 +387,7 @@ begin
writeln(insfile,' (');
writeln(insfile,' opcode : ',opcode,';');
writeln(insfile,' ops : ',ops,';');
writeln(insfile,' optypes : (',optypes[1],',',optypes[2],',',optypes[3],',',optypes[4],');');
writeln(insfile,' optypes : (',optypes[1],',',optypes[2],',',optypes[3],',',optypes[4],',',optypes[5],',',optypes[6],');');
writeln(insfile,' code : ',codes,';');
writeln(insfile,' flags : ',flags);
write(insfile,' )');