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Refactoring procedures in aoptx86 to gain speed boosts
This commit is contained in:
J. Gareth "Curious Kit" Moreton
J. Gareth "Kit" Moreton
parent
c85bef5494
commit
d209d3ba84
@ -50,7 +50,7 @@ unit aoptx86;
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OptsToCheck : set of TOptsToCheck;
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function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
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function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
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function RegReadByInstruction(reg : TRegister; hp : tai) : boolean;
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class function RegReadByInstruction(reg : TRegister; hp : tai) : boolean; static;
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function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
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function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
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@ -98,12 +98,12 @@ unit aoptx86;
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function GetMMRegisterBetween(RegSize: TSubRegister; var AUsedRegs: TAllUsedRegs; p, hp: tai): TRegister;
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{ checks whether loading a new value in reg1 overwrites the entirety of reg2 }
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function Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
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class function Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean; static;
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{ checks whether reading the value in reg1 depends on the value of reg2. This
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is very similar to SuperRegisterEquals, except it takes into account that
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R_SUBH and R_SUBL are independendent (e.g. reading from AL does not
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depend on the value in AH). }
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function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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class function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean; static;
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{ Replaces all references to AOldReg in a memory reference to ANewReg }
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class function ReplaceRegisterInRef(var ref: TReference; const AOldReg, ANewReg: TRegister): Boolean; static;
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@ -353,13 +353,12 @@ unit aoptx86;
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function RefsEqual(const r1, r2: treference): boolean;
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begin
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RefsEqual :=
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(r1.offset = r2.offset) and
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(r1.segment = r2.segment) and (r1.base = r2.base) and
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(r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
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(r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
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(r1.relsymbol = r2.relsymbol) and
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(r1.volatility=[]) and
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(r2.volatility=[]);
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(r1.segment = r2.segment) and (r1.base = r2.base) and
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(r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
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(r1.offset = r2.offset) and
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(r1.volatility + r2.volatility = []);
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end;
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@ -476,7 +475,7 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.RegReadByInstruction(reg: TRegister; hp: tai): boolean;
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class function TX86AsmOptimizer.RegReadByInstruction(reg: TRegister; hp: tai): boolean;
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var
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p: taicpu;
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opcount: longint;
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@ -1069,7 +1068,6 @@ unit aoptx86;
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Currentp: tai;
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Breakout: Boolean;
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begin
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{ TODO: Currently, only the volatile registers are checked - can this be extended to use any register the procedure has preserved? }
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Result := NR_NO;
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RegSet :=
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paramanager.get_volatile_registers_int(current_procinfo.procdef.proccalloption) +
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@ -1143,7 +1141,6 @@ unit aoptx86;
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Currentp: tai;
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Breakout: Boolean;
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begin
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{ TODO: Currently, only the volatile registers are checked - can this be extended to use any register the procedure has preserved? }
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Result := NR_NO;
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RegSet :=
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paramanager.get_volatile_registers_mm(current_procinfo.procdef.proccalloption) +
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@ -1198,7 +1195,7 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
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class function TX86AsmOptimizer.Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
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begin
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if not SuperRegistersEqual(reg1,reg2) then
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exit(false);
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@ -1235,7 +1232,7 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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class function TX86AsmOptimizer.Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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begin
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if not SuperRegistersEqual(reg1,reg2) then
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exit(false);
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@ -1426,7 +1423,7 @@ unit aoptx86;
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function TX86AsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu absolute hp;
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p: taicpu absolute hp; { Implicit typecast }
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i: Integer;
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begin
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Result := False;
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@ -1434,7 +1431,6 @@ unit aoptx86;
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(hp.typ <> ait_instruction) then
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Exit;
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// p := taicpu(hp);
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Prefetch(insprop[p.opcode]);
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if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
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with insprop[p.opcode] do
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@ -1442,12 +1438,14 @@ unit aoptx86;
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case getsubreg(reg) of
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R_SUBW,R_SUBD,R_SUBQ:
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Result:=
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RegLoadedWithNewValue(NR_CARRYFLAG,hp) and
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RegLoadedWithNewValue(NR_PARITYFLAG,hp) and
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RegLoadedWithNewValue(NR_AUXILIARYFLAG,hp) and
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RegLoadedWithNewValue(NR_ZEROFLAG,hp) and
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RegLoadedWithNewValue(NR_SIGNFLAG,hp) and
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RegLoadedWithNewValue(NR_OVERFLOWFLAG,hp);
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{ ZF, CF, OF, SF, PF and AF must all be set in some way (ordered so the most
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uncommon flags are checked first }
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([Ch_W0AuxiliaryFlag,Ch_W1AuxiliaryFlag,Ch_WAuxiliaryFlag,Ch_WUAuxiliaryFlag,Ch_WFlags] * Ch <> []) and
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([Ch_W0ParityFlag,Ch_W1ParityFlag,Ch_WParityFlag,Ch_WUParityFlag,Ch_WFlags]*Ch <> []) and
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([Ch_W0SignFlag,Ch_W1SignFlag,Ch_WSignFlag,Ch_WUSignFlag,Ch_WFlags]*Ch <> []) and
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([Ch_W0OverflowFlag,Ch_W1OverflowFlag,Ch_WOverflowFlag,Ch_WUOverflowFlag,Ch_WFlags]*Ch <> []) and
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([Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag,Ch_WFlags]*Ch <> []) and
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([Ch_W0ZeroFlag,Ch_W1ZeroFlag,Ch_WZeroFlag,Ch_WUZeroFlag,Ch_WFlags]*Ch <> []);
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R_SUBFLAGCARRY:
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Result:=[Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag,Ch_WFlags]*Ch<>[];
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R_SUBFLAGPARITY:
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@ -1465,10 +1463,7 @@ unit aoptx86;
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R_SUBFLAGDIRECTION:
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Result:=[Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags]*Ch<>[];
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else
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begin
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writeln(getsubreg(reg));
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internalerror(2017050501);
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end;
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end;
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exit;
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end;
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@ -1731,7 +1726,7 @@ unit aoptx86;
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end;
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end;
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{ Don't do these ones first in case an input operand is equal to an explicit output registers }
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{ Don't do these ones first in case an input operand is equal to an explicit output register }
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case getsupreg(reg) of
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RS_EAX:
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if ([Ch_WEAX{$ifdef x86_64},Ch_WRAX{$endif x86_64}]*Ch<>[]) and Reg1WriteOverwritesReg2Entirely(NR_EAX, reg) then
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@ -5002,7 +4997,8 @@ unit aoptx86;
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((taicpu(p).oper[0]^.ref^.symbol=nil) or (taicpu(hp1).oper[ref]^.ref^.symbol=nil)) and
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((taicpu(p).oper[0]^.ref^.relsymbol=nil) or (taicpu(hp1).oper[ref]^.ref^.relsymbol=nil)) and
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((taicpu(p).oper[0]^.ref^.scalefactor <= 1) or (taicpu(hp1).oper[ref]^.ref^.scalefactor <= 1)) and
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(taicpu(p).oper[0]^.ref^.segment=NR_NO) and (taicpu(hp1).oper[ref]^.ref^.segment=NR_NO)
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{ Segment register of p.oper[0]^.ref will be NR_NO already }
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(taicpu(hp1).oper[ref]^.ref^.segment=NR_NO)
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{$ifdef x86_64}
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and (abs(taicpu(hp1).oper[ref]^.ref^.offset+taicpu(p).oper[0]^.ref^.offset)<=$7fffffff)
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and (((taicpu(p).oper[0]^.ref^.base<>NR_RIP) and (taicpu(p).oper[0]^.ref^.index<>NR_RIP)) or
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@ -5053,10 +5049,9 @@ unit aoptx86;
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if MatchInstruction(hp1,A_LEA,[taicpu(p).opsize]) and
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(taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
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(taicpu(p).oper[0]^.ref^.relsymbol = nil) and
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(taicpu(p).oper[0]^.ref^.segment = NR_NO) and
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(taicpu(p).oper[0]^.ref^.symbol = nil) and
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(taicpu(hp1).oper[0]^.ref^.relsymbol = nil) and
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(taicpu(hp1).oper[0]^.ref^.segment = NR_NO) and
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{ Since we're merging two LEA instructions, the segment registers don't matter }
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(taicpu(hp1).oper[0]^.ref^.symbol = nil) and
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(
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(taicpu(p).oper[0]^.ref^.base = NR_NO) or { Don't call RegModifiedBetween unnecessarily }
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@ -5855,7 +5850,7 @@ unit aoptx86;
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if (TmpRef.base = NR_NO) and
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(taicpu(hp1).oper[0]^.ref^.symbol=nil) and
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(taicpu(hp1).oper[0]^.ref^.relsymbol=nil) and
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(taicpu(hp1).oper[0]^.ref^.segment=NR_NO) and
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{ Segment register isn't a concern here }
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((taicpu(hp1).oper[0]^.ref^.scalefactor=0) or
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(taicpu(hp1).oper[0]^.ref^.scalefactor*tmpref.scalefactor<=8)) then
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begin
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@ -12200,7 +12195,6 @@ unit aoptx86;
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(taicpu(p).oper[0]^.ref^.offset=-24)) and
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(taicpu(p).oper[0]^.ref^.symbol=nil) and
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(taicpu(p).oper[0]^.ref^.relsymbol=nil) and
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(taicpu(p).oper[0]^.ref^.segment=NR_NO) and
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(taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG) and
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GetNextInstruction(p, hp1) and
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{ Take a copy of hp1 }
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@ -12217,7 +12211,7 @@ unit aoptx86;
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(taicpu(hp2).oper[0]^.ref^.index=NR_NO) and
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(taicpu(hp2).oper[0]^.ref^.symbol=nil) and
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(taicpu(hp2).oper[0]^.ref^.relsymbol=nil) and
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(taicpu(hp2).oper[0]^.ref^.segment=NR_NO) and
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{ Segment register will be NR_NO }
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(taicpu(hp2).oper[1]^.reg=NR_STACK_POINTER_REG) and
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GetNextInstruction(hp2, hp3) and
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{ trick to skip label }
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