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- Removed obsolete comments (copypasted from other CPU code, most likely).

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- Removed topsize, MIPS target does not use it.

git-svn-id: trunk@24535 -
This commit is contained in:
sergei 2013-05-20 10:39:05 +00:00
parent e7cf738c31
commit d367148f75
2 changed files with 0 additions and 25 deletions
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12
compiler/mips/cgcpu.pas
View File

@ -1436,15 +1436,9 @@ begin
{ generate a loop } { generate a loop }
if Count > 4 then if Count > 4 then
begin begin
{ the offsets are zero after the a_loadaddress_ref_reg and just }
{ have to be set to 8. I put an Inc there so debugging may be }
{ easier (should offset be different from zero here, it will be }
{ easy to notice in the generated assembler }
countreg := GetIntRegister(list, OS_INT); countreg := GetIntRegister(list, OS_INT);
tmpreg1 := GetIntRegister(list, OS_INT); tmpreg1 := GetIntRegister(list, OS_INT);
a_load_const_reg(list, OS_INT, Count, countreg); a_load_const_reg(list, OS_INT, Count, countreg);
{ explicitely allocate R_O0 since it can be used safely here }
{ (for holding date that's being copied) }
current_asmdata.getjumplabel(lab); current_asmdata.getjumplabel(lab);
a_label(list, lab); a_label(list, lab);
list.concat(taicpu.op_reg_ref(A_LW, tmpreg1, src)); list.concat(taicpu.op_reg_ref(A_LW, tmpreg1, src));
@ -1526,15 +1520,9 @@ begin
{ generate a loop } { generate a loop }
if len > 4 then if len > 4 then
begin begin
{ the offsets are zero after the a_loadaddress_ref_reg and just }
{ have to be set to 8. I put an Inc there so debugging may be }
{ easier (should offset be different from zero here, it will be }
{ easy to notice in the generated assembler }
countreg := cg.GetIntRegister(list, OS_INT); countreg := cg.GetIntRegister(list, OS_INT);
tmpreg1 := cg.GetIntRegister(list, OS_INT); tmpreg1 := cg.GetIntRegister(list, OS_INT);
a_load_const_reg(list, OS_INT, len, countreg); a_load_const_reg(list, OS_INT, len, countreg);
{ explicitely allocate R_O0 since it can be used safely here }
{ (for holding date that's being copied) }
current_asmdata.getjumplabel(lab); current_asmdata.getjumplabel(lab);
a_label(list, lab); a_label(list, lab);
list.concat(taicpu.op_reg_ref(A_LBU, tmpreg1, src)); list.concat(taicpu.op_reg_ref(A_LBU, tmpreg1, src));

13
compiler/mips/cpubase.pas
View File

@ -138,17 +138,6 @@ unit cpubase;
maxfpuregs = 8; maxfpuregs = 8;
maxaddrregs = 0; maxaddrregs = 0;
{*****************************************************************************
Operand Sizes
*****************************************************************************}
type
topsize = (S_NO,
S_B,S_W,S_L,S_BW,S_BL,S_WL,
S_IS,S_IL,S_IQ,
S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
);
{***************************************************************************** {*****************************************************************************
Constants Constants
*****************************************************************************} *****************************************************************************}
@ -337,8 +326,6 @@ unit cpubase;
function is_calljmp(o:tasmop):boolean; function is_calljmp(o:tasmop):boolean;
begin begin
{ This isn't 100% perfect because the arm allows jumps also by writing to PC=R15.
To overcome this problem we simply forbid that FPC generates jumps by loading R15 }
is_calljmp:= o in [A_J,A_JAL,A_JALR,{ A_JALX, }A_JR, A_BA, A_BC, A_BC1T, A_BC1F]; is_calljmp:= o in [A_J,A_JAL,A_JALR,{ A_JALX, }A_JR, A_BA, A_BC, A_BC1T, A_BC1F];
end; end;