paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-09-13 21:29:19 +02:00
Code Issues Packages Projects Releases Wiki Activity

* x86: RegModifiedByInstruction and RegInInstruction

Browse Source 
are now more accurate for (I)MUL and (I)DIV.
This commit is contained in:
J. Gareth "Curious Kit" Moreton 2022-02-25 00:53:57 +00:00 committed by FPK
parent 3635f7cd6f
commit d372286159
1 changed files with 57 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
compiler/x86/aoptx86.pas
View File

@ -988,6 +988,25 @@ unit aoptx86;
{ change information for xmm movsd are not correct } { change information for xmm movsd are not correct }
((taicpu(p1).opcode<>A_MOVSD) or (taicpu(p1).ops=0)) then ((taicpu(p1).opcode<>A_MOVSD) or (taicpu(p1).ops=0)) then
begin begin
{ Handle instructions that behave differently depending on the size and operand count }
case taicpu(p1).opcode of
A_MUL, A_DIV, A_IDIV:
if taicpu(p1).opsize = S_B then
Result := (getsupreg(Reg) = RS_EAX)
else
Result := (getsupreg(Reg) in [RS_EAX, RS_EDX]);
A_IMUL:
if taicpu(p1).ops = 1 then
begin
if taicpu(p1).opsize = S_B then
Result := (getsupreg(Reg) = RS_EAX)
else
Result := (getsupreg(Reg) in [RS_EAX, RS_EDX]);
end;
{ If ops are greater than 1, call inherited method }
else
case getsupreg(reg) of case getsupreg(reg) of
{ RS_EAX = RS_RAX on x86-64 } { RS_EAX = RS_RAX on x86-64 }
RS_EAX: RS_EAX:
@ -1009,6 +1028,8 @@ unit aoptx86;
else else
; ;
end; end;
end;
if result then if result then
exit; exit;
end end
@ -1140,8 +1161,24 @@ unit aoptx86;
Result := (taicpu(p1).ops=3) and (taicpu(p1).oper[2]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[2]^); Result := (taicpu(p1).ops=3) and (taicpu(p1).oper[2]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[2]^);
exit; exit;
end; end;
A_MUL, A_DIV, A_IDIV:
begin
if taicpu(p1).opsize = S_B then
Result := (getsupreg(Reg) = RS_EAX)
else
Result := (getsupreg(Reg) in [RS_EAX, RS_EDX]);
end;
A_IMUL: A_IMUL:
begin
if taicpu(p1).ops = 1 then
begin
Result := (getsupreg(Reg) in [RS_EAX, RS_EDX]);
end
else
Result := (taicpu(p1).oper[taicpu(p1).ops-1]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[taicpu(p1).ops-1]^); Result := (taicpu(p1).oper[taicpu(p1).ops-1]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[taicpu(p1).ops-1]^);
Exit;
end;
else else
; ;
end; end;