* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.

git-svn-id: trunk@28708 -
This commit is contained in:
sergei 2014-09-22 16:18:16 +00:00
parent 2e0707f465
commit d37e72dbf9
2 changed files with 18 additions and 6 deletions

View File

@ -212,7 +212,7 @@ uses
function is_same_reg_move(regtype: Tregistertype):boolean; override; function is_same_reg_move(regtype: Tregistertype):boolean; override;
function spilling_get_operation_type(opnr: longint): topertype;override; function spilling_get_operation_type(opnr: longint): topertype;override;
function spilling_get_operation_type_ref(opnr: longint; reg: tregister): topertype;override;
{ assembler } { assembler }
public public
{ the next will reset all instructions that can change in pass 2 } { the next will reset all instructions that can change in pass 2 }
@ -777,6 +777,15 @@ implementation
end; end;
function taicpu.spilling_get_operation_type_ref(opnr: longint; reg: tregister): topertype;
begin
result := operand_read;
if (oper[opnr]^.ref^.base = reg) and
(oper[opnr]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) then
result := operand_readwrite;
end;
procedure BuildInsTabCache; procedure BuildInsTabCache;
var var
i : longint; i : longint;

View File

@ -124,11 +124,14 @@ Implementation
begin begin
result:=false; result:=false;
for i:=0 to taicpu(p1).ops-1 do for i:=0 to taicpu(p1).ops-1 do
if (taicpu(p1).oper[i]^.typ=top_reg) and (taicpu(p1).oper[i]^.reg=Reg) and (taicpu(p1).spilling_get_operation_type(i) in [operand_write,operand_readwrite]) then case taicpu(p1).oper[i]^.typ of
begin top_reg:
result:=true; if (taicpu(p1).oper[i]^.reg=Reg) and (taicpu(p1).spilling_get_operation_type(i) in [operand_write,operand_readwrite]) then
exit; exit(true);
end; top_ref:
if (taicpu(p1).spilling_get_operation_type_ref(i,Reg)<>operand_read) then
exit(true);
end;
end; end;
End. End.