From d53b17cadcad90200962c5942a47cec174047612 Mon Sep 17 00:00:00 2001 From: florian Date: Fri, 16 Apr 2021 19:33:31 +0000 Subject: [PATCH] + Aarch64: completed LSE support for all interlocked operations git-svn-id: trunk@49212 - --- compiler/aarch64/a64att.inc | 16 +++++++++++---- compiler/aarch64/a64atts.inc | 8 ++++++++ compiler/aarch64/a64ins.dat | 27 ++++++++++++++++++++----- compiler/aarch64/a64op.inc | 16 +++++++++++---- compiler/aarch64/aasmcpu.pas | 15 ++++++++++++++ rtl/aarch64/aarch64.inc | 38 ++++++++++++++++++++++++++++++++++++ 6 files changed, 107 insertions(+), 13 deletions(-) diff --git a/compiler/aarch64/a64att.inc b/compiler/aarch64/a64att.inc index 34d62055db..96c1b8318c 100644 --- a/compiler/aarch64/a64att.inc +++ b/compiler/aarch64/a64att.inc @@ -398,9 +398,6 @@ 'ror', 'neg', 'ins', -'cas', -'casp', -'ldadd', 'ldclr', 'ldeor', 'ldset', @@ -416,5 +413,16 @@ 'stsmin', 'stumax', 'stumin', -'swp' +'swp', +'swpa', +'swpal', +'swpl', +'ldadd', +'ldadda', +'ldaddal', +'ldaddl', +'cas', +'casa', +'casal', +'casl' ); diff --git a/compiler/aarch64/a64atts.inc b/compiler/aarch64/a64atts.inc index dac8dbfc01..61e446cdaa 100644 --- a/compiler/aarch64/a64atts.inc +++ b/compiler/aarch64/a64atts.inc @@ -416,5 +416,13 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, attsufNONE ); diff --git a/compiler/aarch64/a64ins.dat b/compiler/aarch64/a64ins.dat index cd7e1ce060..9d46a4ad9e 100644 --- a/compiler/aarch64/a64ins.dat +++ b/compiler/aarch64/a64ins.dat @@ -800,11 +800,6 @@ ; Large System Extensions -[CAS] - -[CASP] - -[LDADD] [LDCLR] @@ -838,3 +833,25 @@ [SWP] +[SWPA] + +[SWPAL] + +[SWPL] + +[LDADD] + +[LDADDA] + +[LDADDAL] + +[LDADDL] + +[CAS] + +[CASA] + +[CASAL] + +[CASL] + diff --git a/compiler/aarch64/a64op.inc b/compiler/aarch64/a64op.inc index 93b2b9eb91..6b0ddbcf82 100644 --- a/compiler/aarch64/a64op.inc +++ b/compiler/aarch64/a64op.inc @@ -398,9 +398,6 @@ A_LSR, A_ROR, A_NEG, A_INS, -A_CAS, -A_CASP, -A_LDADD, A_LDCLR, A_LDEOR, A_LDSET, @@ -416,5 +413,16 @@ A_STSMAX, A_STSMIN, A_STUMAX, A_STUMIN, -A_SWP +A_SWP, +A_SWPA, +A_SWPAL, +A_SWPL, +A_LDADD, +A_LDADDA, +A_LDADDAL, +A_LDADDL, +A_CAS, +A_CASA, +A_CASAL, +A_CASL ); diff --git a/compiler/aarch64/aasmcpu.pas b/compiler/aarch64/aasmcpu.pas index f1aed5e3fa..60726b3ffe 100644 --- a/compiler/aarch64/aasmcpu.pas +++ b/compiler/aarch64/aasmcpu.pas @@ -883,11 +883,26 @@ implementation result:=sr_complex; end; A_LDADD, + A_LDADDA, + A_LDADDAL, + A_LDADDL, + + A_SWP, + A_SWPA, + A_SWPAL, + A_SWPL, + + A_CAS, + A_CASA, + A_CASAL, + A_CASL, + A_STADD, A_LDAR, A_LDAXR, A_LDXR, A_LDXP, + A_STLR, A_STLXR, A_STLXP, diff --git a/rtl/aarch64/aarch64.inc b/rtl/aarch64/aarch64.inc index 65fc0f88d3..e8306e9259 100644 --- a/rtl/aarch64/aarch64.inc +++ b/rtl/aarch64/aarch64.inc @@ -326,22 +326,30 @@ function InterLockedExchange (var Target: longint;Source : longint) : longint; a { output: target in x0 } { side-effect: target := source } asm + {$ifdef CPUAARCH64_HAS_LSE} + swp w1,w0,[x0] + {$else CPUAARCH64_HAS_LSE} .LInterLockedXchgLoop: ldxr w2,[x0] stxr w3,w1,[x0] cbnz w3,.LInterLockedXchgLoop mov w0,w2 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + ldadd w1,w0,[x0] + {$else CPUAARCH64_HAS_LSE} .LInterLockedXchgAddLoop: ldxr w2,[x0] add w4,w2,w1 stxr w3,w4,[x0] cbnz w3,.LInterLockedXchgAddLoop mov w0,w2 + {$endif CPUAARCH64_HAS_LSE} end; @@ -350,6 +358,10 @@ function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comp { output: value stored in target before entry of the function } { side-effect: NewValue stored in target if (target = comparand) } asm + {$ifdef CPUAARCH64_HAS_LSE} + cas w2,w1,[x0] + mov w0,w2 + {$else CPUAARCH64_HAS_LSE} .LInterlockedCompareExchangeLoop: ldxr w3,[x0] cmp w3,w2 @@ -357,54 +369,79 @@ function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comp stxr w5,w4,[x0] cbnz w5,.LInterlockedCompareExchangeLoop mov w0,w3 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedDecrement64 (var Target: int64) : int64; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + mov x1,#-1 + ldadd x1,x2,[x0] + add x0,x2,x1 + {$else CPUAARCH64_HAS_LSE} .LInterDecLockedLoop: ldxr x1,[x0] sub x1,x1,#1 stxr w2,x1,[x0] cbnz w2,.LInterDecLockedLoop mov x0,x1 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedIncrement64 (var Target: int64) : int64; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + mov x1,#1 + ldadd x1,x2,[x0] + add x0,x2,x1 + {$else CPUAARCH64_HAS_LSE} .LInterIncLockedLoop: ldxr x1,[x0] add x1,x1,#1 stxr w2,x1,[x0] cbnz w2,.LInterIncLockedLoop mov x0,x1 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedExchange64 (var Target: int64;Source : int64) : int64; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + swp x1,x0,[x0] + {$else CPUAARCH64_HAS_LSE} .LInterLockedXchgLoop: ldxr x2,[x0] stxr w3,x1,[x0] cbnz w3,.LInterLockedXchgLoop mov x0,x2 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedExchangeAdd64 (var Target: int64;Source : int64) : int64; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + ldadd x1,x0,[x0] + {$else CPUAARCH64_HAS_LSE} .LInterLockedXchgAddLoop: ldxr x2,[x0] add x4,x2,x1 stxr w3,x4,[x0] cbnz w3,.LInterLockedXchgAddLoop mov x0,x2 + {$endif CPUAARCH64_HAS_LSE} end; function InterLockedCompareExchange64(var Target: int64; NewValue, Comperand : int64): int64; assembler; nostackframe; asm + {$ifdef CPUAARCH64_HAS_LSE} + cas x2,x1,[x0] + mov x0,x2 + {$else CPUAARCH64_HAS_LSE} .LInterlockedCompareExchangeLoop: ldxr x3,[x0] cmp x3,x2 @@ -412,6 +449,7 @@ function InterLockedCompareExchange64(var Target: int64; NewValue, Comperand : i stxr w5,x4,[x0] cbnz w5,.LInterlockedCompareExchangeLoop mov x0,x3 + {$endif CPUAARCH64_HAS_LSE} end;