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For now completely disable (I)MUL/(I)DIV support for Coldfire and pass through the RTL routines
(of which the names had changed from FPC_MUL_LONGWORD->FPC_MUL_DWORD and FPC_MOD_CARDINAL-> FPC_MOD_DWORD). Also disable the usage of FPU opcodes for Coldfire. git-svn-id: trunk@22739 -
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@ -865,7 +865,7 @@ unit cgcpu;
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end;
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OP_IMUL :
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begin
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if current_settings.cputype = cpu_MC68000 then
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if current_settings.cputype<>cpu_MC68020 then
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begin
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r:=NR_D0;
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r2:=NR_D1;
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@ -894,7 +894,7 @@ unit cgcpu;
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end;
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OP_MUL :
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begin
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if current_settings.cputype = cpu_MC68000 then
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if current_settings.cputype<>cpu_MC68020 then
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begin
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r:=NR_D0;
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r2:=NR_D1;
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@ -902,7 +902,7 @@ unit cgcpu;
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cg.getcpuregister(list,NR_D1);
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list.concat(taicpu.op_const_reg(A_MOVE,S_L,a, r));
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg, r2));
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cg.a_call_name(list,'FPC_MUL_LONGWORD',false);
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cg.a_call_name(list,'FPC_MUL_DWORD',false);
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg));
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cg.ungetcpuregister(list,r);
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cg.ungetcpuregister(list,r2);
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@ -1120,7 +1120,7 @@ unit cgcpu;
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begin
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sign_extend(list, size,reg1);
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sign_extend(list, size,reg2);
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if current_settings.cputype = cpu_MC68000 then
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if current_settings.cputype <> cpu_MC68020 then
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begin
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r:=NR_D0;
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r2:=NR_D1;
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@ -1128,7 +1128,7 @@ unit cgcpu;
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cg.getcpuregister(list,NR_D1);
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1, r));
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg2, r2));
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cg.a_call_name(list,'FPC_MUL_LONGWORD',false);
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cg.a_call_name(list,'FPC_MUL_DWORD',false);
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,r, reg2));
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cg.ungetcpuregister(list,r);
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cg.ungetcpuregister(list,r2);
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@ -145,7 +145,7 @@ implementation
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paraloc1 : tcgpara;
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begin
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{ no RTL call, so inline a zero denominator verification }
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if current_settings.cputype <> cpu_MC68000 then
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if current_settings.cputype=cpu_MC68020 then
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begin
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{ verify if denominator is zero }
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current_asmdata.getjumplabel(continuelabel);
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@ -165,7 +165,7 @@ implementation
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end
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else
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begin
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{ On MC68000/68010 mw must pass through RTL routines }
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{ On MC68000/68010/Coldfire we must pass through RTL routines }
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reg_d0:=NR_D0;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D0);
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reg_d1:=NR_D1;
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@ -193,7 +193,7 @@ implementation
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begin
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// writeln('emit mod reg reg');
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{ no RTL call, so inline a zero denominator verification }
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if current_settings.cputype <> cpu_MC68000 then
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if current_settings.cputype=cpu_MC68020 then
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begin
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{ verify if denominator is zero }
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current_asmdata.getjumplabel(continuelabel);
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@ -228,7 +228,7 @@ implementation
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end
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else
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begin
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{ On MC68000/68010 mw must pass through RTL routines }
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{ On MC68000/68010/coldfire we must pass through RTL routines }
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Reg_d0:=NR_D0;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D0);
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Reg_d1:=NR_D1;
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@ -240,7 +240,7 @@ implementation
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if signed then
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_MOD_LONGINT',false)
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else
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_MOD_CARDINAL',false);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_MOD_DWORD',false);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,Reg_D0,denum);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,Reg_D0);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,Reg_D1);
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@ -142,6 +142,12 @@ Type
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{$ifdef CPUM68K}
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{$define DEFAULT_DOUBLE}
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{$ifdef CPUCOLDFIRE}
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{$define FPC_INCLUDE_SOFTWARE_MOD_DIV}
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{$define FPC_INCLUDE_SOFTWARE_MUL}
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{$define FPC_INCLUDE_SOFTWARE_SHIFT_INT64}
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{$endif}
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{$define SUPPORT_SINGLE}
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{$define SUPPORT_DOUBLE}
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@ -47,10 +47,12 @@ const
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Procedure ResetFPU;
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begin
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{$ifdef CPU68020}
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asm
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fmove.l fpucw,fpcr
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fmove.l fpust,fpsr
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end;
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{$endif}
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end;
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