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* MIPS: fixed 8/16 bit arithmetic shifting to be done without using an additional register.

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git-svn-id: trunk@26736 -
This commit is contained in:
sergei 2014-02-08 21:13:58 +00:00
parent d29300df13
commit d7c7ee2c2a
1 changed files with 3 additions and 6 deletions
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9
compiler/mips/cgcpu.pas
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@ -796,8 +796,6 @@ end;
procedure TCGMIPS.a_op_reg_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
var
hreg: tregister;
begin
if (TOpcg2AsmOp[op]=A_NONE) then
InternalError(2013070305);
@ -805,11 +803,10 @@ begin
begin
if (size in [OS_S8,OS_S16]) then
begin
{ Shift left by 16/24 bits and increase amount of right shift by same value }
{ Sign-extend before shiting }
list.concat(taicpu.op_reg_reg_const(A_SLL, dst, src2, 32-(tcgsize2size[size]*8)));
hreg:=GetIntRegister(list,OS_INT);
a_op_const_reg_reg(list,OP_ADD,OS_INT,32-(tcgsize2size[size]*8),src1,dst);
src1:=hreg;
list.concat(taicpu.op_reg_reg_const(A_SRA, dst, dst, 32-(tcgsize2size[size]*8)));
src2:=dst;
end
else if not (size in [OS_32,OS_S32]) then
InternalError(2013070306);