From d8298c9f14ffe98e06a766597f8af54c81ead38a Mon Sep 17 00:00:00 2001 From: pierre Date: Wed, 8 Jan 2020 23:08:30 +0000 Subject: [PATCH] Try to correctly handle m68k exceptions bits inside SetExceptionMask function git-svn-id: trunk@43893 - --- rtl/m68k/mathu.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/rtl/m68k/mathu.inc b/rtl/m68k/mathu.inc index 61312adcd4..80f2cf0ef9 100644 --- a/rtl/m68k/mathu.inc +++ b/rtl/m68k/mathu.inc @@ -88,9 +88,14 @@ end; function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask; const FPCToFPUExceptionFlags: array[TFPUException] of DWord = - ( FPU68K_EXCEPT_OPERR, 0, FPU68K_EXCEPT_DZ, FPU68K_EXCEPT_OVFL, FPU68K_EXCEPT_UNFL, FPU68K_EXCEPT_INEX2 ); + ( {exInvalidOp,} FPU68K_EXCEPT_OPERR or FPU68K_EXCEPT_SNAN or FPU68K_EXCEPT_BSUN, + {exDenormalized,} 0, + {exZeroDivide,} FPU68K_EXCEPT_DZ, + {exOverflow,} FPU68K_EXCEPT_OVFL, + {exUnderflow,} FPU68K_EXCEPT_UNFL, + {exPrecision} FPU68K_EXCEPT_INEX1 or FPU68K_EXCEPT_INEX2 ); FPUToFPCExceptionFlags: array[0..7] of TFPUExceptionMask = - ( [], [exPrecision], [exZeroDivide], [exUnderflow], [exOverflow], [exInvalidOp], [], [] ); + ( [exPrecision], [exPrecision], [exZeroDivide], [exUnderflow], [exOverflow], [exInvalidOp], [exInvalidOp], [exInvalidOp] ); var oldMode, Mode: DWord; e: TFPUException; @@ -104,10 +109,13 @@ begin result:=result+FPUToFPCExceptionFlags[i]; mode:=0; - for e in Mask do - mode:=mode or FPCToFPUExceptionFlags[e]; + { The bits set inside FPCR register are the enabled exceptions, + not the masked exceptions, thus we need to invert list } + for e:=low(TFPUException) to high(TFPUException) do + if not (e in Mask) then + mode:=mode or FPCToFPUExceptionFlags[e]; - SetFPCR((GetFPCR and not FPU68K_EXCEPT_MASK) or (mode shl FPU68K_EXCEPT_MASK_SHIFT)); + SetFPCR((GetFPCR and not FPU68K_EXCEPT_MASK) or (mode and FPU68K_EXCEPT_MASK)); softfloat_exception_mask:=mask; end;