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* RiscV64: make use of zext.w instruction if available

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florian 2025-02-19 22:43:39 +01:00
parent 35a21de57c
commit d842d822ff
1 changed files with 2 additions and 0 deletions
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2
compiler/riscv64/cgcpu.pas
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@ -102,6 +102,8 @@ implementation
list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
else if (tosize=OS_S32) and (tcgsize2unsigned[fromsize]=OS_64) then
list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
else if (CPURV_HAS_ZBA in cpu_capabilities[current_settings.cputype]) and (tosize=OS_32) and (tcgsize2unsigned[fromsize]=OS_64) then
list.Concat(taicpu.op_reg_reg(A_ZEXT_W,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_S16) then
list.Concat(taicpu.op_reg_reg(A_SEXT_H,reg2,reg1))
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tosize=OS_S16) and (tcgsize2unsigned[fromsize]=OS_64) then