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https://gitlab.com/freepascal.org/fpc/source.git
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* (modified) patch by J. Gareth Moreton to unify ldr/str optimizations on Aarch64/ARM, part of #38841
git-svn-id: trunk@49338 -
This commit is contained in:
florian
parent
3c205f895c
commit
d936280c6b
@ -44,6 +44,10 @@ Interface
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function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;override;
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function InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;override;
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function LookForPostindexedPattern(var p : tai) : boolean;
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public
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{ With these routines, there's optimisation code that's general for all ARM platforms }
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function OptPass1LDR(var p: tai): Boolean; override;
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function OptPass1STR(var p: tai): Boolean; override;
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private
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function RemoveSuperfluousFMov(const p: tai; movp: tai; const optimizer: string): boolean;
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function OptPass1Shift(var p: tai): boolean;
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@ -291,6 +295,24 @@ Implementation
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end;
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function TCpuAsmOptimizer.OptPass1LDR(var p: tai): Boolean;
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begin
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Result := False;
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if inherited OptPass1LDR(p) or
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LookForPostindexedPattern(p) then
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Exit(True);
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end;
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function TCpuAsmOptimizer.OptPass1STR(var p: tai): Boolean;
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begin
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Result := False;
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if inherited OptPass1STR(p) or
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LookForPostindexedPattern(p) then
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Exit(True);
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end;
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function TCpuAsmOptimizer.OptPass1Shift(var p : tai): boolean;
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var
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hp1,hp2: tai;
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@ -764,9 +786,10 @@ Implementation
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if p.typ=ait_instruction then
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begin
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case taicpu(p).opcode of
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A_LDR,
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A_LDR:
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Result:=OptPass1LDR(p);
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A_STR:
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Result:=LookForPostindexedPattern(p);
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Result:=OptPass1STR(p);
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A_MOV:
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Result:=OptPass1Mov(p);
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A_STP:
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@ -59,7 +59,11 @@ Type
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function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
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function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
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function OptPass1And(var p: tai): Boolean; override; { There's optimisation code that's general for all ARM platforms }
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{ With these routines, there's optimisation code that's general for all ARM platforms }
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function OptPass1And(var p: tai): Boolean; override;
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function OptPass1LDR(var p: tai): Boolean; override;
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function OptPass1STR(var p: tai): Boolean; override;
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protected
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function LookForPreindexedPattern(p: taicpu): boolean;
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function LookForPostindexedPattern(p: taicpu): boolean;
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@ -69,9 +73,7 @@ Type
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function OptPass1DataCheckMov(var p: tai): Boolean;
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function OptPass1ADDSUB(var p: tai): Boolean;
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function OptPass1CMP(var p: tai): Boolean;
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function OptPass1LDR(var p: tai): Boolean;
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function OptPass1STM(var p: tai): Boolean;
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function OptPass1STR(var p: tai): Boolean;
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function OptPass1MOV(var p: tai): Boolean;
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function OptPass1MUL(var p: tai): Boolean;
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function OptPass1MVN(var p: tai): Boolean;
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@ -834,7 +836,9 @@ Implementation
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var
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hp1: tai;
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begin
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Result := False;
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Result := inherited OptPass1LDR(p);
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if Result then
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Exit;
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{ change
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ldr reg1,ref
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@ -1022,7 +1026,9 @@ Implementation
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var
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hp1: tai;
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begin
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Result := False;
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Result := inherited OptPass1STR(p);
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if Result then
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Exit;
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{ Common conditions }
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if (taicpu(p).oper[1]^.typ = top_ref) and
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@ -26,7 +26,7 @@ Unit aoptarm;
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{$i fpcdefs.inc}
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{ $define DEBUG_PREREGSCHEDULER}
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{ $define DEBUG_AOPTCPU}
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{$define DEBUG_AOPTCPU}
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Interface
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@ -41,12 +41,15 @@ Type
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function RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string): boolean;
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function RedundantMovProcess(var p: tai; var hp1: tai): boolean;
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function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
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function GetNextInstructionUsingReg(Current: tai; out Next: tai; const reg: TRegister): Boolean;
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function OptPass1UXTB(var p: tai): Boolean;
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function OptPass1UXTH(var p: tai): Boolean;
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function OptPass1SXTB(var p: tai): Boolean;
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function OptPass1SXTH(var p: tai): Boolean;
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function OptPass1LDR(var p: tai): Boolean; virtual;
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function OptPass1STR(var p: tai): Boolean; virtual;
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function OptPass1And(var p: tai): Boolean; virtual;
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End;
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@ -69,15 +72,23 @@ Implementation
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systems,
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cpuinfo,
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cgobj,procinfo,
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aasmbase,aasmdata;
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aasmbase,aasmdata,itcpugas;
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{$ifdef DEBUG_AOPTCPU}
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const
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SPeepholeOptimization: shortstring = 'Peephole Optimization: ';
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procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);
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begin
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asml.insertbefore(tai_comment.Create(strpnew(s)), p);
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end;
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{$else DEBUG_AOPTCPU}
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{ Empty strings help the optimizer to remove string concatenations that won't
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ever appear to the user on release builds. [Kit] }
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const
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SPeepholeOptimization = '';
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procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);inline;
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begin
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end;
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@ -179,7 +190,7 @@ Implementation
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function TARMAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
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Out Next: tai; reg: TRegister): Boolean;
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Out Next: tai; const reg: TRegister): Boolean;
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var
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gniResult: Boolean;
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begin
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@ -395,7 +406,14 @@ Implementation
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UpdateUsedRegs(TmpUsedRegs, tai(current_hp.Next));
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LDRChange := False;
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if (taicpu(next_hp).opcode in [A_LDR,A_STR]) and (taicpu(next_hp).ops = 2) then
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if (taicpu(next_hp).opcode in [A_LDR,A_STR]) and (taicpu(next_hp).ops = 2)
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{$ifdef AARCH64}
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{ If r0 is the zero register, then this sequence of instructions will cause
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an access violation, but that's better than an assembler error caused by
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changing r0 to xzr inside the reference (Where it's illegal). [Kit] }
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and (getsupreg(taicpu(p).oper[1]^.reg) <> RS_XZR)
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{$endif AARCH64}
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then
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begin
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{ Change the registers from r1 to r0 }
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@ -1018,6 +1036,201 @@ Implementation
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end;
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function TARMAsmOptimizer.OptPass1LDR(var p : tai) : Boolean;
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var
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hp1: tai;
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Reference: TReference;
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NewOp: TAsmOp;
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begin
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Result := False;
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if (taicpu(p).ops <> 2) or (taicpu(p).condition <> C_None) then
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Exit;
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Reference := taicpu(p).oper[1]^.ref^;
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if (Reference.addressmode = AM_OFFSET) and
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not RegInRef(taicpu(p).oper[0]^.reg, Reference) and
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{ Delay calling GetNextInstruction for as long as possible }
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GetNextInstruction(p, hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).condition = C_None) and
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(taicpu(hp1).oppostfix = taicpu(p).oppostfix) then
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begin
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if (taicpu(hp1).opcode = A_STR) and
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RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) and
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(getregtype(taicpu(p).oper[0]^.reg) = getregtype(taicpu(hp1).oper[0]^.reg)) then
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begin
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{ With:
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ldr reg1,[ref]
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str reg2,[ref]
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If reg1 = reg2, Remove str
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}
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if taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed redundant store instruction (load/store -> load/nop)', hp1);
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RemoveInstruction(hp1);
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Result := True;
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Exit;
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end;
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end
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else if (taicpu(hp1).opcode = A_LDR) and
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RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) then
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begin
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{ With:
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ldr reg1,[ref]
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ldr reg2,[ref]
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If reg1 = reg2, delete the second ldr
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If reg1 <> reg2, changing the 2nd ldr to a mov might introduce
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a dependency, but it will likely open up new optimisations, so
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do it for now and handle any new dependencies later.
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}
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if taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed duplicate load instruction (load/load -> load/nop)', hp1);
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RemoveInstruction(hp1);
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Result := True;
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Exit;
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end
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else if
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(getregtype(taicpu(p).oper[0]^.reg) = R_INTREGISTER) and
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(getregtype(taicpu(hp1).oper[0]^.reg) = R_INTREGISTER) and
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(getsubreg(taicpu(p).oper[0]^.reg) = getsubreg(taicpu(hp1).oper[0]^.reg)) then
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begin
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DebugMsg(SPeepholeOptimization + 'Changed second ldr' + oppostfix2str[taicpu(hp1).oppostfix] + ' to mov (load/load -> load/move)', hp1);
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taicpu(hp1).opcode := A_MOV;
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taicpu(hp1).oppostfix := PF_None;
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taicpu(hp1).loadreg(1, taicpu(p).oper[0]^.reg);
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AllocRegBetween(taicpu(p).oper[0]^.reg, p, hp1, UsedRegs);
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Result := True;
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Exit;
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end;
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end;
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end;
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end;
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function TARMAsmOptimizer.OptPass1STR(var p : tai) : Boolean;
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var
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hp1: tai;
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Reference: TReference;
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SizeMismatch: Boolean;
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SrcReg: TRegister;
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NewOp: TAsmOp;
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begin
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Result := False;
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if (taicpu(p).ops <> 2) or (taicpu(p).condition <> C_None) then
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Exit;
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Reference := taicpu(p).oper[1]^.ref^;
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if (Reference.addressmode = AM_OFFSET) and
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not RegInRef(taicpu(p).oper[0]^.reg, Reference) and
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{ Delay calling GetNextInstruction for as long as possible }
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GetNextInstruction(p, hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).condition = C_None) and
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(taicpu(hp1).oppostfix = taicpu(p).oppostfix) then
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if GetNextInstruction(p, hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).condition = C_None) then
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begin
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{ Saves constant dereferencing and makes it easier to change the size if necessary }
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SrcReg := taicpu(p).oper[0]^.reg;
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if (taicpu(hp1).opcode = A_LDR) and
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RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) and
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(
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(taicpu(hp1).oppostfix = taicpu(p).oppostfix) or
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((taicpu(p).oppostfix = PF_B) and (taicpu(hp1).oppostfix = PF_SB)) or
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((taicpu(p).oppostfix = PF_H) and (taicpu(hp1).oppostfix = PF_SH))
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{$ifdef AARCH64}
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or ((taicpu(p).oppostfix = PF_W) and (taicpu(hp1).oppostfix = PF_SW))
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{$endif AARCH64}
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) then
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begin
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{ With:
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str reg1,[ref]
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ldr reg2,[ref]
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If reg1 = reg2, Remove ldr.
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If reg1 <> reg2, replace ldr with "mov reg2,reg1"
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}
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if (SrcReg = taicpu(hp1).oper[0]^.reg) and
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{ e.g. the ldrb in strb/ldrb is not a null operation as it clears the upper 24 bits }
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(taicpu(p).oppostfix=PF_None) then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed redundant load instruction (store/load -> store/nop)', hp1);
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RemoveInstruction(hp1);
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Result := True;
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Exit;
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end
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else if (getregtype(taicpu(p).oper[0]^.reg) = R_INTREGISTER) and
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(getregtype(taicpu(hp1).oper[0]^.reg) = R_INTREGISTER) and
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(getsubreg(taicpu(p).oper[0]^.reg) = getsubreg(taicpu(hp1).oper[0]^.reg)) then
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begin
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case taicpu(hp1).oppostfix of
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PF_B:
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NewOp := A_UXTB;
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PF_SB:
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NewOp := A_SXTB;
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PF_H:
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NewOp := A_UXTH;
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PF_SH:
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NewOp := A_SXTH;
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{$ifdef AARCH64}
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PF_SW:
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NewOp := A_SXTW;
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PF_W,
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{$endif AARCH64}
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PF_None:
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NewOp := A_MOV;
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else
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InternalError(2021043001);
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end;
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DebugMsg(SPeepholeOptimization + 'Changed ldr' + oppostfix2str[taicpu(hp1).oppostfix] + ' to ' + gas_op2str[NewOp] + ' (store/load -> store/move)', hp1);
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taicpu(hp1).oppostfix := PF_None;
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taicpu(hp1).opcode := NewOp;
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taicpu(hp1).loadreg(1, taicpu(p).oper[0]^.reg);
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AllocRegBetween(taicpu(p).oper[0]^.reg, p, hp1, UsedRegs);
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Result := True;
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Exit;
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end;
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end
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else if (taicpu(hp1).opcode = A_STR) and
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RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) then
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begin
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{ With:
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str reg1,[ref]
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str reg2,[ref]
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If reg1 <> reg2, delete the first str
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IF reg1 = reg2, delete the second str
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}
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if SrcReg = taicpu(hp1).oper[0]^.reg then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed duplicate store instruction (store/store -> store/nop)', hp1);
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RemoveInstruction(hp1);
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Result := True;
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Exit;
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end
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else if
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{ Registers same byte size? }
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(tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)] = tcgsize2size[reg_cgsize(taicpu(hp1).oper[0]^.reg)]) then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed dominated store instruction (store/store -> nop/store)', p);
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RemoveCurrentP(p, hp1);
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Result := True;
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Exit;
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end;
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end;
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end;
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end;
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function TARMAsmOptimizer.OptPass1And(var p : tai) : Boolean;
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var
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hp1, hp2: tai;
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