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* Made the x86-specific scalefactor optimization of tvecnode available on x86_64 as well, by moving update_reference_reg_mul method from ti386vecnode to newly introduced tx86vecnode.
git-svn-id: trunk@19245 -
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sergei
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e2357b5809
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@ -627,6 +627,7 @@ compiler/x86/nx86cnv.pas svneol=native#text/plain
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compiler/x86/nx86con.pas svneol=native#text/plain
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compiler/x86/nx86inl.pas svneol=native#text/plain
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compiler/x86/nx86mat.pas svneol=native#text/plain
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compiler/x86/nx86mem.pas svneol=native#text/plain
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compiler/x86/nx86set.pas svneol=native#text/plain
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compiler/x86/rax86.pas svneol=native#text/plain
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compiler/x86/rax86att.pas svneol=native#text/plain
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@ -28,7 +28,7 @@ interface
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uses
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globtype,
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cgbase,cpuinfo,cpubase,
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node,nmem,ncgmem;
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node,nmem,ncgmem,nx86mem;
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type
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ti386addrnode = class(tcgaddrnode)
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@ -39,8 +39,7 @@ interface
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procedure pass_generate_code;override;
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end;
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ti386vecnode = class(tcgvecnode)
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procedure update_reference_reg_mul(maybe_const_reg:tregister;l:aint);override;
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ti386vecnode = class(tx86vecnode)
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procedure pass_generate_code;override;
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end;
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@ -84,65 +83,6 @@ implementation
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TI386VECNODE
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*****************************************************************************}
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{ this routine must, like any other routine, not change the contents }
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{ of base/index registers of references, as these may be regvars. }
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{ The register allocator can coalesce one LOC_REGISTER being moved }
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{ into another (as their live ranges won't overlap), but not a }
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{ LOC_CREGISTER moved into a LOC_(C)REGISTER most of the time (as }
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{ the live range of the LOC_CREGISTER will most likely overlap the }
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{ the live range of the target LOC_(C)REGISTER) }
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{ The passed register may be a LOC_CREGISTER as well. }
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procedure ti386vecnode.update_reference_reg_mul(maybe_const_reg:tregister;l:aint);
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var
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l2 : integer;
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hreg : tregister;
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begin
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{ Optimized for x86 to use the index register and scalefactor }
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if location.reference.index=NR_NO then
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begin
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{ no preparations needed }
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end
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else if location.reference.base=NR_NO then
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begin
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if (location.reference.scalefactor > 1) then
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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case location.reference.scalefactor of
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0,1 : hreg:=location.reference.index;
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2 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,1,location.reference.index,hreg);
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4 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,2,location.reference.index,hreg);
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8 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,3,location.reference.index,hreg);
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else
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internalerror(2008091401);
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end;
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location.reference.base:=hreg;
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end
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else
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,location.reference,hreg);
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reference_reset_base(location.reference,hreg,0,location.reference.alignment);
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end;
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{ insert the new index register and scalefactor or
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do the multiplication manual }
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case l of
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1,2,4,8 :
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begin
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location.reference.scalefactor:=l;
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hreg:=maybe_const_reg;
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end;
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else
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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if ispowerof2(l,l2) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,l2,maybe_const_reg,hreg)
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,maybe_const_reg,hreg);
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end;
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end;
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location.reference.index:=hreg;
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end;
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procedure ti386vecnode.pass_generate_code;
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begin
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inherited pass_generate_code;
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108
compiler/x86/nx86mem.pas
Normal file
108
compiler/x86/nx86mem.pas
Normal file
@ -0,0 +1,108 @@
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{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate x86 assembler for in memory related nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86mem;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,
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cgbase,cpuinfo,cpubase,
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node,nmem,ncgmem;
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type
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tx86vecnode = class(tcgvecnode)
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procedure update_reference_reg_mul(maybe_const_reg:tregister;l:aint);override;
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end;
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implementation
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uses
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cutils,verbose,
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aasmtai,aasmdata,
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cgutils,cgobj;
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{*****************************************************************************
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TX86VECNODE
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*****************************************************************************}
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{ this routine must, like any other routine, not change the contents }
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{ of base/index registers of references, as these may be regvars. }
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{ The register allocator can coalesce one LOC_REGISTER being moved }
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{ into another (as their live ranges won't overlap), but not a }
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{ LOC_CREGISTER moved into a LOC_(C)REGISTER most of the time (as }
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{ the live range of the LOC_CREGISTER will most likely overlap the }
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{ the live range of the target LOC_(C)REGISTER) }
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{ The passed register may be a LOC_CREGISTER as well. }
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procedure tx86vecnode.update_reference_reg_mul(maybe_const_reg:tregister;l:aint);
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var
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l2 : integer;
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hreg : tregister;
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begin
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{ Optimized for x86 to use the index register and scalefactor }
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if location.reference.index=NR_NO then
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begin
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{ no preparations needed }
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end
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else if location.reference.base=NR_NO then
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begin
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if (location.reference.scalefactor > 1) then
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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case location.reference.scalefactor of
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0,1 : hreg:=location.reference.index;
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2 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,1,location.reference.index,hreg);
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4 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,2,location.reference.index,hreg);
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8 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,3,location.reference.index,hreg);
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else
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internalerror(2008091401);
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end;
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location.reference.base:=hreg;
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end
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else
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,location.reference,hreg);
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reference_reset_base(location.reference,hreg,0,location.reference.alignment);
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end;
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{ insert the new index register and scalefactor or
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do the multiplication manual }
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case l of
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1,2,4,8 :
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begin
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location.reference.scalefactor:=l;
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hreg:=maybe_const_reg;
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end;
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else
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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if ispowerof2(l,l2) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,l2,maybe_const_reg,hreg)
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,maybe_const_reg,hreg);
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end;
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end;
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location.reference.index:=hreg;
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end;
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begin
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cvecnode:=tx86vecnode;
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end.
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@ -49,6 +49,7 @@ unit cpunode;
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get the correct class pointer }
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nx86set,
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nx86con,
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nx86mem,
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nx64add,
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nx64cal,
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nx64cnv,
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