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Introduce split_into_shifter_const to ARM-Code Generator

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This functions tries to split up a 32-bit value into two shifter
constants. This approach finds a broader range for two shifter constant
combinations.

git-svn-id: trunk@21645 -
This commit is contained in:
masta 2012-06-18 16:59:19 +00:00
parent 3205169ab9
commit d987cee96a
1 changed files with 25 additions and 0 deletions
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25
compiler/arm/cpubase.pas
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@ -347,6 +347,7 @@ unit cpubase;
function is_pc(const r : tregister) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
function is_shifter_const(d : aint;var imm_shift : byte) : boolean;
function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword):boolean;
function dwarf_reg(r:tregister):shortint;
implementation
@ -528,6 +529,30 @@ unit cpubase;
result:=false;
end;
function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword) : boolean;
var
d, i, i2: Dword;
begin
Result:=false;
{Thumb2 is not supported (YET?)}
if current_settings.cputype in cpu_thumb2 then exit;
d:=DWord(value);
for i:=0 to 15 do
begin
imm1:=d and rordword($FF, I*2);
imm2:=d and not (imm1); {remove already found bits}
{is the remainder a shifterconst? YAY! we've done it!}
{Could we start from i instead of 0?}
for i2:=0 to 15 do
begin
if (imm2 and not(rordword($FF,i2*2)))=0 then
begin
result:=true;
exit;
end;
end;
end;
end;
function dwarf_reg(r:tregister):shortint;
begin