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* AAarch64: handle initializations of vector registers with zero properly

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git-svn-id: trunk@45740 -
This commit is contained in:
florian 2020-07-07 20:56:19 +00:00
parent f65f1bd802
commit d9d231c875
1 changed files with 16 additions and 9 deletions
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25
compiler/aarch64/cgcpu.pas
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@ -1129,17 +1129,24 @@ implementation
{ "xor Vx,Vx" is used to initialize global regvars to 0 } { "xor Vx,Vx" is used to initialize global regvars to 0 }
OP_XOR: OP_XOR:
begin begin
if (src<>dst) or if shuffle=nil then
begin
dst:=newreg(R_MMREGISTER,getsupreg(dst),R_SUBMM16B);
src:=newreg(R_MMREGISTER,getsupreg(dst),R_SUBMM16B);
list.concat(taicpu.op_reg_reg_reg(A_EOR,dst,dst,src))
end
else if (src<>dst) or
(reg_cgsize(src)<>size) or (reg_cgsize(src)<>size) or
assigned(shuffle) then assigned(shuffle) then
internalerror(2015011401); internalerror(2015011401)
case size of else
OS_F32, case size of
OS_F64: OS_F32,
list.concat(taicpu.op_reg_const(A_MOVI,makeregsize(dst,OS_F64),0)); OS_F64:
else list.concat(taicpu.op_reg_const(A_MOVI,makeregsize(dst,OS_F64),0));
internalerror(2015011402); else
end; internalerror(2015011402);
end;
end end
else else
internalerror(2015011403); internalerror(2015011403);