paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-08-22 11:29:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

* AAarch64: handle initializations of vector registers with zero properly

Browse Source 
git-svn-id: trunk@45740 -
This commit is contained in:
florian 2020-07-07 20:56:19 +00:00
parent f65f1bd802
commit d9d231c875
1 changed files with 16 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
compiler/aarch64/cgcpu.pas
View File

@ -1129,17 +1129,24 @@ implementation
{ "xor Vx,Vx" is used to initialize global regvars to 0 }
OP_XOR:
begin
if (src<>dst) or
if shuffle=nil then
begin
dst:=newreg(R_MMREGISTER,getsupreg(dst),R_SUBMM16B);
src:=newreg(R_MMREGISTER,getsupreg(dst),R_SUBMM16B);
list.concat(taicpu.op_reg_reg_reg(A_EOR,dst,dst,src))
end
else if (src<>dst) or
(reg_cgsize(src)<>size) or
assigned(shuffle) then
internalerror(2015011401);
case size of
OS_F32,
OS_F64:
list.concat(taicpu.op_reg_const(A_MOVI,makeregsize(dst,OS_F64),0));
else
internalerror(2015011402);
end;
internalerror(2015011401)
else
case size of
OS_F32,
OS_F64:
list.concat(taicpu.op_reg_const(A_MOVI,makeregsize(dst,OS_F64),0));
else
internalerror(2015011402);
end;
end
else
internalerror(2015011403);