From da6c0e919b9846586a59ccfb77a698b2093b3b80 Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Sat, 22 Feb 2025 21:56:46 +0100
Subject: [PATCH]   + RiscV: rv32gcb

---
 compiler/riscv/agrvgas.pas   | 4 ++--
 compiler/riscv32/cpuinfo.pas | 9 ++++++---
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/compiler/riscv/agrvgas.pas b/compiler/riscv/agrvgas.pas
index fdada98b17..780694a7ab 100644
--- a/compiler/riscv/agrvgas.pas
+++ b/compiler/riscv/agrvgas.pas
@@ -233,8 +233,8 @@ unit agrvgas;
       const
         arch_str: array[boolean,tcputype] of string[18] = (
 {$ifdef RISCV32}
-          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imafd','rv32ec','rv32gc'),
-          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc')
+          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imafd','rv32ec','rv32gc','rv32gc_zba_zbb_zbs'),
+          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc','rv32gc_zba_zbb_zbs')
 {$endif RISCV32}
 {$ifdef RISCV64}
           ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs'),
diff --git a/compiler/riscv32/cpuinfo.pas b/compiler/riscv32/cpuinfo.pas
index 34d0f57ae9..6b6b3ccf58 100644
--- a/compiler/riscv32/cpuinfo.pas
+++ b/compiler/riscv32/cpuinfo.pas
@@ -44,7 +44,8 @@ Type
        cpu_rv32imafdc,
        cpu_rv32imafd,
        cpu_rv32ec,
-       cpu_rv32gc
+       cpu_rv32gc,
+       cpu_rv32gcb
       );
 
    tfputype =
@@ -178,7 +179,8 @@ Const
      'RV32IMAFDC',
      'RV32IMAFD',
      'RV32EC',
-     'RV32GC'
+     'RV32GC',
+     'RV32GCB'
    );
 
    fputypestr : array[tfputype] of string[8] = (         
@@ -241,7 +243,8 @@ Const
        { cpu_rv32imafdc} [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32imafd } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT],
-       { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D]
+       { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
+       { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D,CPURV_HAS_ZBA,CPURV_HAS_ZBB,CPURV_HAS_ZBS]
      );
 
 Implementation