From d41579fb2b8c8a5c35d280065944a2fa4aee3d7a Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 17 Nov 2020 16:22:27 +0000 Subject: [PATCH 001/116] bugfix gnu-assembler platform i386 vcvtsi2sd,vcvtsi2ss,vcvtusi2sd,vcvtusi2ss git-svn-id: branches/tg74/avx512-0037785@47441 - --- compiler/i386/i386atts.inc | 8 ++-- compiler/i386/i386nop.inc | 2 +- compiler/i386/i386tab.inc | 65 ++++++++++++++++++---------- compiler/i8086/i8086atts.inc | 8 ++-- compiler/i8086/i8086nop.inc | 2 +- compiler/i8086/i8086tab.inc | 65 ++++++++++++++++++---------- compiler/utils/mkx86ins.pp | 5 +++ compiler/x86/itcpugas.pas | 2 +- compiler/x86/rax86.pas | 15 +++++-- compiler/x86/rax86att.pas | 2 +- compiler/x86/x86ins.dat | 46 +++++++++++++------- compiler/x86_64/x8664ats.inc | 8 ++-- compiler/x86_64/x8664nop.inc | 2 +- compiler/x86_64/x8664tab.inc | 79 +++++++++++++++++++++------------- tests/utils/avx/avxopcodes.pas | 12 ++++-- 15 files changed, 208 insertions(+), 113 deletions(-) diff --git a/compiler/i386/i386atts.inc b/compiler/i386/i386atts.inc index 8380141e9d..f25a0a1855 100644 --- a/compiler/i386/i386atts.inc +++ b/compiler/i386/i386atts.inc @@ -789,8 +789,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufMMX, @@ -1215,8 +1215,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufMMX, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/i386/i386nop.inc b/compiler/i386/i386nop.inc index 4d7b5a2b20..4e2e16f488 100644 --- a/compiler/i386/i386nop.inc +++ b/compiler/i386/i386nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4165; +4168; diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc index 8f37a58747..b84ebfeda2 100644 --- a/compiler/i386/i386tab.inc +++ b/compiler/i386/i386tab.inc @@ -10839,30 +10839,44 @@ ( opcode : A_VCVTSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] + ), + ( + opcode : A_VCVTSI2SD; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #220#232#234#242#243#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] + ), + ( + opcode : A_VCVTSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #219#232#234#242#243#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSS2SD; @@ -22291,36 +22305,43 @@ ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); - code : #220#232#234#248#1#123#61#80; - flags : [if_avx512,if_t1s] - ), - ( - opcode : A_VCVTUSI2SD; - ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg64,ot_none); - code : #220#232#234#248#1#123#61#80; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); + code : #220#232#248#1#123#61#80; flags : [if_avx512] ), ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #220#232#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( - opcode : A_VCVTUSI2SS; + opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits64,ot_none); - code : #219#232#234#248#1#123#61#80; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #220#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( opcode : A_VCVTUSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#248#1#123#61#80; + flags : [if_avx512] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); + code : #219#232#248#1#123#61#80; + flags : [if_avx512,if_t1s] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #219#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( diff --git a/compiler/i8086/i8086atts.inc b/compiler/i8086/i8086atts.inc index 98781350f4..14d8ee5011 100644 --- a/compiler/i8086/i8086atts.inc +++ b/compiler/i8086/i8086atts.inc @@ -789,8 +789,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufMMX, @@ -1229,8 +1229,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufMMX, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/i8086/i8086nop.inc b/compiler/i8086/i8086nop.inc index 3046f29d6b..ceb214a46f 100644 --- a/compiler/i8086/i8086nop.inc +++ b/compiler/i8086/i8086nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4197; +4200; diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc index 59efdf6c71..59a948a851 100644 --- a/compiler/i8086/i8086tab.inc +++ b/compiler/i8086/i8086tab.inc @@ -10867,30 +10867,44 @@ ( opcode : A_VCVTSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] + ), + ( + opcode : A_VCVTSI2SD; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #220#232#234#242#243#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] + ), + ( + opcode : A_VCVTSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #219#232#234#242#243#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSS2SD; @@ -22515,36 +22529,43 @@ ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); - code : #220#232#234#248#1#123#61#80; - flags : [if_avx512,if_t1s] - ), - ( - opcode : A_VCVTUSI2SD; - ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg64,ot_none); - code : #220#232#234#248#1#123#61#80; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); + code : #220#232#248#1#123#61#80; flags : [if_avx512] ), ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #220#232#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( - opcode : A_VCVTUSI2SS; + opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits64,ot_none); - code : #219#232#234#248#1#123#61#80; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #220#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( opcode : A_VCVTUSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#248#1#123#61#80; + flags : [if_avx512] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); + code : #219#232#248#1#123#61#80; + flags : [if_avx512,if_t1s] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #219#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( diff --git a/compiler/utils/mkx86ins.pp b/compiler/utils/mkx86ins.pp index 6e01fce032..791070347e 100644 --- a/compiler/utils/mkx86ins.pp +++ b/compiler/utils/mkx86ins.pp @@ -325,6 +325,11 @@ begin dec(attopcode[0]); attsuffix:='attsufMMX'; end; + 'S' : + begin + dec(attopcode[0]); + attsuffix:='attsufMMS'; + end; 'X' : begin dec(attopcode[0]); diff --git a/compiler/x86/itcpugas.pas b/compiler/x86/itcpugas.pas index d5c058502d..14972b4f69 100644 --- a/compiler/x86/itcpugas.pas +++ b/compiler/x86/itcpugas.pas @@ -29,7 +29,7 @@ interface cgbase,cpubase; type - TAttSuffix = (AttSufNONE,AttSufINT,AttSufFPU,AttSufFPUint,AttSufINTdual,AttSufMM,AttSufMMX); + TAttSuffix = (AttSufNONE,AttSufINT,AttSufFPU,AttSufFPUint,AttSufINTdual,AttSufMM,AttSufMMX,AttSufMMS); const { include mnemonic strings } diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index c5fb0e3060..532d3b8e1e 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -239,7 +239,7 @@ begin ; end; end - else if gas_needsuffix[opcode] in [AttSufMM, AttSufMMX] then + else if gas_needsuffix[opcode] in [AttSufMM, AttSufMMX, AttSufMMS] then begin if (opr.typ=OPR_Reference) then begin @@ -1469,7 +1469,16 @@ procedure Tx86Instruction.SetInstructionOpsize; result := true; end; end; - end; + end + else if gas_needsuffix[opcode] = AttSufMMS then + begin + // spezial handling - use source operand + if ops > 0 then + begin + opsize:=tx86operand(operands[1]).opsize; + result := true; + end; + end; end; end; end; @@ -1569,7 +1578,7 @@ begin //A_VCVTSI2SD, //A_VCVTUSI2SS, //A_VCVTUSI2SD: - // iops:=tx86operand(operands[1]).opsize; + // opsize:=tx86operand(operands[1]).opsize; //A_VFPCLASSPD, //A_VFPCLASSPS: // iops:=tx86operand(operands[2]).opsize; diff --git a/compiler/x86/rax86att.pas b/compiler/x86/rax86att.pas index 062661d601..6621020975 100644 --- a/compiler/x86/rax86att.pas +++ b/compiler/x86/rax86att.pas @@ -1039,7 +1039,7 @@ Implementation actopsize:=att_sizefpusuffix[sufidx] else if gas_needsuffix[actopcode]=attsufFPUint then actopsize:=att_sizefpuintsuffix[sufidx] - else if gas_needsuffix[actopcode]=attsufMM then + else if gas_needsuffix[actopcode]in[attsufMM,attsufMMS] then actopsize:=att_sizemmsuffix[sufidx] else if gas_needsuffix[actopcode]=attsufMMX then actopsize:=att_sizemmXsuffix[sufidx] diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index 6222ca29ce..deda5d6155 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -4259,20 +4259,27 @@ xmmreg_mz,xmmreg,mem64 \334\350\352\362\370\1\x5A\75\120 xmmreg_mz,xmmreg,xmmreg_er \334\350\352\362\370\1\x5A\75\120 AVX,SANDYBRIDGE -[VCVTSI2SD,vcvtsi2sdX] + +; special handling - gas suffix "S" =>> instructions-opsize = source-operand +[VCVTSI2SD,vcvtsi2sdS] (Ch_Wop3, Ch_Rop2, Ch_Rop1) -xmmreg,xmmreg,reg32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD -xmmreg,xmmreg,mem32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD,T1S +;xmmreg,xmmreg,reg32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD +;xmmreg,xmmreg,mem32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD,T1S +;xmmreg,xmmreg_er,reg64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64 +;xmmreg,xmmreg_er,mem64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64,T1S +xmmreg,xmmreg_er,reg32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE xmmreg,xmmreg_er,reg64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64 -xmmreg,xmmreg_er,mem64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64,T1S +xmmreg,xmmreg_er,mem32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,T1S +xmmreg,xmmreg_er,mem64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,T1S -[VCVTSI2SS,vcvtsi2ssX] +; special handling - gas suffix "S" =>> instructions-opsize = source-operand +[VCVTSI2SS,vcvtsi2ssS] (Ch_Wop3, Ch_Rop2, Ch_Rop1) -xmmreg,xmmreg,reg32 \333\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD -xmmreg,xmmreg,mem32 \333\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD,T1S +xmmreg,xmmreg_er,reg32 \333\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE xmmreg,xmmreg_er,reg64 \333\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64 -xmmreg,xmmreg_er,mem64 \333\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64,T1S +xmmreg,xmmreg_er,mem32 \333\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,T1S +xmmreg,xmmreg_er,mem64 \333\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,T1S [VCVTSS2SD] @@ -7507,16 +7514,23 @@ ymmreg_mz,mem512 \334\350\351\352\370\1\x7A\110 ymmreg_mz,bmem64 \334\350\351\352\370\1\x7A\110 AVX512,BCST8,TFV ymmreg_mz,zmmreg_er \334\350\351\352\370\1\x7A\110 AVX512 -[VCVTUSI2SD,vcvtusi2sdX] -(Ch_All) -xmmreg,xmmreg_er,mem64 \334\350\352\370\1\x7B\75\120 AVX512,T1S -xmmreg,xmmreg_er,reg64 \334\350\352\370\1\x7B\75\120 AVX512 -xmmreg,xmmreg_er,rm32 \334\350\370\1\x7B\75\120 AVX512,T1S -[VCVTUSI2SS,vcvtusi2ssX] +; special handling - gas suffix "S" =>> instructions-opsize = source-operand +[VCVTUSI2SD,vcvtusi2sdS] (Ch_All) -xmmreg,xmmreg_er,rm64 \333\350\352\370\1\x7B\75\120 AVX512,T1S -xmmreg,xmmreg_er,rm32 \333\350\370\1\x7B\75\120 AVX512,T1S +xmmreg,xmmreg_er,reg32 \334\350\370\1\x7B\75\120 AVX512 +xmmreg,xmmreg_er,reg64 \334\350\352\370\1\x7B\75\120 AVX512,X86_64 +xmmreg,xmmreg_er,mem32 \334\350\370\1\x7B\75\120 AVX512,T1S +xmmreg,xmmreg_er,mem64 \334\350\352\370\1\x7B\75\120 AVX512,T1S + + +; special handling - gas suffix "S" =>> instructions-opsize = source-operand +[VCVTUSI2SS,vcvtusi2ssS] +(Ch_All) +xmmreg,xmmreg_er,reg32 \333\350\370\1\x7B\75\120 AVX512 +xmmreg,xmmreg_er,reg64 \333\350\352\370\1\x7B\75\120 AVX512,X86_64 +xmmreg,xmmreg_er,mem32 \333\350\370\1\x7B\75\120 AVX512,T1S +xmmreg,xmmreg_er,mem64 \333\350\352\370\1\x7B\75\120 AVX512,T1S [VDBPSADBW] (Ch_All) diff --git a/compiler/x86_64/x8664ats.inc b/compiler/x86_64/x8664ats.inc index 9b94745159..5b2fade508 100644 --- a/compiler/x86_64/x8664ats.inc +++ b/compiler/x86_64/x8664ats.inc @@ -785,8 +785,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufMMX, @@ -1211,8 +1211,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufMMX, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/x86_64/x8664nop.inc b/compiler/x86_64/x8664nop.inc index 57ebecfccb..99f9877d90 100644 --- a/compiler/x86_64/x8664nop.inc +++ b/compiler/x86_64/x8664nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4229; +4232; diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc index 501b7f7f8f..978443453a 100644 --- a/compiler/x86_64/x8664tab.inc +++ b/compiler/x86_64/x8664tab.inc @@ -11140,16 +11140,9 @@ ( opcode : A_VCVTSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] - ), - ( - opcode : A_VCVTSI2SD; - ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); - code : #220#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SD; @@ -11158,26 +11151,26 @@ code : #220#232#234#242#243#248#1#42#61#80; flags : [if_avx,if_sandybridge,if_x86_64] ), + ( + opcode : A_VCVTSI2SD; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); + code : #220#232#242#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] + ), ( opcode : A_VCVTSI2SD; ops : 3; optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); code : #220#232#234#242#243#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_x86_64,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_reg32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd] - ), - ( - opcode : A_VCVTSI2SS; - ops : 3; - optypes : (ot_xmmreg,ot_xmmreg,ot_memory or ot_bits32,ot_none); - code : #219#232#242#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_sd,if_t1s] + flags : [if_avx,if_sandybridge] ), ( opcode : A_VCVTSI2SS; @@ -11186,12 +11179,19 @@ code : #219#232#234#242#243#248#1#42#61#80; flags : [if_avx,if_sandybridge,if_x86_64] ), + ( + opcode : A_VCVTSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); + code : #219#232#242#248#1#42#61#80; + flags : [if_avx,if_sandybridge,if_t1s] + ), ( opcode : A_VCVTSI2SS; ops : 3; optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); code : #219#232#234#242#243#248#1#42#61#80; - flags : [if_avx,if_sandybridge,if_x86_64,if_t1s] + flags : [if_avx,if_sandybridge,if_t1s] ), ( opcode : A_VCVTSS2SD; @@ -22739,36 +22739,57 @@ ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); - code : #220#232#234#248#1#123#61#80; - flags : [if_avx512,if_t1s] + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); + code : #220#232#248#1#123#61#80; + flags : [if_avx512] ), ( opcode : A_VCVTUSI2SD; ops : 3; optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg64,ot_none); code : #220#232#234#248#1#123#61#80; - flags : [if_avx512] + flags : [if_avx512,if_x86_64] ), ( opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); code : #220#232#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( - opcode : A_VCVTUSI2SS; + opcode : A_VCVTUSI2SD; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits64,ot_none); - code : #219#232#234#248#1#123#61#80; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #220#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( opcode : A_VCVTUSI2SS; ops : 3; - optypes : (ot_xmmreg,ot_xmmreg_er,ot_rm_gpr or ot_bits32,ot_none); + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg32,ot_none); code : #219#232#248#1#123#61#80; + flags : [if_avx512] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_reg64,ot_none); + code : #219#232#234#248#1#123#61#80; + flags : [if_avx512,if_x86_64] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits32,ot_none); + code : #219#232#248#1#123#61#80; + flags : [if_avx512,if_t1s] + ), + ( + opcode : A_VCVTUSI2SS; + ops : 3; + optypes : (ot_xmmreg,ot_xmmreg_er,ot_memory or ot_bits64,ot_none); + code : #219#232#234#248#1#123#61#80; flags : [if_avx512,if_t1s] ), ( diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 1167bba32d..559ebb8260 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -1923,10 +1923,14 @@ begin FOpCodeList.Add('vcvtuqq2ps,1,1,1,ymmreg_mz,mem512,,'); FOpCodeList.Add('vcvtuqq2ps,1,1,1,ymmreg_mz,8b64,,'); FOpCodeList.Add('vcvtuqq2ps,1,1,1,ymmreg_mz,zmmreg_er,,'); - FOpCodeList.Add('vcvtusi2sd,1,1,1,xmmreg,xmmreg_er,rm32,'); - FOpCodeList.Add('vcvtusi2sd,1,1,1,xmmreg,xmmreg_er,rm64,'); - FOpCodeList.Add('vcvtusi2ss,1,1,1,xmmreg,xmmreg_er,rm32,'); - FOpCodeList.Add('vcvtusi2ss,1,1,1,xmmreg,xmmreg_er,rm64,'); + FOpCodeList.Add('vcvtusi2sd,1,1,1,xmmreg,xmmreg_er,reg32,'); + FOpCodeList.Add('vcvtusi2sd,1,1,1,xmmreg,xmmreg_er,mem32,'); + FOpCodeList.Add('vcvtusi2sd,0,1,1,xmmreg,xmmreg_er,reg64,'); + FOpCodeList.Add('vcvtusi2sd,0,1,1,xmmreg,xmmreg_er,mem64,'); + FOpCodeList.Add('vcvtusi2ss,1,1,1,xmmreg,xmmreg_er,reg32,'); + FOpCodeList.Add('vcvtusi2ss,1,1,1,xmmreg,xmmreg_er,mem32,'); + FOpCodeList.Add('vcvtusi2ss,0,1,1,xmmreg,xmmreg_er,reg64,'); + FOpCodeList.Add('vcvtusi2ss,0,1,1,xmmreg,xmmreg_er,mem64,'); FOpCodeList.Add('vdbpsadbw,1,1,1,xmmreg_mz,xmmreg,xmmrm,imm8'); FOpCodeList.Add('vdbpsadbw,1,1,1,ymmreg_mz,ymmreg,ymmrm,imm8'); FOpCodeList.Add('vdbpsadbw,1,1,1,zmmreg_mz,zmmreg,zmmrm,imm8'); From 33b4772eab459420afb5788ee18e4f4c5d21efc7 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 18 Nov 2020 04:38:21 +0000 Subject: [PATCH 002/116] bugfix gnu-assembler platform i386 vcvtsi2sd,vcvtsi2ss,vcvtusi2sd,vcvtusi2ss git-svn-id: branches/tg74/avx512-0037785@47443 - --- compiler/x86/rax86.pas | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 532d3b8e1e..9547db0c21 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1455,7 +1455,15 @@ procedure Tx86Instruction.SetInstructionOpsize; end else begin - if MemRefSize in MemRefMultiples - [msiVMemMultiple] then + if (gas_needsuffix[opcode] = AttSufMMS) and (ops > 0) then + begin + // special handling = use source operand for calculate instructions-opsize + // e.g. vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss + + opsize:=tx86operand(operands[1]).opsize; + result := true; + end + else if MemRefSize in MemRefMultiples - [msiVMemMultiple] then begin case ops of 2: begin @@ -1469,16 +1477,7 @@ procedure Tx86Instruction.SetInstructionOpsize; result := true; end; end; - end - else if gas_needsuffix[opcode] = AttSufMMS then - begin - // spezial handling - use source operand - if ops > 0 then - begin - opsize:=tx86operand(operands[1]).opsize; - result := true; - end; - end; + end; end; end; end; From 912f8e8817dd15d27d7dddffcc471737c23050ef Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 25 Nov 2020 09:11:07 +0000 Subject: [PATCH 003/116] add new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47579 - --- tests/utils/avx/asmtestgenerator.pas | 718 +++++++++++++++++++++++++++ tests/utils/avx/avxopcodes.pas | 33 +- tests/utils/avx/avxtestgenerator.pp | 1 + tests/utils/avx/options.pas | 5 + 4 files changed, 753 insertions(+), 4 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 77783cfc8f..71120105cb 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -88,11 +88,13 @@ type procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; public constructor Create; destructor Destroy; override; class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); class procedure CalcTestInstFile; @@ -1860,6 +1862,698 @@ begin end; end; + +function TAsmTestGenerator.InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, + aOp4: String): TStringList; +var + i: integer; + Item: TOperandListItem; + OItem1: TOperandListItem; + OItem2: TOperandListItem; + OItem3: TOperandListItem; + OItem4: TOperandListItem; + + il_Op: integer; + il_Op1: integer; + il_Op2: integer; + il_Op3: integer; + il_Op4: integer; + + sSuffix: string; + sl_Operand: String; + sl_Inst : String; + sl_RegCombi: String; + sl_Prefix: String; + UsePrefix: boolean; + il_Operands: integer; + UsedParams: cardinal; + UseDefault: boolean; + sl_RegCombi1: string; + sl_RegCombi2: string; + sl_RegCombi3: string; + + function PrepareOperandTyp(const aTyp: String): String; + begin + result := aTyp; + if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); + if result = 'XMMRM128' then result := 'XMMRM'; + if result = 'YMMRM256' then result := 'YMMRM'; + end; + + +begin + result := TStringList.Create; + + OItem1 := TOperandListItem.Create; + try + OItem2 := TOperandListItem.Create; + try + OItem3 := TOperandListItem.Create; + try + OItem4 := TOperandListItem.Create; + try + + UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR + (UpperCase(aInst) = 'VCVTPD2PS') OR + (UpperCase(aInst) = 'VCVTSI2SD') OR + (UpperCase(aInst) = 'VCVTSI2SS') OR + (UpperCase(aInst) = 'VCVTTPD2DQ') or + (UpperCase(aInst) = 'VPMOVZXWQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTTPD2UDQ') or + (UpperCase(aInst) = 'VCVTUQQ2PS') or + (UpperCase(aInst) = 'VCVTQQ2PS') or + (UpperCase(aInst) = 'VCVTUSI2SD') or + (UpperCase(aInst) = 'VCVTUSI2SS') or + (UpperCase(aInst) = 'VFPCLASSPD') or + (UpperCase(aInst) = 'VFPCLASSPS') or + (UpperCase(aInst) = 'VCMPSS') + + ; + + + + for il_Op := 1 to 4 do + begin + sl_Prefix := ''; + + case il_Op of + 1: begin + Item := OItem1; + sl_Operand := aOp1; + end; + 2: begin + Item := OItem2; + sl_Operand := aOp2; + end; + 3: begin + Item := OItem3; + sl_Operand := aOp3; + end; + 4: begin + Item := OItem4; + sl_Operand := aOp4; + end; + end; + + sl_Operand := PrepareOperandTyp(sl_Operand); + + if (AnsiSameText(sl_Operand, 'XMMREG')) or + (AnsiSameText(sl_Operand, 'XMMREG_M')) or + (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'XMMREG_ER')) or + (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + Item.Values.Add('XMM0'); + end + else if (AnsiSameText(sl_Operand, 'XMMRM')) or + (AnsiSameText(sl_Operand, 'XMMRM_M')) or + (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'XMMRM8')) or + (AnsiSameText(sl_Operand, 'XMMRM8_M')) or + (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + + end + else if (AnsiSameText(sl_Operand, 'XMMRM16')) or + (AnsiSameText(sl_Operand, 'XMMRM16_M')) or + (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + + end + else if (AnsiSameText(sl_Operand, 'YMMREG')) or + (AnsiSameText(sl_Operand, 'YMMREG_M')) or + (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'YMMREG_ER')) or + (AnsiSameText(sl_Operand, 'YMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + Item.Values.Add('YMM0'); + end + else if (AnsiSameText(sl_Operand, 'YMMRM')) or + (AnsiSameText(sl_Operand, 'YMMRM_M')) or + (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'YMMRM_ER')) or + (AnsiSameText(sl_Operand, 'YMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'ZMMREG')) or + (AnsiSameText(sl_Operand, 'ZMMREG_M')) or + (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or + (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + Item.Values.Add('ZMM0'); + end + else if (AnsiSameText(sl_Operand, 'ZMMRM')) or + (AnsiSameText(sl_Operand, 'ZMMRM_M')) or + (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'MEM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'MEM16') or + AnsiSameText(sl_Operand, 'MEM16_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'MEM32') or + AnsiSameText(sl_Operand, 'MEM32_M') or + AnsiSameText(sl_Operand, 'MEM32_MZ') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'dword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'MEM64')) or + (AnsiSameText(sl_Operand, 'MEM64_M')) or + (AnsiSameText(sl_Operand, 'MEM64_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'qword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'MEM128')) or + (AnsiSameText(sl_Operand, 'MEM128_M')) or + (AnsiSameText(sl_Operand, 'MEM128_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM128; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'MEM256')) or + (AnsiSameText(sl_Operand, 'MEM256_M')) or + (AnsiSameText(sl_Operand, 'MEM256_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM256; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if (AnsiSameText(sl_Operand, 'MEM512')) or + (AnsiSameText(sl_Operand, 'MEM512_M')) or + (AnsiSameText(sl_Operand, 'MEM512_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM512; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'REG8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG8; + Item.OpActive := true; + + Item.Values.Add('al'); + end + else if AnsiSameText(sl_Operand, 'REG16') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG16; + Item.OpActive := true; + + Item.Values.Add('ax'); + end + else if AnsiSameText(sl_Operand, 'REG32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG32; + Item.OpActive := true; + + Item.Values.Add('eax'); + end + else if AnsiSameText(sl_Operand, 'REG64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG64; + Item.OpActive := true; + + Item.Values.Add('rax'); + end + else if AnsiSameText(sl_Operand, 'RM32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + Item.Values.AddStrings(FReg32Base); + + if UsePrefix then sl_Prefix := 'dword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'RM64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'qword '; + + Item.Values.Add('v1'); + Item.Values.Add(sl_Prefix + ' v1'); + Item.Values.Add(sl_Prefix + ' [v1]'); + end + else if AnsiSameText(sl_Operand, 'IMM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otIMM8; + Item.OpActive := true; + + Item.Values.Add('0'); + end + else if AnsiSameText(sl_Operand, 'XMEM32') or + AnsiSameText(sl_Operand, 'XMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + end + else if AnsiSameText(sl_Operand, 'XMEM64') or + AnsiSameText(sl_Operand, 'XMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + end + else if AnsiSameText(sl_Operand, 'YMEM32') or + AnsiSameText(sl_Operand, 'YMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + end + else if AnsiSameText(sl_Operand, 'YMEM64') or + AnsiSameText(sl_Operand, 'YMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + end + else if AnsiSameText(sl_Operand, 'ZMEM32') or + AnsiSameText(sl_Operand, 'ZMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + end + else if AnsiSameText(sl_Operand, 'ZMEM64') or + AnsiSameText(sl_Operand, 'ZMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + end + else if AnsiSameText(sl_Operand, '2B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('v1 {1to2}'); + Item.Values.Add('dword v1 {1to2}'); + end + else if AnsiSameText(sl_Operand, '4B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('v1 {1to4}'); + Item.Values.Add('dword v1 {1to4}'); + end + else if AnsiSameText(sl_Operand, '8B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('v1 {1to8}'); + Item.Values.Add('dword v1 {1to8}'); + end + else if AnsiSameText(sl_Operand, '16B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('v1 {1to16}'); + Item.Values.Add('dword v1 {1to16}'); + end + else if AnsiSameText(sl_Operand, '2B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('v1 {1to2}'); + Item.Values.Add('qword v1 {1to2}'); + end + else if AnsiSameText(sl_Operand, '4B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('v1 {1to4}'); + Item.Values.Add('qword v1 {1to4}'); + end + else if AnsiSameText(sl_Operand, '8B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('v1 {1to8}'); + Item.Values.Add('qword v1 {1to8}'); + end + else if AnsiSameText(sl_Operand, '16B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('v1 {1to16}'); + Item.Values.Add('qword v1 {1to16}'); + end + else if AnsiSameText(sl_Operand, 'KREG') or + AnsiSameText(sl_Operand, 'KREG_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otKREG; + Item.OpActive := true; + + Item.Values.Add('k1'); + end + else if trim(sl_Operand) = '' then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add(''); + end + else + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add('?' + sl_Operand); + end + + end; + + sl_RegCombi := ''; + + + il_Operands := 0; + UsedParams := 0; + + if OItem1.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 1; + end; + + if OItem2.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 2; + end; + + if OItem3.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 4; + end; + + if OItem4.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 8; + end; + + case il_Operands of + 1: UseDefault := UsedParams <> 1; + 2: UseDefault := UsedParams <> 3; + 3: UseDefault := UsedParams <> 7; + 4: UseDefault := UsedParams <> 15; + else UseDefault := true; + end; + + //UseDefault := true; + + if UseDefault then + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sl_RegCombi := ''; + + if OItem1.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + end; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end + else + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + if OItem1.OpActive then + begin + sl_RegCombi1 := OItem1.Values[il_Op1]; + end + else sl_RegCombi1 := ''; + + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + if OItem2.OpActive then + begin + sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + end + else sl_RegCombi2 := sl_RegCombi1; + + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + if OItem3.OpActive then + begin + sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + end + else sl_RegCombi3 := sl_RegCombi2; + + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + if OItem4.OpActive then + begin + sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + end + else sl_RegCombi := sl_RegCombi3; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end; + finally + FreeAndNil(OItem4); + end; + finally + FreeAndNil(OItem3); + end; + finally + FreeAndNil(OItem2); + end; + finally + FreeAndNil(OItem1); + end; +end; + + constructor TAsmTestGenerator.Create; begin inherited; @@ -2210,6 +2904,30 @@ begin end; end; +class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, + aOp4: String; aSL: TStringList); +var + sl: TStringList; +begin + with TAsmTestGenerator.Create do + try + Fx64 := aX64; + FAVX512 := aAVX512; + FSAE := aSAE; + + sl := InternalCalcTestData(aInst, aOp1, aOp2, aOp3, aOp4); + try + aSL.AddStrings(sl); + finally + FreeAndNil(sl); + end; + finally + Free; + end; +end; + + + class procedure TAsmTestGenerator.CalcTestInstFile; var i,j: integer; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 559ebb8260..5058f7a450 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -8,7 +8,7 @@ uses Classes; type - TTestFileTyp = (tfNasm, tfFPC, tfFasm, tfFPCInc); + TTestFileTyp = (tfNasm, tfFPC, tfFasm, tfFPCInc, tfFPCMRef); TAVXTestGenerator = class(TObject) private @@ -16,13 +16,14 @@ type protected procedure Init; - function InternalMakeTestFiles(aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; + function InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; public constructor Create; destructor Destroy; override; function MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; +// function MakeTestFilesMREF(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; property OpCodeList: TStringList read FOpCodeList write FOpCodeList; end; @@ -3256,7 +3257,7 @@ begin end; -function TAVXTestGenerator.InternalMakeTestFiles(aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; +function TAVXTestGenerator.InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; var i: integer; @@ -3369,6 +3370,30 @@ begin slFooter.Add(' end;'); slFooter.Add('end.'); end; + tfFPCMRef: + begin + writeln(format('outputformat: fpc platform: %s path: %s', + [cPlatform[aX64], aDestPath])); + + FileExt := '.pp'; + + slHeader.Add('Program $$$OPCODE$$$;'); + slHeader.Add('{$asmmode intel}'); + slHeader.Add(' procedure 1;'); + slHeader.Add(' begin'); + slHeader.Add(' asm'); + for i := 1 to 10 do + slHeader.Add(' NOP'); + + + for i := 1 to 10 do + slFooter.Add(' NOP'); + + slFooter.Add(' end;'); + slFooter.Add(' end;'); + slFooter.Add('begin'); + slFooter.Add('end.'); + end; tfFPCInc: begin writeln(format('outputformat: fpc platform: %s path: %s', [cPlatform[aX64], aDestPath])); @@ -3444,7 +3469,7 @@ begin end; end; - InternalMakeTestFiles(aX64, aAVX512, aSAE, aDestPath, Fileext, FOpCodeList, slHeader, slFooter); + InternalMakeTestFiles(aTyp = tfFPCMRef, aX64, aAVX512, aSAE, aDestPath, Fileext, FOpCodeList, slHeader, slFooter); finally FreeAndNil(slFooter); diff --git a/tests/utils/avx/avxtestgenerator.pp b/tests/utils/avx/avxtestgenerator.pp index bfe4c8d99e..4c1b43f435 100644 --- a/tests/utils/avx/avxtestgenerator.pp +++ b/tests/utils/avx/avxtestgenerator.pp @@ -58,6 +58,7 @@ begin 'F': MakeTestFiles(tfFasm, x64, AVX512, false, Path); 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path); 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path); + 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path); end; end; finally diff --git a/tests/utils/avx/options.pas b/tests/utils/avx/options.pas index c7f59f61fb..89c8771cbd 100644 --- a/tests/utils/avx/options.pas +++ b/tests/utils/avx/options.pas @@ -35,6 +35,7 @@ type FX64: boolean; FOutputFormat: Char; FPath: string; + FMemRef: boolean; public constructor Create; @@ -45,6 +46,7 @@ type property X64: boolean read FX64 write FX64; property AVX512: boolean read FAVX512 write FAVX512; property Path: string read FPath write FPath; + property MemRef: boolean read FMemref write FMemRef; end; implementation @@ -60,6 +62,7 @@ begin FAVX512 := false; FOutputFormat := '?'; FPath := ''; + FMemRef := false; end; procedure TOptions.LoadParams; @@ -90,6 +93,8 @@ begin else if sValue = 'nasm' then FOutputFormat := 'n' else if sValue = 'fasm' then FOutputFormat := 'F' else if sValue = 'fpcinc' then FOutputFormat := 'I' + else if sValue = 'fpcmref' then FOutputFormat := 'm' + else IsInvalidParam := true; 'p': if sValue = 'x8664' then begin From c69f1a20f498f1e8b5db8a59e83c3e5c53ec95fa Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 25 Nov 2020 11:50:10 +0000 Subject: [PATCH 004/116] working on new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47580 - --- tests/utils/avx/asmtestgenerator.pas | 51 ++++++++++++++++++++++++---- tests/utils/avx/avxopcodes.pas | 17 +++++++--- 2 files changed, 57 insertions(+), 11 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 71120105cb..6ace6596db 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -88,7 +88,7 @@ type procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; - function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String; var aDatatyp: string): TStringList; public constructor Create; destructor Destroy; override; @@ -1864,7 +1864,7 @@ end; function TAsmTestGenerator.InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, - aOp4: String): TStringList; + aOp4: String; var aDatatyp: string): TStringList; var i: integer; Item: TOperandListItem; @@ -1904,6 +1904,8 @@ var begin result := TStringList.Create; + aDatatyp := ''; + OItem1 := TOperandListItem.Create; try OItem2 := TOperandListItem.Create; @@ -1983,6 +1985,8 @@ begin if UsePrefix then sl_Prefix := 'oword '; + aDatatyp := 'array[0..15] of byte'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -1999,6 +2003,8 @@ begin if UsePrefix then sl_Prefix := 'byte '; + aDatatyp := 'byte'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2017,6 +2023,8 @@ begin if UsePrefix then sl_Prefix := 'word '; + aDataTyp := 'word'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2047,6 +2055,7 @@ begin Item.OpActive := true; if UsePrefix then sl_Prefix := 'yword '; + aDatatyp := 'array [0..31] of byte'; Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); @@ -2078,6 +2087,8 @@ begin if UsePrefix then sl_Prefix := 'zword '; + aDatatyp := 'array[0..63] of byte'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2088,8 +2099,13 @@ begin Item.OpTyp := otMEM8; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'byte '; + if UsePrefix then + begin + sl_Prefix := 'byte '; + end; + aDatatyp := 'byte'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2101,7 +2117,12 @@ begin Item.OpTyp := otMEM16; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'word '; + if UsePrefix then + begin + sl_Prefix := 'word '; + end; + + aDataTyp := 'word'; Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); @@ -2116,6 +2137,8 @@ begin Item.OpActive := true; if UsePrefix then sl_Prefix := 'dword '; + aDataTyp := 'dword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); @@ -2131,6 +2154,8 @@ begin if UsePrefix then sl_Prefix := 'qword '; + aDataTyp := 'qword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2145,6 +2170,8 @@ begin if UsePrefix then sl_Prefix := 'oword '; + aDatatyp := 'oword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2159,6 +2186,8 @@ begin if UsePrefix then sl_Prefix := 'yword '; + aDatatyp := 'yword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2173,6 +2202,8 @@ begin if UsePrefix then sl_Prefix := 'zword '; + aDatatyp := 'zword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2219,6 +2250,8 @@ begin if UsePrefix then sl_Prefix := 'dword '; + aDatatyp := 'dword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2231,6 +2264,8 @@ begin if UsePrefix then sl_Prefix := 'qword '; + aDatatyp := 'qword'; + Item.Values.Add('v1'); Item.Values.Add(sl_Prefix + ' v1'); Item.Values.Add(sl_Prefix + ' [v1]'); @@ -2252,6 +2287,7 @@ begin if UsePrefix then sl_Prefix := 'oword '; + aDatatyp := 'array[0.15] of byte'; end else if AnsiSameText(sl_Operand, 'XMEM64') or AnsiSameText(sl_Operand, 'XMEM64_M') then @@ -2262,6 +2298,8 @@ begin if UsePrefix then sl_Prefix := 'oword '; + + end else if AnsiSameText(sl_Operand, 'YMEM32') or AnsiSameText(sl_Operand, 'YMEM32_M') then @@ -2905,8 +2943,9 @@ begin end; class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, - aOp4: String; aSL: TStringList); + aOp4: String; aSL: TStringList); var + sDataTyp: string; sl: TStringList; begin with TAsmTestGenerator.Create do @@ -2915,7 +2954,7 @@ begin FAVX512 := aAVX512; FSAE := aSAE; - sl := InternalCalcTestData(aInst, aOp1, aOp2, aOp3, aOp4); + sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4, sDataTyp); try aSL.AddStrings(sl); finally diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 5058f7a450..d9dff4be5c 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3306,17 +3306,24 @@ begin if (not(aX64) and (sl[1] = '1')) or // i386 (aX64 and (sl[2] = '1')) then // x86_64 begin - if (sl[4] = '') and + sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); + + if (sl[4] = '') and (sl[5] = '') and (sl[6] = '') and (sl[7] = '') then begin // Opcode with no Params, e.g. VZEROALL slAsm.Add(' ' + sl[0]); end - else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); - - sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); - + else + begin + if aMREF then + begin + TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + sDestFile := 'MREF_' + sDestFile; + end + else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + end; SaveFile(slAsm, sDestFile, aDestPath, aFileExt, aHeaderList, aFooterList); writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); From 5207d0ee25a8bb2f37088e654b25dae2a5ade454 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 26 Nov 2020 16:27:48 +0000 Subject: [PATCH 005/116] working on new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47600 - --- tests/utils/avx/asmtestgenerator.pas | 7 +++---- tests/utils/avx/avxopcodes.pas | 12 ++++++++++-- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 6ace6596db..c3bf728b03 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -94,7 +94,7 @@ type destructor Destroy; override; class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); - class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList; var aLocalVarDataTyp: string); class procedure CalcTestInstFile; @@ -2943,9 +2943,8 @@ begin end; class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, - aOp4: String; aSL: TStringList); + aOp4: String; aSL: TStringList; var aLocalVarDataTyp: string); var - sDataTyp: string; sl: TStringList; begin with TAsmTestGenerator.Create do @@ -2954,7 +2953,7 @@ begin FAVX512 := aAVX512; FSAE := aSAE; - sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4, sDataTyp); + sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4, aLocalVarDataTyp); try aSL.AddStrings(sl); finally diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index d9dff4be5c..2259841271 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3263,6 +3263,7 @@ var i: integer; sData: string; sDestFile: string; + sLocalVarDataTyp: string; sl: TStringList; slAsm: TStringList; LastOpCode: String; @@ -3319,8 +3320,13 @@ begin begin if aMREF then begin - TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm, sLocalVarDataTyp); sDestFile := 'MREF_' + sDestFile; + + if trim(sLocalVarDataTyp) = '' then + sLocalVarDataTyp := 'byte'; + + aHeaderList.Text := StringReplace(aHeaderList.Text, '$$$LOCALVARDATATYP$$$', sLocalVarDataTyp, [rfReplaceAll]); end else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); end; @@ -3386,7 +3392,9 @@ begin slHeader.Add('Program $$$OPCODE$$$;'); slHeader.Add('{$asmmode intel}'); - slHeader.Add(' procedure 1;'); + slHeader.Add(' procedure dummyproc;'); + slHeader.Add(' var'); + slHeader.Add(' v1: $$$LOCALVARDATATYP$$$;'); slHeader.Add(' begin'); slHeader.Add(' asm'); for i := 1 to 10 do From 3af6a9826347573ff8a33b50748e48541e41a1e9 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 27 Nov 2020 05:45:44 +0000 Subject: [PATCH 006/116] bugfix internal assembler-reader x86 opsize local var git-svn-id: branches/tg74/avx512-0037785@47606 - --- compiler/x86/rax86.pas | 27 +++++++++++++++++++++++++++ tests/utils/avx/avxopcodes.pas | 12 ++++++------ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 9547db0c21..c6e7ea3fc2 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1954,6 +1954,33 @@ begin ai.loadlocal(i-1,localsym,localsymofs,localindexreg, localscale,localgetoffset,localforceref); ai.oper[i-1]^.localoper^.localsegment:=localsegment; + + if MemRefInfo(opcode).ExistsSSEAVX then + begin + asize := 0; + + case operands[i].size of + OS_32,OS_M32: if (operands[i].HasType) or + (MemRefInfo(opcode).MemRefSize = msiMem32) or + (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) + //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and + // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) + //) + then + asize:=OT_BITS32; + OS_64,OS_M64: if (operands[i].HasType) or + (MemRefInfo(opcode).MemRefSize = msiMem64) or + //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and + // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) + //) then + (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then + asize:=OT_BITS64; + else; + end; + + if asize<>0 then + ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; + end; end; OPR_REFERENCE: begin diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 2259841271..5b1b08d73d 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -200,10 +200,10 @@ begin FOpCodeList.Add('vaddpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vaddpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vaddpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vaddpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vaddpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vaddpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_ER,'); FOpCodeList.Add('vaddpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vaddpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vaddpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vaddps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vaddps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vaddps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -228,9 +228,9 @@ begin FOpCodeList.Add('vandnpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vandnpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vandnpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vandnpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vandnpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vandnpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vandnpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vandnpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vandnps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vandnps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vandnps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -240,9 +240,9 @@ begin FOpCodeList.Add('vandpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vandpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vandpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vandpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vandpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vandpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vandpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vandpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vandps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vandps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vandps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); From f4251bc11a21d64cf80df90db853c8df12558b73 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 27 Nov 2020 15:54:47 +0000 Subject: [PATCH 007/116] working on new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47608 - --- tests/utils/avx/avxopcodes.pas | 58 ++++++++++++++++------------ tests/utils/avx/avxtestgenerator.lpi | 10 ++--- 2 files changed, 39 insertions(+), 29 deletions(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 5b1b08d73d..481a2e156f 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3266,6 +3266,7 @@ var sLocalVarDataTyp: string; sl: TStringList; slAsm: TStringList; + slLocalHeader: TStringList; LastOpCode: String; NewOpCode: String; @@ -3308,31 +3309,40 @@ begin (aX64 and (sl[2] = '1')) then // x86_64 begin sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); - - if (sl[4] = '') and - (sl[5] = '') and - (sl[6] = '') and - (sl[7] = '') then - begin // Opcode with no Params, e.g. VZEROALL - slAsm.Add(' ' + sl[0]); - end - else - begin - if aMREF then - begin - TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm, sLocalVarDataTyp); - sDestFile := 'MREF_' + sDestFile; - - if trim(sLocalVarDataTyp) = '' then - sLocalVarDataTyp := 'byte'; - - aHeaderList.Text := StringReplace(aHeaderList.Text, '$$$LOCALVARDATATYP$$$', sLocalVarDataTyp, [rfReplaceAll]); - end - else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); - end; - SaveFile(slAsm, sDestFile, aDestPath, aFileExt, aHeaderList, aFooterList); - writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); + slLocalHeader := TStringList.Create; + try + slLocalHeader.Text := aHeaderList.text; + + if (sl[4] = '') and + (sl[5] = '') and + (sl[6] = '') and + (sl[7] = '') then + begin // Opcode with no Params, e.g. VZEROALL + slAsm.Add(' ' + sl[0]); + end + else + begin + if aMREF then + begin + sLocalVarDataTyp := ''; + TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm, sLocalVarDataTyp); + sDestFile := 'MREF_' + sDestFile; + + if trim(sLocalVarDataTyp) = '' then + sLocalVarDataTyp := 'byte'; + + slLocalHeader.Text := StringReplace(aHeaderList.Text, '$$$LOCALVARDATATYP$$$', sLocalVarDataTyp, [rfReplaceAll]); + end + else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + end; + + SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); + writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); + + finally + FreeAndNil(slLocalHeader); + end; slAsm.Clear; end; diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index c14694660c..6bf45626ec 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -1,13 +1,12 @@ - + - @@ -20,11 +19,12 @@ - - - + + + + From 0a3d980f7e883862dec13db1745e75646c5f6f09 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 30 Nov 2020 13:53:25 +0000 Subject: [PATCH 008/116] working on new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47640 - --- compiler/ppcx64.lpi | 23 ++-- tests/utils/avx/asmtestgenerator.pas | 191 ++++++++------------------- tests/utils/avx/avxopcodes.pas | 29 +++- 3 files changed, 91 insertions(+), 152 deletions(-) diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index a28f04cf21..d10e934a3e 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -1,7 +1,7 @@ - + - + @@ -19,26 +19,30 @@ - - - - - + + + + + + + + + + + - - @@ -71,7 +75,6 @@ - diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index c3bf728b03..f9072a868e 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -88,13 +88,13 @@ type procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; - function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String; var aDatatyp: string): TStringList; + function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; public constructor Create; destructor Destroy; override; class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); - class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList; var aLocalVarDataTyp: string); + class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); class procedure CalcTestInstFile; @@ -1864,7 +1864,7 @@ end; function TAsmTestGenerator.InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, - aOp4: String; var aDatatyp: string): TStringList; + aOp4: String): TStringList; var i: integer; Item: TOperandListItem; @@ -1904,8 +1904,6 @@ var begin result := TStringList.Create; - aDatatyp := ''; - OItem1 := TOperandListItem.Create; try OItem2 := TOperandListItem.Create; @@ -1985,11 +1983,12 @@ begin if UsePrefix then sl_Prefix := 'oword '; - aDatatyp := 'array[0..15] of byte'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add(' lOWord'); + Item.Values.Add(' gOWord'); + + Item.Values.Add(' oword lOWord'); + Item.Values.Add(' oword gOWord'); + end else if (AnsiSameText(sl_Operand, 'XMMRM8')) or (AnsiSameText(sl_Operand, 'XMMRM8_M')) or @@ -2003,12 +2002,8 @@ begin if UsePrefix then sl_Prefix := 'byte '; - aDatatyp := 'byte'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); - + Item.Values.Add('lbyte'); + Item.Values.Add('gbyte'); end else if (AnsiSameText(sl_Operand, 'XMMRM16')) or (AnsiSameText(sl_Operand, 'XMMRM16_M')) or @@ -2021,14 +2016,8 @@ begin Item.OpTyp := otXMMRM16; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'word '; - - aDataTyp := 'word'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); - + Item.Values.Add('lword'); + Item.Values.Add('gword'); end else if (AnsiSameText(sl_Operand, 'YMMREG')) or (AnsiSameText(sl_Operand, 'YMMREG_M')) or @@ -2054,12 +2043,8 @@ begin Item.OpTyp := otYMMRM; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'yword '; - aDatatyp := 'array [0..31] of byte'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lYWord'); + Item.Values.Add('gYWord'); end else if (AnsiSameText(sl_Operand, 'ZMMREG')) or (AnsiSameText(sl_Operand, 'ZMMREG_M')) or @@ -2085,13 +2070,8 @@ begin Item.OpTyp := otZMMRM; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'zword '; - - aDatatyp := 'array[0..63] of byte'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lZWord'); + Item.Values.Add('gZWord'); end else if AnsiSameText(sl_Operand, 'MEM8') then begin @@ -2099,16 +2079,8 @@ begin Item.OpTyp := otMEM8; Item.OpActive := true; - if UsePrefix then - begin - sl_Prefix := 'byte '; - end; - - aDatatyp := 'byte'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lByte'); + Item.Values.Add('gByte'); end else if AnsiSameText(sl_Operand, 'MEM16') or AnsiSameText(sl_Operand, 'MEM16_M') then @@ -2117,16 +2089,8 @@ begin Item.OpTyp := otMEM16; Item.OpActive := true; - if UsePrefix then - begin - sl_Prefix := 'word '; - end; - - aDataTyp := 'word'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lWord'); + Item.Values.Add('gWord'); end else if AnsiSameText(sl_Operand, 'MEM32') or AnsiSameText(sl_Operand, 'MEM32_M') or @@ -2136,13 +2100,8 @@ begin Item.OpTyp := otMEM32; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'dword '; - aDataTyp := 'dword'; - - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lDWord'); + Item.Values.Add('gDWord'); end else if (AnsiSameText(sl_Operand, 'MEM64')) or (AnsiSameText(sl_Operand, 'MEM64_M')) or @@ -2152,13 +2111,8 @@ begin Item.OpTyp := otMEM64; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'qword '; - - aDataTyp := 'qword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lQWord'); + Item.Values.Add('gQWord'); end else if (AnsiSameText(sl_Operand, 'MEM128')) or (AnsiSameText(sl_Operand, 'MEM128_M')) or @@ -2168,13 +2122,8 @@ begin Item.OpTyp := otMEM128; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'oword '; - - aDatatyp := 'oword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lOWord'); + Item.Values.Add('gOWord'); end else if (AnsiSameText(sl_Operand, 'MEM256')) or (AnsiSameText(sl_Operand, 'MEM256_M')) or @@ -2184,13 +2133,8 @@ begin Item.OpTyp := otMEM256; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'yword '; - - aDatatyp := 'yword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lYWord'); + Item.Values.Add('gYWord'); end else if (AnsiSameText(sl_Operand, 'MEM512')) or (AnsiSameText(sl_Operand, 'MEM512_M')) or @@ -2200,13 +2144,8 @@ begin Item.OpTyp := otMEM512; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'zword '; - - aDatatyp := 'zword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lZWord'); + Item.Values.Add('gZWord'); end else if AnsiSameText(sl_Operand, 'REG8') then begin @@ -2246,15 +2185,8 @@ begin Item.OpTyp := otRM32; Item.OpActive := true; - Item.Values.AddStrings(FReg32Base); - - if UsePrefix then sl_Prefix := 'dword '; - - aDatatyp := 'dword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lDWord'); + Item.Values.Add('gDWord'); end else if AnsiSameText(sl_Operand, 'RM64') then begin @@ -2262,13 +2194,8 @@ begin Item.OpTyp := otRM64; Item.OpActive := true; - if UsePrefix then sl_Prefix := 'qword '; - - aDatatyp := 'qword'; - - Item.Values.Add('v1'); - Item.Values.Add(sl_Prefix + ' v1'); - Item.Values.Add(sl_Prefix + ' [v1]'); + Item.Values.Add('lQWord'); + Item.Values.Add('gQWord'); end else if AnsiSameText(sl_Operand, 'IMM8') then begin @@ -2284,10 +2211,6 @@ begin Item.OpNumber := il_Op; Item.OpTyp := otXMEM32; Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - aDatatyp := 'array[0.15] of byte'; end else if AnsiSameText(sl_Operand, 'XMEM64') or AnsiSameText(sl_Operand, 'XMEM64_M') then @@ -2295,11 +2218,6 @@ begin Item.OpNumber := il_Op; Item.OpTyp := otXMEM64; Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - - end else if AnsiSameText(sl_Operand, 'YMEM32') or AnsiSameText(sl_Operand, 'YMEM32_M') then @@ -2307,9 +2225,6 @@ begin Item.OpNumber := il_Op; Item.OpTyp := otYMEM32; Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - end else if AnsiSameText(sl_Operand, 'YMEM64') or AnsiSameText(sl_Operand, 'YMEM64_M') then @@ -2347,8 +2262,8 @@ begin Item.OpTyp := otB32; Item.OpActive := true; - Item.Values.Add('v1 {1to2}'); - Item.Values.Add('dword v1 {1to2}'); + Item.Values.Add('lDWord {1to2}'); + Item.Values.Add('gDWord {1to2}'); end else if AnsiSameText(sl_Operand, '4B32') then begin @@ -2356,8 +2271,8 @@ begin Item.OpTyp := otB32; Item.OpActive := true; - Item.Values.Add('v1 {1to4}'); - Item.Values.Add('dword v1 {1to4}'); + Item.Values.Add('lDWord {1to4}'); + Item.Values.Add('gDWord {1to4}'); end else if AnsiSameText(sl_Operand, '8B32') then begin @@ -2365,8 +2280,8 @@ begin Item.OpTyp := otB32; Item.OpActive := true; - Item.Values.Add('v1 {1to8}'); - Item.Values.Add('dword v1 {1to8}'); + Item.Values.Add('lDWord {1to8}'); + Item.Values.Add('gDWord {1to8}'); end else if AnsiSameText(sl_Operand, '16B32') then begin @@ -2374,8 +2289,8 @@ begin Item.OpTyp := otB32; Item.OpActive := true; - Item.Values.Add('v1 {1to16}'); - Item.Values.Add('dword v1 {1to16}'); + Item.Values.Add('lDWord {1to16}'); + Item.Values.Add('gDWord {1to16}'); end else if AnsiSameText(sl_Operand, '2B64') then begin @@ -2383,8 +2298,8 @@ begin Item.OpTyp := otB64; Item.OpActive := true; - Item.Values.Add('v1 {1to2}'); - Item.Values.Add('qword v1 {1to2}'); + Item.Values.Add('lQWord {1to2}'); + Item.Values.Add('gQWord {1to2}'); end else if AnsiSameText(sl_Operand, '4B64') then begin @@ -2392,8 +2307,8 @@ begin Item.OpTyp := otB64; Item.OpActive := true; - Item.Values.Add('v1 {1to4}'); - Item.Values.Add('qword v1 {1to4}'); + Item.Values.Add('lQWord {1to4}'); + Item.Values.Add('gQWord {1to4}'); end else if AnsiSameText(sl_Operand, '8B64') then begin @@ -2401,8 +2316,8 @@ begin Item.OpTyp := otB64; Item.OpActive := true; - Item.Values.Add('v1 {1to8}'); - Item.Values.Add('qword v1 {1to8}'); + Item.Values.Add('lQWord {1to8}'); + Item.Values.Add('gQWord {1to8}'); end else if AnsiSameText(sl_Operand, '16B64') then begin @@ -2410,8 +2325,8 @@ begin Item.OpTyp := otB64; Item.OpActive := true; - Item.Values.Add('v1 {1to16}'); - Item.Values.Add('qword v1 {1to16}'); + Item.Values.Add('lQWord {1to16}'); + Item.Values.Add('gQWord {1to16}'); end else if AnsiSameText(sl_Operand, 'KREG') or AnsiSameText(sl_Operand, 'KREG_M') then @@ -2943,7 +2858,7 @@ begin end; class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, - aOp4: String; aSL: TStringList; var aLocalVarDataTyp: string); + aOp4: String; aSL: TStringList); var sl: TStringList; begin @@ -2953,7 +2868,7 @@ begin FAVX512 := aAVX512; FSAE := aSAE; - sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4, aLocalVarDataTyp); + sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4); try aSL.AddStrings(sl); finally diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 481a2e156f..4ef598c02d 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -602,9 +602,9 @@ begin FOpCodeList.Add('vminpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vminpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vminpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vminpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vminpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vminpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vminpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vminpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vminpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_SAE,'); FOpCodeList.Add('vminps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vminps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); @@ -3326,7 +3326,7 @@ begin if aMREF then begin sLocalVarDataTyp := ''; - TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm, sLocalVarDataTyp); + TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); sDestFile := 'MREF_' + sDestFile; if trim(sLocalVarDataTyp) = '' then @@ -3402,9 +3402,30 @@ begin slHeader.Add('Program $$$OPCODE$$$;'); slHeader.Add('{$asmmode intel}'); + + + slHeader.Add('var'); + slHeader.Add(' gByte: byte;'); + slHeader.Add(' gWord: word;'); + slHeader.Add(' gDWord: dword;'); + slHeader.Add(' gQWord: qword;'); + slHeader.Add(' gOWord: array[0..15] of byte;'); + slHeader.Add(' gYWord: array[0..31] of byte;'); + slHeader.Add(' gZWord: array[0..63] of byte;'); + slHeader.Add(' procedure dummyproc;'); slHeader.Add(' var'); - slHeader.Add(' v1: $$$LOCALVARDATATYP$$$;'); + slHeader.Add(' lByte: byte;'); + slHeader.Add(' lWord: word;'); + slHeader.Add(' lDWord: dword;'); + slHeader.Add(' lQWord: qword;'); + slHeader.Add(' lOWord: array[0..15] of byte;'); + slHeader.Add(' lYWord: array[0..31] of byte;'); + slHeader.Add(' lZWord: array[0..63] of byte;'); + + slHeader.Add(' lSingle: single;'); + slHeader.Add(' lDouble: double;'); + slHeader.Add(' begin'); slHeader.Add(' asm'); for i := 1 to 10 do From ae71ab728462e24367107623c19c4ba6aaaf8716 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 30 Nov 2020 16:31:51 +0000 Subject: [PATCH 009/116] working on new testmethods memref operands git-svn-id: branches/tg74/avx512-0037785@47642 - --- compiler/x86/rax86.pas | 9 +++ tests/utils/avx/avxopcodes.pas | 112 ++++++++++++++++----------------- 2 files changed, 65 insertions(+), 56 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index c6e7ea3fc2..f765c88537 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1975,6 +1975,15 @@ begin //) then (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then asize:=OT_BITS64; + OS_M128: if (operands[i].HasType) or + (MemRefInfo(opcode).MemRefSize = msiMem128) then + asize:=OT_BITS128; + OS_M256: if (operands[i].HasType) or + (MemRefInfo(opcode).MemRefSize = msiMem256) then + asize:=OT_BITS256; + OS_M512: if (operands[i].HasType) or + (MemRefInfo(opcode).MemRefSize = msiMem512) then + asize:=OT_BITS512; else; end; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 4ef598c02d..dbfae9c23a 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -536,9 +536,9 @@ begin FOpCodeList.Add('vdivpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vdivpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vdivpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vdivpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vdivpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vdivpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vdivpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vdivpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vdivpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_ER,'); FOpCodeList.Add('vdivps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vdivps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); @@ -584,10 +584,10 @@ begin FOpCodeList.Add('vmaxpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vmaxpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vmaxpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vmaxpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vmaxpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vmaxpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_SAE,'); FOpCodeList.Add('vmaxpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vmaxpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vmaxpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vmaxps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vmaxps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vmaxps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -725,9 +725,9 @@ begin FOpCodeList.Add('vmulpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vmulpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vmulpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vmulpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vmulpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vmulpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vmulpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vmulpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vmulpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_ER,'); FOpCodeList.Add('vmulps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vmulps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); @@ -743,9 +743,9 @@ begin FOpCodeList.Add('vorpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vorpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vorpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vorpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vorpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vorpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vorpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vorpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vorps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vorps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vorps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -794,9 +794,9 @@ begin FOpCodeList.Add('vpaddq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpaddq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpaddq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpaddq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpaddq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpaddq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpaddq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpaddq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpaddsb,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpaddsb,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpaddsb,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); @@ -848,9 +848,9 @@ begin FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,XMMREG,XMMRM,'); FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,XMMREG,2B64,'); FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,YMMREG,YMMRM,'); - FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,YMMREG,4B32,'); + FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,YMMREG,4B64,'); FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,ZMMREG,8B32,'); + FOpCodeList.Add('vpcmpeqq,1,1,1,KREG_M,ZMMREG,8B64,'); FOpCodeList.Add('vpcmpeqq,1,1,0,XMMREG,XMMREG,XMMRM,'); FOpCodeList.Add('vpcmpeqq,1,1,0,YMMREG,YMMREG,YMMRM,'); FOpCodeList.Add('vpcmpeqw,1,1,1,KREG_M,XMMREG,XMMRM,'); @@ -876,9 +876,9 @@ begin FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,XMMREG,XMMRM,'); FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,XMMREG,2B64,'); FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,YMMREG,YMMRM,'); - FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,YMMREG,4B32,'); + FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,YMMREG,4B64,'); FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,ZMMREG,8B32,'); + FOpCodeList.Add('vpcmpgtq,1,1,1,KREG_M,ZMMREG,8B64,'); FOpCodeList.Add('vpcmpgtq,1,1,0,XMMREG,XMMREG,XMMRM,'); FOpCodeList.Add('vpcmpgtq,1,1,0,YMMREG,YMMREG,YMMRM,'); FOpCodeList.Add('vpcmpgtw,1,1,1,KREG_M,XMMREG,XMMRM,'); @@ -894,13 +894,13 @@ begin FOpCodeList.Add('vpermilpd,1,1,1,XMMREG_MZ,XMMRM,IMM8,'); FOpCodeList.Add('vpermilpd,1,1,1,XMMREG_MZ,2B64,IMM8,'); FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,YMMRM,IMM8,'); - FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,4B32,IMM8,'); + FOpCodeList.Add('vpermilpd,1,1,1,YMMREG_MZ,4B64,IMM8,'); FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,ZMMRM,IMM8,'); - FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,8B32,IMM8,'); + FOpCodeList.Add('vpermilpd,1,1,1,ZMMREG_MZ,8B64,IMM8,'); FOpCodeList.Add('vpermilps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpermilps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vpermilps,1,1,1,XMMREG_MZ,XMMRM,IMM8,'); @@ -1076,9 +1076,9 @@ begin FOpCodeList.Add('vpmuldq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpmuldq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpmuldq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpmuldq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpmuldq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpmuldq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpmuldq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpmuldq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpmulhrsw,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpmulhrsw,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpmulhrsw,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); @@ -1100,9 +1100,9 @@ begin FOpCodeList.Add('vpmuludq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpmuludq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpmuludq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpmuludq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpmuludq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpmuludq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpmuludq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpmuludq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpor,1,1,0,XMMREG,XMMREG,XMMRM,'); FOpCodeList.Add('vpor,1,1,0,YMMREG,YMMREG,YMMRM,'); FOpCodeList.Add('vpsadbw,1,1,1,XMMREG,XMMREG,XMMRM,'); @@ -1146,10 +1146,10 @@ begin FOpCodeList.Add('vpsllq,1,1,1,XMMREG_MZ,2B64,IMM8,'); FOpCodeList.Add('vpsllq,1,1,1,YMMREG_MZ,YMMREG,XMMRM,'); FOpCodeList.Add('vpsllq,1,1,1,YMMREG_MZ,YMMRM,IMM8,'); - FOpCodeList.Add('vpsllq,1,1,1,YMMREG_MZ,4B32,IMM8,'); + FOpCodeList.Add('vpsllq,1,1,1,YMMREG_MZ,4B64,IMM8,'); FOpCodeList.Add('vpsllq,1,1,1,ZMMREG_MZ,ZMMREG,XMMRM,'); FOpCodeList.Add('vpsllq,1,1,1,ZMMREG_MZ,ZMMRM,IMM8,'); - FOpCodeList.Add('vpsllq,1,1,1,ZMMREG_MZ,8B32,IMM8,'); + FOpCodeList.Add('vpsllq,1,1,1,ZMMREG_MZ,8B64,IMM8,'); FOpCodeList.Add('vpsllw,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsllw,1,1,1,XMMREG_MZ,XMMRM,IMM8,'); FOpCodeList.Add('vpsllw,1,1,1,YMMREG_MZ,YMMREG,XMMRM,'); @@ -1187,11 +1187,11 @@ begin FOpCodeList.Add('vpsrlq,1,1,1,XMMREG_MZ,XMMRM,IMM8,'); FOpCodeList.Add('vpsrlq,1,1,1,XMMREG_MZ,2B64,IMM8,'); FOpCodeList.Add('vpsrlq,1,1,1,YMMREG_MZ,YMMRM,IMM8,'); - FOpCodeList.Add('vpsrlq,1,1,1,YMMREG_MZ,4B32,IMM8,'); + FOpCodeList.Add('vpsrlq,1,1,1,YMMREG_MZ,4B64,IMM8,'); FOpCodeList.Add('vpsrlq,1,1,1,YMMREG_MZ,YMMREG,XMMRM,'); FOpCodeList.Add('vpsrlq,1,1,1,ZMMREG_MZ,ZMMREG,XMMRM,'); FOpCodeList.Add('vpsrlq,1,1,1,ZMMREG_MZ,ZMMRM,IMM8,'); - FOpCodeList.Add('vpsrlq,1,1,1,ZMMREG_MZ,8B32,IMM8,'); + FOpCodeList.Add('vpsrlq,1,1,1,ZMMREG_MZ,8B64,IMM8,'); FOpCodeList.Add('vpsrlw,1,1,1,XMMREG_MZ,XMMRM,IMM8,'); FOpCodeList.Add('vpsrlw,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsrlw,1,1,1,YMMREG_MZ,YMMRM,IMM8,'); @@ -1210,9 +1210,9 @@ begin FOpCodeList.Add('vpsubq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsubq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpsubq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpsubq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpsubq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpsubq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpsubq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpsubq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpsubsb,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsubsb,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpsubsb,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); @@ -1242,9 +1242,9 @@ begin FOpCodeList.Add('vpunpckhqdq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpunpckhqdq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpunpckhqdq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpunpckhqdq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpunpckhqdq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpunpckhqdq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpunpckhqdq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpunpckhqdq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpunpckhwd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpunpckhwd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpunpckhwd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); @@ -1260,9 +1260,9 @@ begin FOpCodeList.Add('vpunpcklqdq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpunpcklqdq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpunpcklqdq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpunpcklqdq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpunpcklqdq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpunpcklqdq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpunpcklqdq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpunpcklqdq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpunpcklwd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpunpcklwd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpunpcklwd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); @@ -1287,9 +1287,9 @@ begin FOpCodeList.Add('vshufpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,IMM8'); FOpCodeList.Add('vshufpd,1,1,1,XMMREG_MZ,XMMREG,2B64,IMM8'); FOpCodeList.Add('vshufpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,IMM8'); - FOpCodeList.Add('vshufpd,1,1,1,YMMREG_MZ,YMMREG,4B32,IMM8'); + FOpCodeList.Add('vshufpd,1,1,1,YMMREG_MZ,YMMREG,4B64,IMM8'); FOpCodeList.Add('vshufpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,IMM8'); - FOpCodeList.Add('vshufpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,IMM8'); + FOpCodeList.Add('vshufpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,IMM8'); FOpCodeList.Add('vshufps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,IMM8'); FOpCodeList.Add('vshufps,1,1,1,XMMREG_MZ,XMMREG,4B32,IMM8'); FOpCodeList.Add('vshufps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,IMM8'); @@ -1299,9 +1299,9 @@ begin FOpCodeList.Add('vsqrtpd,1,1,1,XMMREG_MZ,XMMRM,,'); FOpCodeList.Add('vsqrtpd,1,1,1,XMMREG_MZ,2B64,,'); FOpCodeList.Add('vsqrtpd,1,1,1,YMMREG_MZ,YMMRM,,'); - FOpCodeList.Add('vsqrtpd,1,1,1,YMMREG_MZ,4B32,,'); + FOpCodeList.Add('vsqrtpd,1,1,1,YMMREG_MZ,4B64,,'); FOpCodeList.Add('vsqrtpd,1,1,1,ZMMREG_MZ,MEM512,,'); - FOpCodeList.Add('vsqrtpd,1,1,1,ZMMREG_MZ,8B32,,'); + FOpCodeList.Add('vsqrtpd,1,1,1,ZMMREG_MZ,8B64,,'); FOpCodeList.Add('vsqrtpd,1,1,1,ZMMREG_MZ,ZMMREG_ER,,'); FOpCodeList.Add('vsqrtps,1,1,1,XMMREG_MZ,XMMRM,,'); FOpCodeList.Add('vsqrtps,1,1,1,XMMREG_MZ,4B32,,'); @@ -1318,9 +1318,9 @@ begin FOpCodeList.Add('vsubpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vsubpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vsubpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vsubpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vsubpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vsubpd,1,1,1,ZMMREG_MZ,ZMMREG,MEM512,'); - FOpCodeList.Add('vsubpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vsubpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vsubpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMREG_ER,'); FOpCodeList.Add('vsubps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vsubps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); @@ -1344,9 +1344,9 @@ begin FOpCodeList.Add('vunpckhpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vunpckhpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vunpckhpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vunpckhpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vunpckhpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vunpckhpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vunpckhpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vunpckhpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vunpckhps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vunpckhps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vunpckhps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -1356,9 +1356,9 @@ begin FOpCodeList.Add('vunpcklpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vunpcklpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vunpcklpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vunpcklpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vunpcklpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vunpcklpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vunpcklpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vunpcklpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vunpcklps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vunpcklps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vunpcklps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -1368,9 +1368,9 @@ begin FOpCodeList.Add('vxorpd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vxorpd,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vxorpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vxorpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vxorpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vxorpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vxorpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vxorpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vxorps,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vxorps,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vxorps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -1454,25 +1454,25 @@ begin FOpCodeList.Add('vpermd,1,1,1,ZMMREG_MZ,ZMMREG,16B32,'); FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,MEM256,IMM8,'); FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,YMMREG,IMM8,'); - FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,4B32,IMM8,'); + FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,4B64,IMM8,'); FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpermpd,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,ZMMRM,IMM8,'); - FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,8B32,IMM8,'); + FOpCodeList.Add('vpermpd,1,1,1,ZMMREG_MZ,8B64,IMM8,'); FOpCodeList.Add('vpermps,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); FOpCodeList.Add('vpermps,1,1,1,YMMREG_MZ,YMMREG,8B32,'); FOpCodeList.Add('vpermps,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); FOpCodeList.Add('vpermps,1,1,1,ZMMREG_MZ,ZMMREG,16B32,'); FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,YMMRM,IMM8,'); - FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,4B32,IMM8,'); + FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,4B64,IMM8,'); FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpermq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,ZMMRM,IMM8,'); - FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,8B32,IMM8,'); + FOpCodeList.Add('vpermq,1,1,1,ZMMREG_MZ,8B64,IMM8,'); FOpCodeList.Add('vpmaskmovd,1,1,0,XMMREG,XMMREG,MEM128,'); FOpCodeList.Add('vpmaskmovd,1,1,0,MEM128,XMMREG,XMMREG,'); FOpCodeList.Add('vpmaskmovd,1,1,0,YMMREG,YMMREG,MEM256,'); @@ -1490,9 +1490,9 @@ begin FOpCodeList.Add('vpsllvq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsllvq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpsllvq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpsllvq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpsllvq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpsllvq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpsllvq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpsllvq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vpsravd,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsravd,1,1,1,XMMREG_MZ,XMMREG,4B32,'); FOpCodeList.Add('vpsravd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -1508,9 +1508,9 @@ begin FOpCodeList.Add('vpsrlvq,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); FOpCodeList.Add('vpsrlvq,1,1,1,XMMREG_MZ,XMMREG,2B64,'); FOpCodeList.Add('vpsrlvq,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); - FOpCodeList.Add('vpsrlvq,1,1,1,YMMREG_MZ,YMMREG,4B32,'); + FOpCodeList.Add('vpsrlvq,1,1,1,YMMREG_MZ,YMMREG,4B64,'); FOpCodeList.Add('vpsrlvq,1,1,1,ZMMREG_MZ,ZMMREG,ZMMRM,'); - FOpCodeList.Add('vpsrlvq,1,1,1,ZMMREG_MZ,ZMMREG,8B32,'); + FOpCodeList.Add('vpsrlvq,1,1,1,ZMMREG_MZ,ZMMREG,8B64,'); FOpCodeList.Add('vgatherdpd,1,1,0,XMMREG,XMEM32,XMMREG,'); FOpCodeList.Add('vgatherdpd,1,1,1,XMMREG_M,XMEM32,,'); From 84bf87b20dbacb2db9bc8770043968fe1d4e35d9 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 1 Dec 2020 05:43:17 +0000 Subject: [PATCH 010/116] working on new testmethods (memref-operands) git-svn-id: branches/tg74/avx512-0037785@47654 - --- compiler/x86/rax86.pas | 90 +++++++++++++++++++++++++----------------- 1 file changed, 54 insertions(+), 36 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index f765c88537..d72c4ff7a7 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1437,6 +1437,7 @@ procedure Tx86Instruction.SetInstructionOpsize; var i: integer; bBroadcastMemRef: boolean; + bExistMemRef: boolean; begin Result := False; @@ -1450,7 +1451,12 @@ procedure Tx86Instruction.SetInstructionOpsize; if bBroadcastMemRef then begin - opsize := S_NO; + case MemRefSizeBCST of + msbBCST32: opsize := S_L; + msbBCST64: opsize := S_Q; + else opsize := S_NO; + end; + result := true; end else @@ -1477,6 +1483,18 @@ procedure Tx86Instruction.SetInstructionOpsize; result := true; end; end; + end + else if not(MemRefSize in [msiMemRegSize]) then + begin + //bExistMemRef:=false; + + for i := 1 to ops do + if tx86operand(operands[1]).opr.typ in [OPR_REFERENCE,OPR_LOCAL] then + begin + opsize := tx86operand(operands[1]).opsize; + result := true; + break; + end; end; end; end; @@ -1955,41 +1973,41 @@ begin localscale,localgetoffset,localforceref); ai.oper[i-1]^.localoper^.localsegment:=localsegment; - if MemRefInfo(opcode).ExistsSSEAVX then - begin - asize := 0; - - case operands[i].size of - OS_32,OS_M32: if (operands[i].HasType) or - (MemRefInfo(opcode).MemRefSize = msiMem32) or - (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) - //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and - // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) - //) - then - asize:=OT_BITS32; - OS_64,OS_M64: if (operands[i].HasType) or - (MemRefInfo(opcode).MemRefSize = msiMem64) or - //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and - // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) - //) then - (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then - asize:=OT_BITS64; - OS_M128: if (operands[i].HasType) or - (MemRefInfo(opcode).MemRefSize = msiMem128) then - asize:=OT_BITS128; - OS_M256: if (operands[i].HasType) or - (MemRefInfo(opcode).MemRefSize = msiMem256) then - asize:=OT_BITS256; - OS_M512: if (operands[i].HasType) or - (MemRefInfo(opcode).MemRefSize = msiMem512) then - asize:=OT_BITS512; - else; - end; - - if asize<>0 then - ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; - end; + // if MemRefInfo(opcode).ExistsSSEAVX then + // begin + // asize := 0; + // + // case operands[i].size of + // OS_32,OS_M32: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSize = msiMem32) or + // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) + // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and + // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) + // //) + // then + // asize:=OT_BITS32; + // OS_64,OS_M64: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSize = msiMem64) or + // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and + // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) + // //) then + // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then + // asize:=OT_BITS64; + // OS_M128: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSize = msiMem128) then + //asize:=OT_BITS128; + // OS_M256: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSize = msiMem256) then + //asize:=OT_BITS256; + // OS_M512: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSize = msiMem512) then + //asize:=OT_BITS512; + // else; + // end; + // + // if asize<>0 then + // ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; + // end; end; OPR_REFERENCE: begin From 06b229e1c33157af5d90c1596dd62b675ae34bc8 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 2 Dec 2020 09:19:41 +0000 Subject: [PATCH 011/116] working on internal assembler-reader x86 opsize local var git-svn-id: branches/tg74/avx512-0037785@47663 - --- compiler/x86/rax86.pas | 41 +++++++++++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index d72c4ff7a7..44d5b3d1e9 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1451,12 +1451,13 @@ procedure Tx86Instruction.SetInstructionOpsize; if bBroadcastMemRef then begin - case MemRefSizeBCST of - msbBCST32: opsize := S_L; - msbBCST64: opsize := S_Q; - else opsize := S_NO; - end; + //case MemRefSizeBCST of + // msbBCST32: opsize := S_L; + // msbBCST64: opsize := S_Q; + // else opsize := S_NO; + //end; + opsize := S_NO; result := true; end else @@ -1476,7 +1477,8 @@ procedure Tx86Instruction.SetInstructionOpsize; opsize:=tx86operand(operands[1]).opsize; result := true; end; - 3: begin + 3,4: + begin if (tx86operand(operands[1]).opr.typ <> OPR_CONSTANT) then opsize:=tx86operand(operands[1]).opsize else opsize:=tx86operand(operands[2]).opsize; @@ -1489,9 +1491,9 @@ procedure Tx86Instruction.SetInstructionOpsize; //bExistMemRef:=false; for i := 1 to ops do - if tx86operand(operands[1]).opr.typ in [OPR_REFERENCE,OPR_LOCAL] then + if tx86operand(operands[i]).opr.typ in [OPR_REFERENCE,OPR_LOCAL] then begin - opsize := tx86operand(operands[1]).opsize; + opsize := tx86operand(operands[i]).opsize; result := true; break; end; @@ -1606,8 +1608,8 @@ begin end; //end; end; - 4 : - opsize:=tx86operand(operands[ops]).opsize; + 4 : if not CheckSSEAVX then + opsize:=tx86operand(operands[ops]).opsize; end; end; @@ -1973,6 +1975,25 @@ begin localscale,localgetoffset,localforceref); ai.oper[i-1]^.localoper^.localsegment:=localsegment; + // check for embedded broadcast + if MemRefInfo(opcode).ExistsSSEAVX then + begin + asize := 0; + + if ((operands[i] as tx86operand).vopext <> 0) and + (MemRefInfo(opcode).MemRefSizeBCST in [msbBCST32,msbBCST64]) then + begin + case operands[i].size of + OS_32,OS_M32: asize:=OT_BITS32; + OS_64,OS_M64: asize:=OT_BITS64; + else; + end; + end; + + if asize<>0 then + ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; + end; + // if MemRefInfo(opcode).ExistsSSEAVX then // begin // asize := 0; From 28fdba2c08f6fdee34557b1419e310e70b864a41 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 3 Dec 2020 16:24:00 +0000 Subject: [PATCH 012/116] working on new testmethods and bug-fixing size of (memref-operands | global and local variable git-svn-id: branches/tg74/avx512-0037785@47678 - --- compiler/i386/i386nop.inc | 2 +- compiler/i386/i386tab.inc | 96 +++++----------------------------- compiler/i8086/i8086nop.inc | 2 +- compiler/i8086/i8086tab.inc | 96 +++++----------------------------- compiler/ppcx64.lpi | 14 ++--- compiler/x86/aasmcpu.pas | 14 +++-- compiler/x86/rax86.pas | 25 ++++----- compiler/x86/x86ins.dat | 56 ++++++++++++-------- compiler/x86_64/x8664nop.inc | 2 +- compiler/x86_64/x8664tab.inc | 96 +++++----------------------------- tests/utils/avx/avxopcodes.pas | 4 +- 11 files changed, 105 insertions(+), 302 deletions(-) diff --git a/compiler/i386/i386nop.inc b/compiler/i386/i386nop.inc index 4e2e16f488..dae95022af 100644 --- a/compiler/i386/i386nop.inc +++ b/compiler/i386/i386nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4168; +4158; diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc index b84ebfeda2..3524db5ac7 100644 --- a/compiler/i386/i386tab.inc +++ b/compiler/i386/i386tab.inc @@ -10531,7 +10531,7 @@ ( opcode : A_VCVTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -10542,13 +10542,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -10587,7 +10580,7 @@ ( opcode : A_VCVTPD2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_tfv] ), @@ -10598,13 +10591,6 @@ code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#241#248#1#90#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPH2PS; ops : 2; @@ -10958,7 +10944,7 @@ ( opcode : A_VCVTTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -10969,13 +10955,6 @@ code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#241#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPS2DQ; ops : 2; @@ -21266,13 +21245,6 @@ code : #232#233#234#241#248#1#123#72; flags : [if_avx512] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#121#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2UDQ; ops : 2; @@ -21283,9 +21255,9 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#121#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTPD2UDQ; @@ -21311,7 +21283,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -21588,13 +21560,6 @@ code : #219#232#233#234#248#1#230#72; flags : [if_avx512] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#91#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTQQ2PS; ops : 2; @@ -21605,7 +21570,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; flags : [if_avx512] ), @@ -21633,7 +21598,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#91#72; flags : [if_avx512,if_tfv] ), @@ -21644,13 +21609,6 @@ code : #232#233#234#248#1#91#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#91#72; - flags : [if_avx512] - ), ( opcode : A_VCVTSD2USI; ops : 2; @@ -21756,13 +21714,6 @@ code : #232#233#234#241#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#120#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTTPD2UDQ; ops : 2; @@ -21773,7 +21724,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; flags : [if_avx512] ), @@ -21801,7 +21752,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#248#1#120#72; flags : [if_avx512,if_tfv] ), @@ -21812,13 +21763,6 @@ code : #232#233#234#248#1#120#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#248#1#120#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPD2UQQ; ops : 2; @@ -22239,13 +22183,6 @@ code : #219#232#233#234#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #220#232#234#248#1#122#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTUQQ2PS; ops : 2; @@ -22256,9 +22193,9 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #220#232#234#248#1#122#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTUQQ2PS; @@ -22284,7 +22221,7 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_tfv] ), @@ -22295,13 +22232,6 @@ code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#122#72; - flags : [if_avx512] - ), ( opcode : A_VCVTUSI2SD; ops : 3; diff --git a/compiler/i8086/i8086nop.inc b/compiler/i8086/i8086nop.inc index ceb214a46f..596abe4e2e 100644 --- a/compiler/i8086/i8086nop.inc +++ b/compiler/i8086/i8086nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4200; +4190; diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc index 59a948a851..c84bb020fb 100644 --- a/compiler/i8086/i8086tab.inc +++ b/compiler/i8086/i8086tab.inc @@ -10559,7 +10559,7 @@ ( opcode : A_VCVTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -10570,13 +10570,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -10615,7 +10608,7 @@ ( opcode : A_VCVTPD2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_tfv] ), @@ -10626,13 +10619,6 @@ code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#241#248#1#90#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPH2PS; ops : 2; @@ -10986,7 +10972,7 @@ ( opcode : A_VCVTTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -10997,13 +10983,6 @@ code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#241#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPS2DQ; ops : 2; @@ -21490,13 +21469,6 @@ code : #232#233#234#241#248#1#123#72; flags : [if_avx512] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#121#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2UDQ; ops : 2; @@ -21507,9 +21479,9 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#121#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTPD2UDQ; @@ -21535,7 +21507,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -21812,13 +21784,6 @@ code : #219#232#233#234#248#1#230#72; flags : [if_avx512] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#91#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTQQ2PS; ops : 2; @@ -21829,7 +21794,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; flags : [if_avx512] ), @@ -21857,7 +21822,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#91#72; flags : [if_avx512,if_tfv] ), @@ -21868,13 +21833,6 @@ code : #232#233#234#248#1#91#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#91#72; - flags : [if_avx512] - ), ( opcode : A_VCVTSD2USI; ops : 2; @@ -21980,13 +21938,6 @@ code : #232#233#234#241#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#120#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTTPD2UDQ; ops : 2; @@ -21997,7 +21948,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; flags : [if_avx512] ), @@ -22025,7 +21976,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#248#1#120#72; flags : [if_avx512,if_tfv] ), @@ -22036,13 +21987,6 @@ code : #232#233#234#248#1#120#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#248#1#120#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPD2UQQ; ops : 2; @@ -22463,13 +22407,6 @@ code : #219#232#233#234#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #220#232#234#248#1#122#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTUQQ2PS; ops : 2; @@ -22480,9 +22417,9 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #220#232#234#248#1#122#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTUQQ2PS; @@ -22508,7 +22445,7 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_tfv] ), @@ -22519,13 +22456,6 @@ code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#122#72; - flags : [if_avx512] - ), ( opcode : A_VCVTUSI2SD; ops : 3; diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index d10e934a3e..6fcb6c71e8 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -1,7 +1,7 @@ - + @@ -22,18 +22,10 @@ - + + - - - - - - - - - diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index ecadd5e0eb..198a09cc5b 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -1829,9 +1829,17 @@ implementation if (insot and OT_SIZE_MASK) = 0 then begin case insot and (OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of - OT_XMMRM: insot := insot or OT_BITS128; - OT_YMMRM: insot := insot or OT_BITS256; - OT_ZMMRM: insot := insot or OT_BITS512; + //OT_XMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize128 + // then insot := insot or OT_BITS128; + //OT_YMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize256 + // then insot := insot or OT_BITS256; + //OT_ZMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize512 + // then insot := insot or OT_BITS512; + + OT_MEM128: insot := insot or OT_BITS128; + OT_MEM256: insot := insot or OT_BITS256; + OT_MEM512: insot := insot or OT_BITS512; + else ; end; diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 44d5b3d1e9..c921b446e7 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -726,13 +726,13 @@ begin msiYMem64, msiZMem64: ; // ignore; gather/scatter opcodes haven a fixed element-size, not a fixed memory-size // the vector-register have indices with base of the memory-address in the memory-operand - msiMultipleMinSize8, - msiMultipleMinSize16, - msiMultipleMinSize32, - msiMultipleMinSize64, - msiMultipleMinSize128, - msiMultipleMinSize256, - msiMultipleMinSize512: ; // ignore + msiMultipleMinSize8: memrefsize := 8; + msiMultipleMinSize16: memrefsize := 16; + msiMultipleMinSize32: memrefsize := 32; + msiMultipleMinSize64: memrefsize := 64; + msiMultipleMinSize128: memrefsize := 128; + msiMultipleMinSize256: memrefsize := 256; + msiMultipleMinSize512: memrefsize := 512; msiNoSize, msiNoMemRef, msiUnknown, @@ -2005,24 +2005,25 @@ begin // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) // //) - // then + // then // asize:=OT_BITS32; // OS_64,OS_M64: if (operands[i].HasType) or + // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) // (MemRefInfo(opcode).MemRefSize = msiMem64) or // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) // //) then // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then - // asize:=OT_BITS64; + // asize:=OT_BITS64; // OS_M128: if (operands[i].HasType) or // (MemRefInfo(opcode).MemRefSize = msiMem128) then - //asize:=OT_BITS128; + // //asize:=OT_BITS128; // OS_M256: if (operands[i].HasType) or // (MemRefInfo(opcode).MemRefSize = msiMem256) then - //asize:=OT_BITS256; + // //asize:=OT_BITS256; // OS_M512: if (operands[i].HasType) or // (MemRefInfo(opcode).MemRefSize = msiMem512) then - //asize:=OT_BITS512; + // //asize:=OT_BITS512; // else; // end; // diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index deda5d6155..6b44fe1818 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -4184,9 +4184,10 @@ xmmreg_mz,ymmreg \334\350\352\362\364\370\1\xE6\110 xmmreg_mz,bmem64 \334\350\352\370\1\xE6\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \334\350\352\364\370\1\xE6\110 AVX512,BCST4,TFV -ymmreg_mz,mem512 \334\350\351\352\370\1\xE6\110 AVX512,TFV +;ymmreg_mz,mem512 \334\350\351\352\370\1\xE6\110 AVX512,TFV +ymmreg_mz,zmmrm_er \334\350\351\352\370\1\xE6\110 AVX512,TFV ymmreg_mz,bmem64 \334\350\351\352\370\1\xE6\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_er \334\350\351\352\370\1\xE6\110 AVX512 +;ymmreg_mz,zmmreg_er \334\350\351\352\370\1\xE6\110 AVX512 ; VCVTPD2PS xmmreg_mz,mem256 must come first - map MemRefSize 256bits correct @@ -4198,9 +4199,10 @@ xmmreg_mz,ymmreg \350\352\361\362\364\370\1\x5A\110 xmmreg_mz,xmmrm \350\352\361\362\370\1\x5A\110 AVX,SANDYBRIDGE,TFV xmmreg_mz,bmem64 \350\352\361\370\1\x5A\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\361\364\370\1\x5A\110 AVX512,BCST4,TFV -ymmreg_mz,mem512 \350\351\352\361\370\1\x5A\110 AVX512,TFV +;ymmreg_mz,mem512 \350\351\352\361\370\1\x5A\110 AVX512,TFV +ymmreg_mz,zmmrm_er \350\351\352\361\370\1\x5A\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\361\370\1\x5A\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_er \350\351\352\361\370\1\x5A\110 AVX512 +;ymmreg_mz,zmmreg_er \350\351\352\361\370\1\x5A\110 AVX512 [VCVTPH2PS] (Ch_Wop2, Ch_Rop1) @@ -4304,9 +4306,10 @@ xmmreg_mz,ymmreg \350\352\361\362\364\370\1\xE6\110 xmmreg_mz,xmmrm \350\352\361\362\370\1\xE6\110 AVX,SANDYBRIDGE,AVX512,TFV xmmreg_mz,bmem64 \350\352\361\370\1\xE6\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\361\364\370\1\xE6\110 AVX512,BCST4,TFV -ymmreg_mz,mem512 \350\351\352\361\370\1\xE6\110 AVX512,TFV +;ymmreg_mz,mem512 \350\351\352\361\370\1\xE6\110 AVX512,TFV +ymmreg_mz,zmmrm_sae \350\351\352\361\370\1\xE6\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\361\370\1\xE6\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_sae \350\351\352\361\370\1\xE6\110 AVX512 +;ymmreg_mz,zmmreg_sae \350\351\352\361\370\1\xE6\110 AVX512 [VCVTTPS2DQ] (Ch_Wop2, Ch_Rop1) @@ -7305,15 +7308,14 @@ zmmreg_mz,zmmreg_er \350\351\352\361\370\1\x7B\110 [VCVTPD2UDQ, vcvtpd2udqN] (Ch_All) -xmmreg_mz,mem128 \350\352\370\1\x79\110 AVX512,TFV xmmreg_mz,mem256 \350\352\364\370\1\x79\110 AVX512,TFV -xmmreg_mz,xmmreg \350\352\370\1\x79\110 AVX512 +xmmreg_mz,xmmrm \350\352\370\1\x79\110 AVX512,TFV xmmreg_mz,bmem64 \350\352\370\1\x79\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x79\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x79\110 AVX512 -ymmreg_mz,mem512 \350\351\352\370\1\x79\110 AVX512,TFV +;ymmreg_mz,mem512 \350\351\352\370\1\x79\110 AVX512,TFV +ymmreg_mz,zmmrm_er \350\351\352\370\1\x79\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x79\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_er \350\351\352\370\1\x79\110 AVX512 [VCVTPD2UQQ] (Ch_All) @@ -7367,17 +7369,22 @@ zmmreg_mz,mem512 \333\350\351\352\370\1\xE6\110 zmmreg_mz,bmem64 \333\350\351\352\370\1\xE6\110 AVX512,TFV zmmreg_mz,zmmreg_er \333\350\351\352\370\1\xE6\110 AVX512 +; VCVTQQ2PS xmmreg_mz,mem256 must come first - map MemRefSize 256,512bits correct +; map all other MemrefSize (without broasdcast MemRef) to xmmreg, xmmrm +; [VCVTQQ2PS,vcvtqq2psN] (Ch_All) -xmmreg_mz,mem128 \350\352\370\1\x5B\110 AVX512,TFV +;xmmreg_mz,mem128 \350\352\370\1\x5B\110 AVX512,TFV xmmreg_mz,mem256 \350\352\364\370\1\x5B\110 AVX512,TFV -xmmreg_mz,xmmreg \350\352\370\1\x5B\110 AVX512 +;xmmreg_mz,xmmreg \350\352\370\1\x5B\110 AVX512 +xmmreg_mz,xmmrm \350\352\370\1\x5B\110 AVX512 xmmreg_mz,bmem64 \350\352\370\1\x5B\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x5B\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x5B\110 AVX512 -ymmreg_mz,mem512 \350\351\352\370\1\x5B\110 AVX512,TFV +;ymmreg_mz,mem512 \350\351\352\370\1\x5B\110 AVX512,TFV +ymmreg_mz,zmmrm_er \350\351\352\370\1\x5B\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x5B\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_er \350\351\352\370\1\x5B\110 AVX512 +;ymmreg_mz,zmmreg_er \350\351\352\370\1\x5B\110 AVX512 [VCVTSD2USI] (Ch_All) @@ -7403,17 +7410,22 @@ zmmreg_mz,mem512 \350\351\352\361\370\1\x7A\110 zmmreg_mz,bmem64 \350\351\352\361\370\1\x7A\110 AVX512,TFV zmmreg_mz,zmmreg_sae \350\351\352\361\370\1\x7A\110 AVX512 + +; VCVTTPD2UDQ xmmreg_mz,mem256 must come first - map MemRefSize 256,512bits correct +; map all other MemrefSize (without broasdcast MemRef) to kreg_m, xmmrm [VCVTTPD2UDQ,vcvttpd2udqN] (Ch_All) -xmmreg_mz,mem128 \350\352\370\1\x78\110 AVX512,TFV +;xmmreg_mz,mem128 \350\352\370\1\x78\110 AVX512,TFV xmmreg_mz,mem256 \350\352\364\370\1\x78\110 AVX512,TFV -xmmreg_mz,xmmreg \350\352\370\1\x78\110 AVX512 +;xmmreg_mz,xmmreg \350\352\370\1\x78\110 AVX512 +xmmreg_mz,xmmrm \350\352\370\1\x78\110 AVX512 xmmreg_mz,bmem64 \350\352\370\1\x78\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x78\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x78\110 AVX512 -ymmreg_mz,mem512 \350\351\352\370\1\x78\110 AVX512,TFV +;ymmreg_mz,mem512 \350\351\352\370\1\x78\110 AVX512,TFV +ymmreg_mz,zmmrm_sae \350\351\352\370\1\x78\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x78\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_sae \350\351\352\370\1\x78\110 AVX512 +;ymmreg_mz,zmmreg_sae \350\351\352\370\1\x78\110 AVX512 [VCVTTPD2UQQ] (Ch_All) @@ -7504,15 +7516,15 @@ zmmreg_mz,zmmreg_er \333\350\351\352\370\1\x7A\110 [VCVTUQQ2PS,vcvtuqq2psN] (Ch_All) -xmmreg_mz,mem128 \334\350\352\370\1\x7A\110 AVX512,TFV xmmreg_mz,mem256 \334\350\352\364\370\1\x7A\110 AVX512,TFV -xmmreg_mz,xmmreg \334\350\352\370\1\x7A\110 AVX512 +xmmreg_mz,xmmrm \334\350\352\370\1\x7A\110 AVX512,TFV xmmreg_mz,bmem64 \334\350\352\370\1\x7A\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \334\350\352\364\370\1\x7A\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \334\350\352\364\370\1\x7A\110 AVX512 -ymmreg_mz,mem512 \334\350\351\352\370\1\x7A\110 AVX512,TFV +;ymmreg_mz,mem512 \334\350\351\352\370\1\x7A\110 AVX512,TFV +ymmreg_mz,zmmrm_er \334\350\351\352\370\1\x7A\110 AVX512,TFV ymmreg_mz,bmem64 \334\350\351\352\370\1\x7A\110 AVX512,BCST8,TFV -ymmreg_mz,zmmreg_er \334\350\351\352\370\1\x7A\110 AVX512 +;ymmreg_mz,zmmreg_er \334\350\351\352\370\1\x7A\110 AVX512 ; special handling - gas suffix "S" =>> instructions-opsize = source-operand diff --git a/compiler/x86_64/x8664nop.inc b/compiler/x86_64/x8664nop.inc index 99f9877d90..4b57c937c2 100644 --- a/compiler/x86_64/x8664nop.inc +++ b/compiler/x86_64/x8664nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4232; +4222; diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc index 978443453a..5e38b3747b 100644 --- a/compiler/x86_64/x8664tab.inc +++ b/compiler/x86_64/x8664tab.inc @@ -10832,7 +10832,7 @@ ( opcode : A_VCVTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -10843,13 +10843,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -10888,7 +10881,7 @@ ( opcode : A_VCVTPD2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_tfv] ), @@ -10899,13 +10892,6 @@ code : #232#233#234#241#248#1#90#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#241#248#1#90#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPH2PS; ops : 2; @@ -11273,7 +11259,7 @@ ( opcode : A_VCVTTPD2DQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_tfv] ), @@ -11284,13 +11270,6 @@ code : #232#233#234#241#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#241#248#1#230#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPS2DQ; ops : 2; @@ -21700,13 +21679,6 @@ code : #232#233#234#241#248#1#123#72; flags : [if_avx512] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#121#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2UDQ; ops : 2; @@ -21717,9 +21689,9 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#121#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTPD2UDQ; @@ -21745,7 +21717,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -22022,13 +21994,6 @@ code : #219#232#233#234#248#1#230#72; flags : [if_avx512] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#91#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTQQ2PS; ops : 2; @@ -22039,7 +22004,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; flags : [if_avx512] ), @@ -22067,7 +22032,7 @@ ( opcode : A_VCVTQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#91#72; flags : [if_avx512,if_tfv] ), @@ -22078,13 +22043,6 @@ code : #232#233#234#248#1#91#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#91#72; - flags : [if_avx512] - ), ( opcode : A_VCVTSD2USI; ops : 2; @@ -22190,13 +22148,6 @@ code : #232#233#234#241#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #232#234#248#1#120#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTTPD2UDQ; ops : 2; @@ -22207,7 +22158,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; flags : [if_avx512] ), @@ -22235,7 +22186,7 @@ ( opcode : A_VCVTTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_sae,ot_none,ot_none); code : #232#233#234#248#1#120#72; flags : [if_avx512,if_tfv] ), @@ -22246,13 +22197,6 @@ code : #232#233#234#248#1#120#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_sae,ot_none,ot_none); - code : #232#233#234#248#1#120#72; - flags : [if_avx512] - ), ( opcode : A_VCVTTPD2UQQ; ops : 2; @@ -22673,13 +22617,6 @@ code : #219#232#233#234#248#1#122#72; flags : [if_avx512] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_xmmreg_mz,ot_memory or ot_bits128,ot_none,ot_none); - code : #220#232#234#248#1#122#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTUQQ2PS; ops : 2; @@ -22690,9 +22627,9 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_xmmreg_mz,ot_xmmreg,ot_none,ot_none); + optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #220#232#234#248#1#122#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTUQQ2PS; @@ -22718,7 +22655,7 @@ ( opcode : A_VCVTUQQ2PS; ops : 2; - optypes : (ot_ymmreg_mz,ot_memory or ot_bits512,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_tfv] ), @@ -22729,13 +22666,6 @@ code : #220#232#233#234#248#1#122#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTUQQ2PS; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #220#232#233#234#248#1#122#72; - flags : [if_avx512] - ), ( opcode : A_VCVTUSI2SD; ops : 3; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index dbfae9c23a..db789e98c8 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -399,9 +399,9 @@ begin FOpCodeList.Add('vcmppd,1,1,1,KREG_M,XMMREG,XMMRM,IMM8'); FOpCodeList.Add('vcmppd,1,1,1,KREG_M,XMMREG,2B64,IMM8'); FOpCodeList.Add('vcmppd,1,1,1,KREG_M,YMMREG,YMMRM,IMM8'); - FOpCodeList.Add('vcmppd,1,1,1,KREG_M,YMMREG,4B32,IMM8'); + FOpCodeList.Add('vcmppd,1,1,1,KREG_M,YMMREG,4B64,IMM8'); FOpCodeList.Add('vcmppd,1,1,1,KREG_M,ZMMREG,MEM512,IMM8'); - FOpCodeList.Add('vcmppd,1,1,1,KREG_M,ZMMREG,8B32,IMM8'); + FOpCodeList.Add('vcmppd,1,1,1,KREG_M,ZMMREG,8B64,IMM8'); FOpCodeList.Add('vcmppd,1,1,1,KREG_M,ZMMREG,ZMMREG_SAE,IMM8'); FOpCodeList.Add('vcmppd,1,1,0,XMMREG,XMMREG,XMMRM,IMM8'); FOpCodeList.Add('vcmppd,1,1,0,YMMREG,YMMREG,YMMRM,IMM8'); From d8d472cf68aaa59c255456d23a5698d70858c45f Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 4 Dec 2020 08:35:00 +0000 Subject: [PATCH 013/116] bugfix internal assembler-reader x86 opsize local va git-svn-id: branches/tg74/avx512-0037785@47681 - --- compiler/i386/i386tab.inc | 16 ++++---- compiler/i8086/i8086tab.inc | 16 ++++---- compiler/ppcx64.lpi | 12 +++++- compiler/x86/aasmcpu.pas | 9 +++++ compiler/x86/rax86.pas | 73 ++++++++++++++++++++++++++++++++---- compiler/x86/x86ins.dat | 1 + compiler/x86_64/x8664tab.inc | 16 ++++---- 7 files changed, 110 insertions(+), 33 deletions(-) diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc index 3524db5ac7..f1e13131c8 100644 --- a/compiler/i386/i386tab.inc +++ b/compiler/i386/i386tab.inc @@ -10542,6 +10542,13 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), + ( + opcode : A_VCVTPD2DQ; + ops : 2; + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + code : #220#232#233#234#248#1#230#72; + flags : [if_avx512,if_tfv] + ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -21283,7 +21290,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -21294,13 +21301,6 @@ code : #232#233#234#248#1#121#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#121#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2UQQ; ops : 2; diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc index c84bb020fb..2f5f2b0c63 100644 --- a/compiler/i8086/i8086tab.inc +++ b/compiler/i8086/i8086tab.inc @@ -10570,6 +10570,13 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), + ( + opcode : A_VCVTPD2DQ; + ops : 2; + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + code : #220#232#233#234#248#1#230#72; + flags : [if_avx512,if_tfv] + ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -21507,7 +21514,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -21518,13 +21525,6 @@ code : #232#233#234#248#1#121#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#121#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2UQQ; ops : 2; diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index 6fcb6c71e8..5819327b82 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -22,10 +22,18 @@ - - + + + + + + + + + + diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index 198a09cc5b..bf48134dad 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -376,6 +376,9 @@ interface ExistsSSEAVX : boolean; ConstSize : TConstSizeInfo; BCSTTypes : Set of TMemRefSizeInfoBCSTType; + RegXMMSizeMask : int64; + RegYMMSizeMask : int64; + RegZMMSizeMask : int64; end; @@ -5342,6 +5345,7 @@ implementation inc(insentry); end; + if InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX then begin case RegBCSTSizeMask of @@ -5493,6 +5497,11 @@ implementation begin InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiNoMemRef; end; + + InsTabMemRefSizeInfoCache^[AsmOp].RegXMMSizeMask:=RegXMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask; + end; end; diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index c921b446e7..2da28d1f41 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -456,6 +456,21 @@ var mmregs: Set of TSubregister; multiplicator: integer; bcst1,bcst2: string; + + function ScanLowestActiveBit(aValue: int64): int64; + var + i: integer; + begin + result := 0; + + for i := 0 to 63 do + if aValue and (1 shl i) <> 0 then + begin + result := 1 shl i; + break; + end; + end; + begin ExistsMemRefNoSize := false; ExistsMemRef := false; @@ -726,13 +741,57 @@ begin msiYMem64, msiZMem64: ; // ignore; gather/scatter opcodes haven a fixed element-size, not a fixed memory-size // the vector-register have indices with base of the memory-address in the memory-operand - msiMultipleMinSize8: memrefsize := 8; - msiMultipleMinSize16: memrefsize := 16; - msiMultipleMinSize32: memrefsize := 32; - msiMultipleMinSize64: memrefsize := 64; - msiMultipleMinSize128: memrefsize := 128; - msiMultipleMinSize256: memrefsize := 256; - msiMultipleMinSize512: memrefsize := 512; + // msiMultipleMinSize8: memrefsize := 8; + // msiMultipleMinSize16: memrefsize := 16; + // msiMultipleMinSize32: memrefsize := 32; + // msiMultipleMinSize64: memrefsize := 64; + //msiMultipleMinSize128: memrefsize := 128; + //msiMultipleMinSize256: memrefsize := 256; + //msiMultipleMinSize512: memrefsize := 512; + msiMultipleMinSize8, + msiMultipleMinSize16, + msiMultipleMinSize32, + msiMultipleMinSize64, + msiMultipleMinSize128, + msiMultipleMinSize256, + msiMultipleMinSize512: + begin + for j := 1 to ops do + begin + if operands[j].Opr.Typ = OPR_REGISTER then + begin + case getsubreg(operands[j].opr.reg) of + R_SUBMMX: begin + memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegXMMSizeMask); + break; + end; + R_SUBMMY: begin + memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegYMMSizeMask); + break; + end; + R_SUBMMZ: begin + memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegZMMSizeMask); + break; + end; + else; + end; + end; + end; + + if memrefsize = -1 then + begin + case MemRefInfo(opcode).MemRefSize of + msiMultipleMinSize8: memrefsize := 8; + msiMultipleMinSize16: memrefsize := 16; + msiMultipleMinSize32: memrefsize := 32; + msiMultipleMinSize64: memrefsize := 64; + msiMultipleMinSize128: memrefsize := 128; + msiMultipleMinSize256: memrefsize := 256; + msiMultipleMinSize512: memrefsize := 512; + else; + end; + end; + end; msiNoSize, msiNoMemRef, msiUnknown, diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index 6b44fe1818..bc5c8d8572 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -4188,6 +4188,7 @@ xmmreg_mz,bmem64 \334\350\352\364\370\1\xE6\110 ymmreg_mz,zmmrm_er \334\350\351\352\370\1\xE6\110 AVX512,TFV ymmreg_mz,bmem64 \334\350\351\352\370\1\xE6\110 AVX512,BCST8,TFV ;ymmreg_mz,zmmreg_er \334\350\351\352\370\1\xE6\110 AVX512 +ymmreg_mz,zmmrm \334\350\351\352\370\1\xE6\110 AVX512,TFV ; VCVTPD2PS xmmreg_mz,mem256 must come first - map MemRefSize 256bits correct diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc index 5e38b3747b..df80ca4a14 100644 --- a/compiler/x86_64/x8664tab.inc +++ b/compiler/x86_64/x8664tab.inc @@ -10843,6 +10843,13 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), + ( + opcode : A_VCVTPD2DQ; + ops : 2; + optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + code : #220#232#233#234#248#1#230#72; + flags : [if_avx512,if_tfv] + ), ( opcode : A_VCVTPD2PS; ops : 2; @@ -21717,7 +21724,7 @@ ( opcode : A_VCVTPD2UDQ; ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); + optypes : (ot_ymmreg_mz,ot_zmmrm_er,ot_none,ot_none); code : #232#233#234#248#1#121#72; flags : [if_avx512,if_tfv] ), @@ -21728,13 +21735,6 @@ code : #232#233#234#248#1#121#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2UDQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmreg_er,ot_none,ot_none); - code : #232#233#234#248#1#121#72; - flags : [if_avx512] - ), ( opcode : A_VCVTPD2UQQ; ops : 2; From b2615a9ba11f613a7920efd59b2199cfbc4f4017 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 4 Dec 2020 16:19:48 +0000 Subject: [PATCH 014/116] working on new testmethods and bug-fixing size of (memref-operands | global and local variable git-svn-id: branches/tg74/avx512-0037785@47685 - --- compiler/x86/rax86.pas | 55 ++++++++------- tests/utils/avx/asmtestgenerator.pas | 102 +++++++++++++++++++++++++++ tests/utils/avx/avxopcodes.pas | 67 +++++++++++++++++- 3 files changed, 198 insertions(+), 26 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 2da28d1f41..ea762d5ab2 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -72,7 +72,7 @@ type procedure FixupOpcode;virtual; { opcode adding } function ConcatInstruction(p : TAsmList) : tai;override; - function getstring: string; + function getstring(aAddMemRefSize: boolean = true): string; { returns true, if the opcode might have an extension as used by AVX512 } function MightHaveExtension : boolean; end; @@ -457,20 +457,22 @@ var multiplicator: integer; bcst1,bcst2: string; - function ScanLowestActiveBit(aValue: int64): int64; + function ScanLowestOpsize(aValue: int64): int64; var i: integer; begin result := 0; - for i := 0 to 63 do - if aValue and (1 shl i) <> 0 then - begin - result := 1 shl i; - break; - end; + if aValue and OT_BITS8 = OT_BITS8 then result := 8 + else if aValue and OT_BITS16 = OT_BITS16 then result := 16 + else if aValue and OT_BITS32 = OT_BITS32 then result := 32 + else if aValue and OT_BITS64 = OT_BITS64 then result := 64 + else if aValue and OT_BITS128 = OT_BITS128 then result := 128 + else if aValue and OT_BITS256 = OT_BITS256 then result := 256 + else if aValue and OT_BITS512 = OT_BITS512 then result := 512; end; + begin ExistsMemRefNoSize := false; ExistsMemRef := false; @@ -762,15 +764,15 @@ begin begin case getsubreg(operands[j].opr.reg) of R_SUBMMX: begin - memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegXMMSizeMask); + memrefsize := ScanLowestOpsize(MemRefInfo(opcode).RegXMMSizeMask); break; end; R_SUBMMY: begin - memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegYMMSizeMask); + memrefsize := ScanLowestOpsize(MemRefInfo(opcode).RegYMMSizeMask); break; end; R_SUBMMZ: begin - memrefsize := ScanLowestActiveBit(MemRefInfo(opcode).RegZMMSizeMask); + memrefsize := ScanLowestOpsize(MemRefInfo(opcode).RegZMMSizeMask); break; end; else; @@ -861,7 +863,8 @@ begin if memoffset < 0 then begin Message2(asmr_w_check_mem_operand_negative_offset, - std_op2str[opcode], + //std_op2str[opcode], + getstring(false), ToStr(memoffset)); end else if ((tx86operand(operands[i]).hastype) and (memopsize < memrefsize)) or @@ -872,7 +875,8 @@ begin if memoffset = 0 then begin Message3(asmr_w_check_mem_operand_size3, - std_op2str[opcode], + //std_op2str[opcode], + getstring(false), ToStr(memopsize), ToStr(memrefsize) ); @@ -880,7 +884,8 @@ begin else begin Message4(asmr_w_check_mem_operand_size_offset, - std_op2str[opcode], + //std_op2str[opcode], + getstring(false), ToStr(memopsize), ToStr(memrefsize), ToStr(memoffset) @@ -933,7 +938,7 @@ begin tx86operand(operands[i]).opsize := S_B; tx86operand(operands[i]).size := OS_8; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"8 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"8 bit memory operand"'); end; msiMem16: begin @@ -945,7 +950,7 @@ begin tx86operand(operands[i]).opsize := S_W; tx86operand(operands[i]).size := OS_16; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"16 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"16 bit memory operand"'); end; msiMem32: begin @@ -957,7 +962,7 @@ begin tx86operand(operands[i]).opsize := S_L; tx86operand(operands[i]).size := OS_32; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"32 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"32 bit memory operand"'); end; msiMem64: begin @@ -969,7 +974,7 @@ begin tx86operand(operands[i]).opsize := S_Q; tx86operand(operands[i]).size := OS_M64; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"64 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"64 bit memory operand"'); end; msiMem128: begin @@ -981,7 +986,7 @@ begin tx86operand(operands[i]).opsize := S_XMM; tx86operand(operands[i]).size := OS_M128; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"128 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"128 bit memory operand"'); end; msiMem256: begin @@ -995,7 +1000,7 @@ begin tx86operand(operands[i]).size := OS_M256; opsize := S_YMM; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"256 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"256 bit memory operand"'); end; msiMem512: begin @@ -1009,7 +1014,7 @@ begin tx86operand(operands[i]).size := OS_M512; opsize := S_ZMM; - Message2(asmr_w_check_mem_operand_automap_multiple_size, std_op2str[opcode], '"512 bit memory operand"'); + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"512 bit memory operand"'); end; msiMemRegSize: @@ -2172,7 +2177,7 @@ begin result:=ai; end; -function Tx86Instruction.getstring: string; +function Tx86Instruction.getstring(aAddMemRefSize: boolean): string; var i : longint; s, sval : string; @@ -2184,7 +2189,7 @@ begin begin with operands[i] as Tx86Operand do begin - if i=0 then + if i=1 then s:=s+' ' else s:=s+','; @@ -2234,7 +2239,9 @@ begin OPR_LOCAL, OPR_REFERENCE: begin s:=s + 'mem'; - addsize:=true; + + if aAddMemRefSize then + addsize:=true; end; else s:=s + '???'; end; diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index f9072a868e..a91d5ed112 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -1985,9 +1985,22 @@ begin Item.Values.Add(' lOWord'); Item.Values.Add(' gOWord'); + Item.Values.Add(' clOWord'); + Item.Values.Add(' cgOWord'); Item.Values.Add(' oword lOWord'); Item.Values.Add(' oword gOWord'); + Item.Values.Add(' oword clOWord'); + Item.Values.Add(' oword cgOWord'); + + Item.Values.Add(' byte lOWord'); + Item.Values.Add(' byte gOWord'); + Item.Values.Add(' byte clOWord'); + Item.Values.Add(' byte cgOWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + end else if (AnsiSameText(sl_Operand, 'XMMRM8')) or @@ -2004,6 +2017,15 @@ begin Item.Values.Add('lbyte'); Item.Values.Add('gbyte'); + Item.Values.Add('clbyte'); + Item.Values.Add('cgbyte'); + + Item.Values.Add('byte lbyte'); + Item.Values.Add('byte gbyte'); + Item.Values.Add('byte clbyte'); + Item.Values.Add('byte cgbyte'); + + end else if (AnsiSameText(sl_Operand, 'XMMRM16')) or (AnsiSameText(sl_Operand, 'XMMRM16_M')) or @@ -2018,6 +2040,14 @@ begin Item.Values.Add('lword'); Item.Values.Add('gword'); + Item.Values.Add('clword'); + Item.Values.Add('cgword'); + + Item.Values.Add('word lword'); + Item.Values.Add('word gword'); + Item.Values.Add('word clword'); + Item.Values.Add('word cgword'); + end else if (AnsiSameText(sl_Operand, 'YMMREG')) or (AnsiSameText(sl_Operand, 'YMMREG_M')) or @@ -2045,6 +2075,14 @@ begin Item.Values.Add('lYWord'); Item.Values.Add('gYWord'); + Item.Values.Add('clYWord'); + Item.Values.Add('cgYWord'); + + Item.Values.Add('yword lYWord'); + Item.Values.Add('yword gYWord'); + Item.Values.Add('yword clYWord'); + Item.Values.Add('yword cgYWord'); + end else if (AnsiSameText(sl_Operand, 'ZMMREG')) or (AnsiSameText(sl_Operand, 'ZMMREG_M')) or @@ -2072,6 +2110,14 @@ begin Item.Values.Add('lZWord'); Item.Values.Add('gZWord'); + Item.Values.Add('clZWord'); + Item.Values.Add('cgZWord'); + + Item.Values.Add('zword lZWord'); + Item.Values.Add('zword gZWord'); + Item.Values.Add('zword clZWord'); + Item.Values.Add('zword cgZWord'); + end else if AnsiSameText(sl_Operand, 'MEM8') then begin @@ -2081,6 +2127,14 @@ begin Item.Values.Add('lByte'); Item.Values.Add('gByte'); + Item.Values.Add('clByte'); + Item.Values.Add('cgByte'); + + Item.Values.Add('byte lByte'); + Item.Values.Add('byte gByte'); + Item.Values.Add('byte clByte'); + Item.Values.Add('byte cgByte'); + end else if AnsiSameText(sl_Operand, 'MEM16') or AnsiSameText(sl_Operand, 'MEM16_M') then @@ -2091,6 +2145,14 @@ begin Item.Values.Add('lWord'); Item.Values.Add('gWord'); + Item.Values.Add('clWord'); + Item.Values.Add('cgWord'); + + Item.Values.Add('word lWord'); + Item.Values.Add('word gWord'); + Item.Values.Add('word clWord'); + Item.Values.Add('word cgWord'); + end else if AnsiSameText(sl_Operand, 'MEM32') or AnsiSameText(sl_Operand, 'MEM32_M') or @@ -2102,6 +2164,14 @@ begin Item.Values.Add('lDWord'); Item.Values.Add('gDWord'); + Item.Values.Add('clDWord'); + Item.Values.Add('cgDWord'); + + Item.Values.Add('dword lDWord'); + Item.Values.Add('dword gDWord'); + Item.Values.Add('dword clDWord'); + Item.Values.Add('dword cgDWord'); + end else if (AnsiSameText(sl_Operand, 'MEM64')) or (AnsiSameText(sl_Operand, 'MEM64_M')) or @@ -2113,6 +2183,14 @@ begin Item.Values.Add('lQWord'); Item.Values.Add('gQWord'); + Item.Values.Add('clQWord'); + Item.Values.Add('cgQWord'); + + Item.Values.Add('qword lQWord'); + Item.Values.Add('qword gQWord'); + Item.Values.Add('qword clQWord'); + Item.Values.Add('qword cgQWord'); + end else if (AnsiSameText(sl_Operand, 'MEM128')) or (AnsiSameText(sl_Operand, 'MEM128_M')) or @@ -2124,6 +2202,14 @@ begin Item.Values.Add('lOWord'); Item.Values.Add('gOWord'); + Item.Values.Add('clOWord'); + Item.Values.Add('cgOWord'); + + Item.Values.Add('oword lOWord'); + Item.Values.Add('oword gOWord'); + Item.Values.Add('oword clOWord'); + Item.Values.Add('oword cgOWord'); + end else if (AnsiSameText(sl_Operand, 'MEM256')) or (AnsiSameText(sl_Operand, 'MEM256_M')) or @@ -2135,6 +2221,14 @@ begin Item.Values.Add('lYWord'); Item.Values.Add('gYWord'); + Item.Values.Add('clYWord'); + Item.Values.Add('cgYWord'); + + Item.Values.Add('yword lYWord'); + Item.Values.Add('yword gYWord'); + Item.Values.Add('yword clYWord'); + Item.Values.Add('yword cgYWord'); + end else if (AnsiSameText(sl_Operand, 'MEM512')) or (AnsiSameText(sl_Operand, 'MEM512_M')) or @@ -2146,6 +2240,14 @@ begin Item.Values.Add('lZWord'); Item.Values.Add('gZWord'); + Item.Values.Add('clZWord'); + Item.Values.Add('cgZWord'); + + Item.Values.Add('zword lZWord'); + Item.Values.Add('zword gZWord'); + Item.Values.Add('zword clZWord'); + Item.Values.Add('zword cgZWord'); + end else if AnsiSameText(sl_Operand, 'REG8') then begin diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index db789e98c8..71baedc394 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3403,8 +3403,22 @@ begin slHeader.Add('Program $$$OPCODE$$$;'); slHeader.Add('{$asmmode intel}'); + slHeader.Add('type'); + slHeader.Add(' rec = record'); + + slHeader.Add(' rByte: byte;'); + slHeader.Add(' rWord: word;'); + slHeader.Add(' rDWord: dword;'); + slHeader.Add(' rQWord: qword;'); + slHeader.Add(' rOWord: array[0..15] of byte;'); + slHeader.Add(' rYWord: array[0..31] of byte;'); + slHeader.Add(' rZWord: array[0..63] of byte;'); + + slHeader.Add(' end;'); + slHeader.Add('var'); + slHeader.Add(' gRec: rec;'); slHeader.Add(' gByte: byte;'); slHeader.Add(' gWord: word;'); slHeader.Add(' gDWord: dword;'); @@ -3413,18 +3427,67 @@ begin slHeader.Add(' gYWord: array[0..31] of byte;'); slHeader.Add(' gZWord: array[0..63] of byte;'); + slHeader.Add('const'); + slHeader.Add(' cgByte: byte = 0;'); + slHeader.Add(' cgWord: word = 0;'); + slHeader.Add(' cgDWord: dword = 0;'); + slHeader.Add(' cgQWord: qword = 0;'); + slHeader.Add(' cgOWord: array[0..15] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + + slHeader.Add(' cgYWord: array[0..31] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + + slHeader.Add(' cgZWord: array[0..63] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + +// slHeader.Add(' cgZWord: array[0..63] of byte;'); + slHeader.Add(' procedure dummyproc;'); slHeader.Add(' var'); + slHeader.Add(' lRec: rec;'); slHeader.Add(' lByte: byte;'); slHeader.Add(' lWord: word;'); slHeader.Add(' lDWord: dword;'); slHeader.Add(' lQWord: qword;'); slHeader.Add(' lOWord: array[0..15] of byte;'); slHeader.Add(' lYWord: array[0..31] of byte;'); + slHeader.Add(' lSingle: single;'); + + slHeader.Add(' lDouble: double;'); slHeader.Add(' lZWord: array[0..63] of byte;'); - slHeader.Add(' lSingle: single;'); - slHeader.Add(' lDouble: double;'); + slHeader.Add(' const'); + slHeader.Add(' clByte: byte = 0;'); + slHeader.Add(' clWord: word = 0;'); + slHeader.Add(' clDWord: dword = 0;'); + slHeader.Add(' clQWord: qword = 0;'); + slHeader.Add(' clOWord: array[0..15] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + + slHeader.Add(' clYWord: array[0..31] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + + slHeader.Add(' clZWord: array[0..63] of byte = ((0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0),' + + '(0),(0),(0),(0),(0),(0),(0),(0));'); + + slHeader.Add(' begin'); slHeader.Add(' asm'); From aeca33e80ad2db7c2c885c624b534c0b19aaef21 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 7 Dec 2020 04:39:36 +0000 Subject: [PATCH 015/116] working on internal assembler-reader x86 opsize local var git-svn-id: branches/tg74/avx512-0037785@47707 - --- compiler/x86/rax86.pas | 41 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index ea762d5ab2..c804120ffb 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1304,6 +1304,41 @@ begin Internalerror(2019081008); end; end; + OPR_LOCAL: + if not(ExistsBCST) then + begin + case MemRefInfo(opcode).MemRefSize of + msiMultipleMinSize8: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"8 bit memory operand"'); + end; + msiMultipleMinSize16: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"16 bit memory operand"'); + end; + msiMultipleMinSize32: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"32 bit memory operand"'); + end; + msiMultipleMinSize64: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"64 bit memory operand"'); + end; + msiMultipleMinSize128: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"128 bit memory operand"'); + end; + msiMultipleMinSize256: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"256 bit memory operand"'); + end; + msiMultipleMinSize512: + begin + Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"512 bit memory operand"'); + end; + else; + end; + end; OPR_CONSTANT: case MemRefInfo(opcode).ConstSize of csiMem8: begin @@ -2228,11 +2263,7 @@ begin else if getregtype(opr.reg)=R_ADDRESSREGISTER then begin - // 14102020 TG TODO CHECK - if (opr.reg >= NR_K0) and (opr.reg >= NR_K7) then - begin - s:=s+'k' + regnr; - end; + s:=s+'k' + regnr; end; end; From 7aa94f6191bb586ebf69cd93e13c3bebdf10001e Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 7 Dec 2020 04:45:24 +0000 Subject: [PATCH 016/116] bugfixing operandsize from 32-bit to (correct) 64-bit git-svn-id: branches/tg74/avx512-0037785@47708 - --- tests/utils/avx/avxopcodes.pas | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 71baedc394..4c05dd8786 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -116,41 +116,41 @@ begin FOpCodeList.Add('CMPEQSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPEQSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPEQSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPLTSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPLTSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPLTSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPNEQSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPNEQSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPNEQSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPNLESD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPNLESD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPNLESD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPNLTSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPNLTSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPNLTSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPORDSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPORDSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPORDSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('CMPUNORDSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('CMPUNORDSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('CMPUNORDSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('COMISD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('COMISD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('COMISD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('DIVSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('DIVSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('DIVSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('MAXSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('MAXSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('MAXSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('MINSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('MINSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('MINSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('MULSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('MULSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('MULSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('SQRTSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('SQRTSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('SQRTSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('SUBSD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('SUBSD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('SUBSD,1,1,0,XMMREG,MEM64,,,'); FOpCodeList.Add('UCOMISD,1,1,0,XMMREG,XMMREG,,,'); - FOpCodeList.Add('UCOMISD,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('UCOMISD,1,1,0,XMMREG,MEM64,,,'); From 8c98be824df6e28fad2a957e4908cf96be65d400 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 10 Dec 2020 04:43:24 +0000 Subject: [PATCH 017/116] cleanup bugfix internal assembler-reader x86 opsize local/global var git-svn-id: branches/tg74/avx512-0037785@47745 - --- compiler/x86/rax86.pas | 51 ++---------------------------------------- 1 file changed, 2 insertions(+), 49 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index c804120ffb..2683c45011 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -743,13 +743,6 @@ begin msiYMem64, msiZMem64: ; // ignore; gather/scatter opcodes haven a fixed element-size, not a fixed memory-size // the vector-register have indices with base of the memory-address in the memory-operand - // msiMultipleMinSize8: memrefsize := 8; - // msiMultipleMinSize16: memrefsize := 16; - // msiMultipleMinSize32: memrefsize := 32; - // msiMultipleMinSize64: memrefsize := 64; - //msiMultipleMinSize128: memrefsize := 128; - //msiMultipleMinSize256: memrefsize := 256; - //msiMultipleMinSize512: memrefsize := 512; msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, @@ -908,7 +901,8 @@ begin if (tx86operand(operands[i]).opsize = S_NO) then begin case operands[i].Opr.Typ of - OPR_REFERENCE: + OPR_REFERENCE, + OPR_LOCAL: begin if ExistsBCST then begin @@ -1304,41 +1298,6 @@ begin Internalerror(2019081008); end; end; - OPR_LOCAL: - if not(ExistsBCST) then - begin - case MemRefInfo(opcode).MemRefSize of - msiMultipleMinSize8: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"8 bit memory operand"'); - end; - msiMultipleMinSize16: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"16 bit memory operand"'); - end; - msiMultipleMinSize32: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"32 bit memory operand"'); - end; - msiMultipleMinSize64: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"64 bit memory operand"'); - end; - msiMultipleMinSize128: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"128 bit memory operand"'); - end; - msiMultipleMinSize256: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"256 bit memory operand"'); - end; - msiMultipleMinSize512: - begin - Message2(asmr_w_check_mem_operand_automap_multiple_size, GetString(false), '"512 bit memory operand"'); - end; - else; - end; - end; OPR_CONSTANT: case MemRefInfo(opcode).ConstSize of csiMem8: begin @@ -1550,12 +1509,6 @@ procedure Tx86Instruction.SetInstructionOpsize; if bBroadcastMemRef then begin - //case MemRefSizeBCST of - // msbBCST32: opsize := S_L; - // msbBCST64: opsize := S_Q; - // else opsize := S_NO; - //end; - opsize := S_NO; result := true; end From 324032941a3b4171b59c99a1663c2a6407dbeec0 Mon Sep 17 00:00:00 2001 From: tg74 Date: Sat, 12 Dec 2020 21:36:31 +0000 Subject: [PATCH 018/116] add new option to avxtestgenerator to list opcodes-memrefsize-state git-svn-id: branches/tg74/avx512-0037785@47764 - --- tests/utils/avx/asmtestgenerator.pas | 1049 +++++++++++++++++++++++++- tests/utils/avx/avxopcodes.pas | 8 + tests/utils/avx/avxtestgenerator.lpi | 13 +- tests/utils/avx/avxtestgenerator.pp | 7 +- tests/utils/avx/options.pas | 1 + 5 files changed, 1071 insertions(+), 7 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index a91d5ed112..76f1088adf 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -97,19 +97,75 @@ type class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); class procedure CalcTestInstFile; + class procedure ListMemRefState; property x64: boolean read Fx64; end; implementation -uses SysUtils, Dialogs; +uses SysUtils, Dialogs, typinfo; + +type + TAsmOp={$i ../../../compiler/x86_64/x8664op.inc} + + TMemRefSizeInfo = (msiUnknown, msiUnsupported, msiNoSize, msiNoMemRef, + msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, + msiMultipleMinSize64, msiMultipleMinSize128, msiMultipleminSize256, msiMultipleMinSize512, + msiMemRegSize, msiMemRegx16y32, msiMemRegx16y32z64, msiMemRegx32y64, msiMemRegx32y64z128, msiMemRegx64y128, msiMemRegx64y128z256, + msiMemRegx64y256, msiMemRegx64y256z512, + msiMem8, msiMem16, msiMem32, msiBMem32, msiMem64, msiBMem64, msiMem128, msiMem256, msiMem512, + msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64, + msiVMemMultiple, msiVMemRegSize, + msiMemRegConst128,msiMemRegConst256,msiMemRegConst512); + + TMemRefSizeInfoBCST = (msbUnknown, msbBCST32, msbBCST64, msbMultiple); + TMemRefSizeInfoBCSTType = (btUnknown, bt1to2, bt1to4, bt1to8, bt1to16); + + TEVEXTupleState = (etsUnknown, etsIsTuple, etsNotTuple); + TConstSizeInfo = (csiUnknown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64); + + + TInsTabMemRefSizeInfoRec = record + MemRefSize : TMemRefSizeInfo; + MemRefSizeBCST : TMemRefSizeInfoBCST; + BCSTXMMMultiplicator : byte; + ExistsSSEAVX : boolean; + ConstSize : TConstSizeInfo; + BCSTTypes : Set of TMemRefSizeInfoBCSTType; + RegXMMSizeMask : int64; + RegYMMSizeMask : int64; + RegZMMSizeMask : int64; + end; + + + TInsTabMemRefSizeInfoCache=array[TasmOp] of TInsTabMemRefSizeInfoRec; + PInsTabMemRefSizeInfoCache=^TInsTabMemRefSizeInfoCache; + + TInsTabCache=array[TasmOp] of longint; + PInsTabCache=^TInsTabCache; + const instabentries = {$i ../../../compiler/x86_64/x8664nop.inc} + MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultipleMinSize8, + msiMultipleMinSize16, msiMultipleMinSize32, + msiMultipleMinSize64, msiMultipleMinSize128, + msiMultipleMinSize256, msiMultipleMinSize512, + msiVMemMultiple]; + + MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64, + msiZMem32, msiZMem64, + msiVMemMultiple, msiVMemRegSize]; + + +var + InsTabCache : PInsTabCache; + InsTabMemRefSizeInfoCache: PInsTabMemRefSizeInfoCache; + type - TAsmOp={$i ../../../compiler/x86_64/x8664op.inc} + op2strtable=array[tasmop] of string[16]; @@ -467,6 +523,629 @@ const InsTab:array[0..instabentries-1] of TInsEntry={$i ../../../compiler/x86_64/x8664tab.inc} + procedure BuildInsTabCache; + var + i : longint; + begin + new(instabcache); + FillChar(instabcache^,sizeof(tinstabcache),$ff); + i:=0; + while (i= 0 then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 0; + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := false; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := []; + + insentry:=@instab[i]; + RegMMXSizeMask := 0; + RegXMMSizeMask := 0; + RegYMMSizeMask := 0; + RegZMMSizeMask := 0; + + RegMMXConstSizeMask := 0; + RegXMMConstSizeMask := 0; + RegYMMConstSizeMask := 0; + RegZMMConstSizeMask := 0; + + RegBCSTSizeMask:= 0; + RegBCSTXMMSizeMask := 0; + RegBCSTYMMSizeMask := 0; + RegBCSTZMMSizeMask := 0; + ExistsMemRef := false; + + while (insentry^.opcode=AsmOp) do + begin + MRefInfo := msiUnknown; + + actRegSize := 0; + actRegCount := 0; + actRegTypes := 0; + NewRegSize := 0; + + actMemSize := 0; + actMemCount := 0; + actRegMemTypes := 0; + + actVMemCount := 0; + actVMemTypes := 0; + + actConstSize := 0; + actConstCount := 0; + + ExistsCode336 := false; // indicate fixed operand size 32 bit + ExistsCode337 := false; // indicate fixed operand size 64 bit + ExistsSSEAVXReg := false; + + // parse insentry^.code for &336 and &337 + // &336 (octal) = 222 (decimal) == fixed operand size 32 bit + // &337 (octal) = 223 (decimal) == fixed operand size 64 bit + for i := low(insentry^.code) to high(insentry^.code) do + begin + case insentry^.code[i] of + #222: ExistsCode336 := true; + #223: ExistsCode337 := true; + #0,#1,#2,#3: break; + end; + end; + + for i := 0 to insentry^.ops -1 do + begin + if (insentry^.optypes[i] and OT_REGISTER) = OT_REGISTER then + case insentry^.optypes[i] and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of + OT_XMMREG, + OT_YMMREG, + OT_ZMMREG: ExistsSSEAVXReg := true; + else; + end; + end; + + + for j := 0 to insentry^.ops -1 do + begin + if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR + ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR + ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR + ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) OR + ((insentry^.optypes[j] and OT_ZMEM32) = OT_ZMEM32) OR + ((insentry^.optypes[j] and OT_ZMEM64) = OT_ZMEM64) then + begin + inc(actVMemCount); + + case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64 OR OT_ZMEM32 OR OT_ZMEM64) of + OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32; + OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64; + OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32; + OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64; + OT_ZMEM32: actVMemTypes := actVMemTypes or OT_ZMEM32; + OT_ZMEM64: actVMemTypes := actVMemTypes or OT_ZMEM64; + else; + end; + end + else if (insentry^.optypes[j] and OT_REGISTER) = OT_REGISTER then + begin + inc(actRegCount); + + NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK); + if NewRegSize = 0 then + begin + case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of + OT_MMXREG: begin + NewRegSize := OT_BITS64; + end; + OT_XMMREG: begin + NewRegSize := OT_BITS128; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_YMMREG: begin + NewRegSize := OT_BITS256; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_ZMMREG: begin + NewRegSize := OT_BITS512; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_KREG: begin + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + + else NewRegSize := not(0); + end; + end; + + actRegSize := actRegSize or NewRegSize; + actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK)); + end + else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then + begin + inc(actMemCount); + + + if ExistsSSEAVXReg and ExistsCode336 then + actMemSize := actMemSize or OT_BITS32 + else if ExistsSSEAVXReg and ExistsCode337 then + actMemSize := actMemSize or OT_BITS64 + else + actMemSize:=actMemSize or (insentry^.optypes[j] and (OT_SIZE_MASK OR OT_VECTORBCST)); + + if (insentry^.optypes[j] and OT_REGMEM) = OT_REGMEM then + begin + actRegMemTypes := actRegMemTypes or insentry^.optypes[j]; + end; + end + else if ((insentry^.optypes[j] and OT_IMMEDIATE) = OT_IMMEDIATE) then + begin + inc(actConstCount); + + actConstSize := actConstSize or (insentry^.optypes[j] and OT_SIZE_MASK); + end + end; + + if actConstCount > 0 then + begin + case actConstSize of + 0: SConstInfo := csiNoSize; + OT_BITS8: SConstInfo := csiMem8; + OT_BITS16: SConstInfo := csiMem16; + OT_BITS32: SConstInfo := csiMem32; + OT_BITS64: SConstInfo := csiMem64; + else SConstInfo := csiMultiple; + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize = csiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := SConstInfo; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize <> SConstInfo then + begin + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiMultiple; + end; + end; + + if actVMemCount > 0 then + begin + if actVMemCount = 1 then + begin + if actVMemTypes > 0 then + begin + case actVMemTypes of + OT_XMEM32: MRefInfo := msiXMem32; + OT_XMEM64: MRefInfo := msiXMem64; + OT_YMEM32: MRefInfo := msiYMem32; + OT_YMEM64: MRefInfo := msiYMem64; + OT_ZMEM32: MRefInfo := msiZMem32; + OT_ZMEM64: MRefInfo := msiZMem64; + else; + end; + + case actRegTypes of + OT_XMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS512; + else; + end; + OT_YMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS512; + else; + end; + OT_ZMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS512; + else; + end; + + //else InternalError(777209); + end; + + + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64] then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> msiVMemMultiple then; + end; + + end; + end + else; + end + else + begin + if (actMemCount=2) and ((AsmOp=A_MOVS) or (AsmOp=A_CMPS)) then actMemCount:=1; + + ExistsMemRef := ExistsMemRef or (actMemCount > 0); + + case actMemCount of + 0: ; // nothing todo + 1: begin + MRefInfo := msiUnknown; + + if not(ExistsCode336 or ExistsCode337) then + case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of + OT_MMXRM: actMemSize := actMemSize or OT_BITS64; + OT_XMMRM: actMemSize := actMemSize or OT_BITS128; + OT_YMMRM: actMemSize := actMemSize or OT_BITS256; + OT_ZMMRM: actMemSize := actMemSize or OT_BITS512; + end; + + case actMemSize of + 0: MRefInfo := msiNoSize; + OT_BITS8: MRefInfo := msiMem8; + OT_BITS16: MRefInfo := msiMem16; + OT_BITS32: MRefInfo := msiMem32; + OT_BITSB32: MRefInfo := msiBMem32; + OT_BITS64: MRefInfo := msiMem64; + OT_BITSB64: MRefInfo := msiBMem64; + OT_BITS128: MRefInfo := msiMem128; + OT_BITS256: MRefInfo := msiMem256; + OT_BITS512: MRefInfo := msiMem512; + OT_BITS80, + OT_FAR, + OT_NEAR, + OT_SHORT: ; // ignore + else + begin + bitcount := bitcnt(actMemSize); + + if bitcount > 1 then MRefInfo := msiMultiple + else; + end; + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; + end + else + begin + // ignore broadcast-memory + if not(MRefInfo in [msiBMem32, msiBMem64]) then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then + begin + with InsTabMemRefSizeInfoCache^[AsmOp] do + begin + if ((MemRefSize in [msiMem8, msiMULTIPLEMinSize8]) OR (MRefInfo = msiMem8)) then MemRefSize := msiMultipleMinSize8 + else if ((MemRefSize in [ msiMem16, msiMULTIPLEMinSize16]) OR (MRefInfo = msiMem16)) then MemRefSize := msiMultipleMinSize16 + else if ((MemRefSize in [ msiMem32, msiMULTIPLEMinSize32]) OR (MRefInfo = msiMem32)) then MemRefSize := msiMultipleMinSize32 + else if ((MemRefSize in [ msiMem64, msiMULTIPLEMinSize64]) OR (MRefInfo = msiMem64)) then MemRefSize := msiMultipleMinSize64 + else if ((MemRefSize in [msiMem128, msiMULTIPLEMinSize128]) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultipleMinSize128 + else if ((MemRefSize in [msiMem256, msiMULTIPLEMinSize256]) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultipleMinSize256 + else if ((MemRefSize in [msiMem512, msiMULTIPLEMinSize512]) OR (MRefInfo = msiMem512)) then MemRefSize := msiMultipleMinSize512 + else MemRefSize := msiMultiple; + end; + end; + end; + end; + + //if not(MRefInfo in [msiBMem32, msiBMem64]) and (actRegCount > 0) then + if actRegCount > 0 then + begin + if MRefInfo in [msiBMem32, msiBMem64] then + begin + if IF_BCST2 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to2]; + if IF_BCST4 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to4]; + if IF_BCST8 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to8]; + if IF_BCST16 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to16]; + + //InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + + // BROADCAST - OPERAND + RegBCSTSizeMask := RegBCSTSizeMask or actMemSize; + + case actRegTypes and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of + OT_XMMREG: RegBCSTXMMSizeMask := RegBCSTXMMSizeMask or actMemSize; + OT_YMMREG: RegBCSTYMMSizeMask := RegBCSTYMMSizeMask or actMemSize; + OT_ZMMREG: RegBCSTZMMSizeMask := RegBCSTZMMSizeMask or actMemSize; + else begin + + RegBCSTXMMSizeMask := not(0); + RegBCSTYMMSizeMask := not(0); + RegBCSTZMMSizeMask := not(0); + end; + end; + end + else + case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of + OT_MMXREG: if actConstCount > 0 then RegMMXConstSizeMask := RegMMXConstSizeMask or actMemSize + else RegMMXSizeMask := RegMMXSizeMask or actMemSize; + OT_XMMREG: if actConstCount > 0 then RegXMMConstSizeMask := RegXMMConstSizeMask or actMemSize + else RegXMMSizeMask := RegXMMSizeMask or actMemSize; + OT_YMMREG: if actConstCount > 0 then RegYMMConstSizeMask := RegYMMConstSizeMask or actMemSize + else RegYMMSizeMask := RegYMMSizeMask or actMemSize; + OT_ZMMREG: if actConstCount > 0 then RegZMMConstSizeMask := RegZMMConstSizeMask or actMemSize + else RegZMMSizeMask := RegZMMSizeMask or actMemSize; + else begin + RegMMXSizeMask := not(0); + RegXMMSizeMask := not(0); + RegYMMSizeMask := not(0); + RegZMMSizeMask := not(0); + + RegMMXConstSizeMask := not(0); + RegXMMConstSizeMask := not(0); + RegYMMConstSizeMask := not(0); + RegZMMConstSizeMask := not(0); + end; + end; + end + else + + + end + else; + end; + end; + + inc(insentry); + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX then + begin + case RegBCSTSizeMask of + 0: ; // ignore; + OT_BITSB32: begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST32; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 4; + end; + OT_BITSB64: begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST64; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 2; + end; + else begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbMultiple; + end; + end; + end; + + + if (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples) and + (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX)then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiVMemMultiple then + begin + if ((RegXMMSizeMask = OT_BITS128) or (RegXMMSizeMask = 0)) and + ((RegYMMSizeMask = OT_BITS256) or (RegYMMSizeMask = 0)) and + ((RegZMMSizeMask = OT_BITS512) or (RegZMMSizeMask = 0)) and + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) <> 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemRegSize; + end; + end + else if (RegMMXSizeMask or RegMMXConstSizeMask) <> 0 then + begin + if ((RegMMXSizeMask or RegMMXConstSizeMask) = OT_BITS64) and + ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = 0) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; + end; + end + else if (((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) or ((RegXMMSizeMask or RegXMMConstSizeMask) = 0)) and + (((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) or ((RegYMMSizeMask or RegYMMConstSizeMask) = 0)) and + (((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) or ((RegZMMSizeMask or RegZMMConstSizeMask) = 0)) and + (((RegXMMSizeMask or RegXMMConstSizeMask or + RegYMMSizeMask or RegYMMConstSizeMask or + RegZMMSizeMask or RegZMMConstSizeMask)) <> 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; + end + else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and + (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and + (RegZMMSizeMask or RegZMMConstSizeMask = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32; + end + else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and + (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and + (RegZMMSizeMask or RegZMMConstSizeMask = OT_BITS64) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32z64; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS32) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS64) then + begin + if ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64; + end + else if ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS128) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64z128; + end; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS256) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128z256; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256z512; + end + else if ((RegXMMConstSizeMask = 0) or (RegXMMConstSizeMask = OT_BITS128)) and + ((RegYMMConstSizeMask = 0) or (RegYMMConstSizeMask = OT_BITS256)) and + ((RegZMMConstSizeMask = 0) or (RegZMMConstSizeMask = OT_BITS512)) and + ((RegXMMConstSizeMask or RegYMMConstSizeMask or RegZMMConstSizeMask) <> 0) and + ( + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS128) or + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS256) or + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS512) + ) then + begin + case RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask of + OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst128; + OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst256; + OT_BITS512: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst512; + else InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMultiple; + end; + end + else + begin + if not( + (AsmOp = A_CVTSI2SS) or + (AsmOp = A_CVTSI2SD) or + (AsmOp = A_CVTPD2DQ) or + (AsmOp = A_VCVTPD2DQ) or + (AsmOp = A_VCVTPD2PS) or + (AsmOp = A_VCVTSI2SD) or + (AsmOp = A_VCVTSI2SS) or + (AsmOp = A_VCVTTPD2DQ) or + (AsmOp = A_VCVTPD2UDQ) or + (AsmOp = A_VCVTQQ2PS) or + (AsmOp = A_VCVTTPD2UDQ) or + (AsmOp = A_VCVTUQQ2PS) or + (AsmOp = A_VCVTUSI2SD) or + (AsmOp = A_VCVTUSI2SS) or + + + // TODO check + (AsmOp = A_VCMPSS) + + + ) then; + + end; + + end + else if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and + (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown) and + (not(ExistsMemRef)) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiNoMemRef; + end; + + InsTabMemRefSizeInfoCache^[AsmOp].RegXMMSizeMask:=RegXMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask; + + end; + end; + + for AsmOp := low(TAsmOp) to high(TAsmOp) do + begin + + + // only supported intructiones with SSE- or AVX-operands + if not(InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; + end; + end; + end; + { TOperandListItem } constructor TOperandListItem.Create; @@ -2001,6 +2680,32 @@ begin Item.Values.Add(' lRec'); Item.Values.Add(' gRec'); + Item.Values.Add(' oword lRec'); + Item.Values.Add(' oword gRec'); + + Item.Values.Add(' oword lRec.rOWord'); + Item.Values.Add(' oword gRec.rOWord'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); end else if (AnsiSameText(sl_Operand, 'XMMRM8')) or @@ -2025,6 +2730,35 @@ begin Item.Values.Add('byte clbyte'); Item.Values.Add('byte cgbyte'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' byte lRec'); + Item.Values.Add(' byte gRec'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); end else if (AnsiSameText(sl_Operand, 'XMMRM16')) or @@ -2048,6 +2782,33 @@ begin Item.Values.Add('word clword'); Item.Values.Add('word cgword'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' word lRec'); + Item.Values.Add(' word gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'YMMREG')) or (AnsiSameText(sl_Operand, 'YMMREG_M')) or @@ -2083,6 +2844,33 @@ begin Item.Values.Add('yword clYWord'); Item.Values.Add('yword cgYWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' yword lRec'); + Item.Values.Add(' yword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'ZMMREG')) or (AnsiSameText(sl_Operand, 'ZMMREG_M')) or @@ -2118,6 +2906,33 @@ begin Item.Values.Add('zword clZWord'); Item.Values.Add('zword cgZWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' zword lRec'); + Item.Values.Add(' zword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if AnsiSameText(sl_Operand, 'MEM8') then begin @@ -2135,6 +2950,32 @@ begin Item.Values.Add('byte clByte'); Item.Values.Add('byte cgByte'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' byte lRec'); + Item.Values.Add(' byte gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); end else if AnsiSameText(sl_Operand, 'MEM16') or AnsiSameText(sl_Operand, 'MEM16_M') then @@ -2153,6 +2994,33 @@ begin Item.Values.Add('word clWord'); Item.Values.Add('word cgWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' word lRec'); + Item.Values.Add(' word gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if AnsiSameText(sl_Operand, 'MEM32') or AnsiSameText(sl_Operand, 'MEM32_M') or @@ -2172,6 +3040,33 @@ begin Item.Values.Add('dword clDWord'); Item.Values.Add('dword cgDWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' dword lRec'); + Item.Values.Add(' dword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'MEM64')) or (AnsiSameText(sl_Operand, 'MEM64_M')) or @@ -2191,6 +3086,33 @@ begin Item.Values.Add('qword clQWord'); Item.Values.Add('qword cgQWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' qword lRec'); + Item.Values.Add(' qword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'MEM128')) or (AnsiSameText(sl_Operand, 'MEM128_M')) or @@ -2210,6 +3132,33 @@ begin Item.Values.Add('oword clOWord'); Item.Values.Add('oword cgOWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' oword lRec'); + Item.Values.Add(' oword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'MEM256')) or (AnsiSameText(sl_Operand, 'MEM256_M')) or @@ -2229,6 +3178,33 @@ begin Item.Values.Add('yword clYWord'); Item.Values.Add('yword cgYWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' yword lRec'); + Item.Values.Add(' yword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + end else if (AnsiSameText(sl_Operand, 'MEM512')) or (AnsiSameText(sl_Operand, 'MEM512_M')) or @@ -2248,6 +3224,13 @@ begin Item.Values.Add('zword clZWord'); Item.Values.Add('zword cgZWord'); + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' zword lRec'); + Item.Values.Add(' zword gRec'); + + end else if AnsiSameText(sl_Operand, 'REG8') then begin @@ -3131,4 +4114,66 @@ begin end; end; +class procedure TAsmTestGenerator.ListMemRefState; +var + i: integer; + mrsize: TMemRefSizeInfo; + opcode: tasmop; + sl: TStringList; + slEmpty: TStringList; +begin + BuildInsTabCache; + BuildInsTabMemRefSizeInfoCache; + + slEmpty := TStringList.Create; + try + for mrsize := low(TMemRefSizeInfo) to high(TMemRefSizeInfo) do + begin + + sl := TStringList.Create; + try + for opcode:=low(tasmop) to high(tasmop) do + begin + if InsTabMemRefSizeInfoCache^[opcode].MemRefSize = mrsize then + sl.add(format('%-25s: %s', [GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize)), std_op2str[opcode]])); + end; + + sl.Sort; + + if sl.Count > 0 then + begin + writeln; + + writeln(sl.text); + end + else slEmpty.Add(GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize))); + + + finally + FreeAndNil(sl); + end; + end; + + slEmpty.Sort; + writeln(''); + writeln(slEmpty.Text); + finally + FreeAndNil(slEmpty); + end; + + if assigned(instabcache) then + begin + dispose(instabcache); + instabcache:=nil; + end; + + if assigned(InsTabMemRefSizeInfoCache) then + begin + dispose(InsTabMemRefSizeInfoCache); + InsTabMemRefSizeInfoCache:=nil; + end; + + +end; + end. diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 4c05dd8786..00760c284e 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -10,6 +10,8 @@ type TTestFileTyp = (tfNasm, tfFPC, tfFasm, tfFPCInc, tfFPCMRef); + { TAVXTestGenerator } + TAVXTestGenerator = class(TObject) private FOpCodeList: TStringList; @@ -23,6 +25,7 @@ type destructor Destroy; override; function MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; + procedure ListMemRefState; // function MakeTestFilesMREF(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; property OpCodeList: TStringList read FOpCodeList write FOpCodeList; @@ -3588,5 +3591,10 @@ begin end; end; +procedure TAVXTestGenerator.ListMemRefState; +begin + TAsmTestGenerator.ListMemRefState; +end; + end. diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index 6bf45626ec..89266c4b32 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -1,7 +1,7 @@ - + @@ -22,9 +22,16 @@ - - + + + + + + + + + diff --git a/tests/utils/avx/avxtestgenerator.pp b/tests/utils/avx/avxtestgenerator.pp index 4c1b43f435..6f2f33ea6a 100644 --- a/tests/utils/avx/avxtestgenerator.pp +++ b/tests/utils/avx/avxtestgenerator.pp @@ -42,10 +42,12 @@ begin writeln('make avx assembler-testfiles'); writeln(''); writeln('-h help'); - writeln('-f [fpc,nasm,fasm,fpcinc] outputformat'); - writeln('-p [x8664] codegenerator for x86_64 platform'); + writeln('-f [fpc,fpcmref,nasm,fasm,fpcinc] outputformat'); + writeln('-l list opcode-memrefsize-states'); writeln('-o destination path'); + writeln('-p [x8664] codegenerator for x86_64 platform'); writeln('-z avx512'); + writeln(''); end else @@ -59,6 +61,7 @@ begin 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path); 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path); 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path); + 'l': ListMemRefState; end; end; finally diff --git a/tests/utils/avx/options.pas b/tests/utils/avx/options.pas index 89c8771cbd..28eab2500a 100644 --- a/tests/utils/avx/options.pas +++ b/tests/utils/avx/options.pas @@ -101,6 +101,7 @@ begin Fx64 := true; end else IsInvalidParam := true; + 'l': FOutputFormat := 'l'; 'z': FAVX512 := true; 'o': if sValue <> '' then begin From d6fdb384590bf8306e16b990dac52ca86f90deab Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 16 Dec 2020 11:02:14 +0000 Subject: [PATCH 019/116] cleanup and add comments to div. vcvt.. opcodes git-svn-id: branches/tg74/avx512-0037785@47785 - --- compiler/x86/x86ins.dat | 27 +++++++-------------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index bc5c8d8572..c3cca348d9 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -4180,15 +4180,11 @@ zmmreg_mz,zmmreg_er \350\351\370\1\x5B\110 (Ch_Wop2, Ch_Rop1) xmmreg_mz,mem256 \334\350\352\362\364\370\1\xE6\110 AVX,SANDYBRIDGE,TFV xmmreg_mz,xmmrm \334\350\352\362\370\1\xE6\110 AVX,SANDYBRIDGE,TFV -xmmreg_mz,ymmreg \334\350\352\362\364\370\1\xE6\110 AVX,SANDYBRIDGE +xmmreg_mz,ymmreg \334\350\352\362\364\370\1\xE6\110 AVX,SANDYBRIDGE xmmreg_mz,bmem64 \334\350\352\370\1\xE6\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \334\350\352\364\370\1\xE6\110 AVX512,BCST4,TFV - -;ymmreg_mz,mem512 \334\350\351\352\370\1\xE6\110 AVX512,TFV ymmreg_mz,zmmrm_er \334\350\351\352\370\1\xE6\110 AVX512,TFV ymmreg_mz,bmem64 \334\350\351\352\370\1\xE6\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_er \334\350\351\352\370\1\xE6\110 AVX512 -ymmreg_mz,zmmrm \334\350\351\352\370\1\xE6\110 AVX512,TFV ; VCVTPD2PS xmmreg_mz,mem256 must come first - map MemRefSize 256bits correct @@ -4200,10 +4196,8 @@ xmmreg_mz,ymmreg \350\352\361\362\364\370\1\x5A\110 xmmreg_mz,xmmrm \350\352\361\362\370\1\x5A\110 AVX,SANDYBRIDGE,TFV xmmreg_mz,bmem64 \350\352\361\370\1\x5A\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\361\364\370\1\x5A\110 AVX512,BCST4,TFV -;ymmreg_mz,mem512 \350\351\352\361\370\1\x5A\110 AVX512,TFV ymmreg_mz,zmmrm_er \350\351\352\361\370\1\x5A\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\361\370\1\x5A\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_er \350\351\352\361\370\1\x5A\110 AVX512 [VCVTPH2PS] (Ch_Wop2, Ch_Rop1) @@ -4307,10 +4301,8 @@ xmmreg_mz,ymmreg \350\352\361\362\364\370\1\xE6\110 xmmreg_mz,xmmrm \350\352\361\362\370\1\xE6\110 AVX,SANDYBRIDGE,AVX512,TFV xmmreg_mz,bmem64 \350\352\361\370\1\xE6\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\361\364\370\1\xE6\110 AVX512,BCST4,TFV -;ymmreg_mz,mem512 \350\351\352\361\370\1\xE6\110 AVX512,TFV -ymmreg_mz,zmmrm_sae \350\351\352\361\370\1\xE6\110 AVX512,TFV +ymmreg_mz,zmmrm_sae \350\351\352\361\370\1\xE6\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\361\370\1\xE6\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_sae \350\351\352\361\370\1\xE6\110 AVX512 [VCVTTPS2DQ] (Ch_Wop2, Ch_Rop1) @@ -7307,6 +7299,9 @@ zmmreg_mz,mem512 \350\351\352\361\370\1\x7B\110 zmmreg_mz,bmem64 \350\351\352\361\370\1\x7B\110 AVX512,TFV zmmreg_mz,zmmreg_er \350\351\352\361\370\1\x7B\110 AVX512 + +; VCVTPD2UDQ xmmreg_mz,mem256 must come first - map MemRefSize 256,512bits correct +; map all other MemrefSize (without broasdcast MemRef) to xmmreg, xmmrm [VCVTPD2UDQ, vcvtpd2udqN] (Ch_All) xmmreg_mz,mem256 \350\352\364\370\1\x79\110 AVX512,TFV @@ -7314,7 +7309,6 @@ xmmreg_mz,xmmrm \350\352\370\1\x79\110 xmmreg_mz,bmem64 \350\352\370\1\x79\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x79\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x79\110 AVX512 -;ymmreg_mz,mem512 \350\351\352\370\1\x79\110 AVX512,TFV ymmreg_mz,zmmrm_er \350\351\352\370\1\x79\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x79\110 AVX512,BCST8,TFV @@ -7372,20 +7366,15 @@ zmmreg_mz,zmmreg_er \333\350\351\352\370\1\xE6\110 ; VCVTQQ2PS xmmreg_mz,mem256 must come first - map MemRefSize 256,512bits correct ; map all other MemrefSize (without broasdcast MemRef) to xmmreg, xmmrm -; [VCVTQQ2PS,vcvtqq2psN] (Ch_All) -;xmmreg_mz,mem128 \350\352\370\1\x5B\110 AVX512,TFV xmmreg_mz,mem256 \350\352\364\370\1\x5B\110 AVX512,TFV -;xmmreg_mz,xmmreg \350\352\370\1\x5B\110 AVX512 xmmreg_mz,xmmrm \350\352\370\1\x5B\110 AVX512 xmmreg_mz,bmem64 \350\352\370\1\x5B\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x5B\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x5B\110 AVX512 -;ymmreg_mz,mem512 \350\351\352\370\1\x5B\110 AVX512,TFV ymmreg_mz,zmmrm_er \350\351\352\370\1\x5B\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x5B\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_er \350\351\352\370\1\x5B\110 AVX512 [VCVTSD2USI] (Ch_All) @@ -7416,17 +7405,13 @@ zmmreg_mz,zmmreg_sae \350\351\352\361\370\1\x7A\110 ; map all other MemrefSize (without broasdcast MemRef) to kreg_m, xmmrm [VCVTTPD2UDQ,vcvttpd2udqN] (Ch_All) -;xmmreg_mz,mem128 \350\352\370\1\x78\110 AVX512,TFV xmmreg_mz,mem256 \350\352\364\370\1\x78\110 AVX512,TFV -;xmmreg_mz,xmmreg \350\352\370\1\x78\110 AVX512 xmmreg_mz,xmmrm \350\352\370\1\x78\110 AVX512 xmmreg_mz,bmem64 \350\352\370\1\x78\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x78\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x78\110 AVX512 -;ymmreg_mz,mem512 \350\351\352\370\1\x78\110 AVX512,TFV ymmreg_mz,zmmrm_sae \350\351\352\370\1\x78\110 AVX512,TFV ymmreg_mz,bmem64 \350\351\352\370\1\x78\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_sae \350\351\352\370\1\x78\110 AVX512 [VCVTTPD2UQQ] (Ch_All) @@ -7515,6 +7500,8 @@ zmmreg_mz,mem512 \333\350\351\352\370\1\x7A\110 zmmreg_mz,bmem64 \333\350\351\352\370\1\x7A\110 AVX512,TFV zmmreg_mz,zmmreg_er \333\350\351\352\370\1\x7A\110 AVX512 +; VCVTTUQQ2PSQ xmmreg_mz,mem256 must come first - map MemRefSize 256,512bits correct +; map all other MemrefSize (without broasdcast MemRef) to kreg_m, xmmrm [VCVTUQQ2PS,vcvtuqq2psN] (Ch_All) xmmreg_mz,mem256 \334\350\352\364\370\1\x7A\110 AVX512,TFV From 04b059268bb291cb1b5471481bacf5aa93a756eb Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 16 Dec 2020 15:39:19 +0000 Subject: [PATCH 020/116] cleanup x86ins.dat git-svn-id: branches/tg74/avx512-0037785@47788 - --- compiler/x86/x86ins.dat | 6 ------ 1 file changed, 6 deletions(-) diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index c3cca348d9..56c9989a1a 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -4260,10 +4260,6 @@ xmmreg_mz,xmmreg,xmmreg_er \334\350\352\362\370\1\x5A\75\120 ; special handling - gas suffix "S" =>> instructions-opsize = source-operand [VCVTSI2SD,vcvtsi2sdS] (Ch_Wop3, Ch_Rop2, Ch_Rop1) -;xmmreg,xmmreg,reg32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD -;xmmreg,xmmreg,mem32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,SD,T1S -;xmmreg,xmmreg_er,reg64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64 -;xmmreg,xmmreg_er,mem64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64,T1S xmmreg,xmmreg_er,reg32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE xmmreg,xmmreg_er,reg64 \334\350\352\362\363\370\1\x2A\75\120 AVX,SANDYBRIDGE,X86_64 xmmreg,xmmreg_er,mem32 \334\350\362\370\1\x2A\75\120 AVX,SANDYBRIDGE,T1S @@ -7509,10 +7505,8 @@ xmmreg_mz,xmmrm \334\350\352\370\1\x7A\110 xmmreg_mz,bmem64 \334\350\352\370\1\x7A\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \334\350\352\364\370\1\x7A\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \334\350\352\364\370\1\x7A\110 AVX512 -;ymmreg_mz,mem512 \334\350\351\352\370\1\x7A\110 AVX512,TFV ymmreg_mz,zmmrm_er \334\350\351\352\370\1\x7A\110 AVX512,TFV ymmreg_mz,bmem64 \334\350\351\352\370\1\x7A\110 AVX512,BCST8,TFV -;ymmreg_mz,zmmreg_er \334\350\351\352\370\1\x7A\110 AVX512 ; special handling - gas suffix "S" =>> instructions-opsize = source-operand From 25b27281375284e07b7b9047d7cfcb14f2805555 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 16 Dec 2020 15:43:34 +0000 Subject: [PATCH 021/116] cleanup x86ins.dat git-svn-id: branches/tg74/avx512-0037785@47789 - --- compiler/i386/i386nop.inc | 2 +- compiler/i386/i386tab.inc | 7 ------- compiler/i8086/i8086nop.inc | 2 +- compiler/i8086/i8086tab.inc | 7 ------- compiler/x86_64/x8664nop.inc | 2 +- compiler/x86_64/x8664tab.inc | 7 ------- 6 files changed, 3 insertions(+), 24 deletions(-) diff --git a/compiler/i386/i386nop.inc b/compiler/i386/i386nop.inc index dae95022af..ed3109117c 100644 --- a/compiler/i386/i386nop.inc +++ b/compiler/i386/i386nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4158; +4157; diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc index f1e13131c8..d95f7c30d4 100644 --- a/compiler/i386/i386tab.inc +++ b/compiler/i386/i386tab.inc @@ -10542,13 +10542,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2PS; ops : 2; diff --git a/compiler/i8086/i8086nop.inc b/compiler/i8086/i8086nop.inc index 596abe4e2e..fceef2d44d 100644 --- a/compiler/i8086/i8086nop.inc +++ b/compiler/i8086/i8086nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4190; +4189; diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc index 2f5f2b0c63..b00d14af39 100644 --- a/compiler/i8086/i8086tab.inc +++ b/compiler/i8086/i8086tab.inc @@ -10570,13 +10570,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2PS; ops : 2; diff --git a/compiler/x86_64/x8664nop.inc b/compiler/x86_64/x8664nop.inc index 4b57c937c2..0ec8174663 100644 --- a/compiler/x86_64/x8664nop.inc +++ b/compiler/x86_64/x8664nop.inc @@ -1,2 +1,2 @@ { don't edit, this file is generated from x86ins.dat } -4222; +4221; diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc index df80ca4a14..d30c2a81e3 100644 --- a/compiler/x86_64/x8664tab.inc +++ b/compiler/x86_64/x8664tab.inc @@ -10843,13 +10843,6 @@ code : #220#232#233#234#248#1#230#72; flags : [if_avx512,if_bcst8,if_tfv] ), - ( - opcode : A_VCVTPD2DQ; - ops : 2; - optypes : (ot_ymmreg_mz,ot_zmmrm,ot_none,ot_none); - code : #220#232#233#234#248#1#230#72; - flags : [if_avx512,if_tfv] - ), ( opcode : A_VCVTPD2PS; ops : 2; From 76dd6ff6e784410972d33fdd3aa77d0252a46ea5 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 18 Dec 2020 05:27:56 +0000 Subject: [PATCH 022/116] working on new testmethods and bug-fixing size of (memref-operands | global and local variable git-svn-id: branches/tg74/avx512-0037785@47807 - --- tests/utils/avx/asmtestgenerator.pas | 87 +--------------------------- 1 file changed, 3 insertions(+), 84 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 76f1088adf..480e2538b6 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -607,6 +607,8 @@ const if i >= 0 then begin + + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbUnknown; InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 0; @@ -615,6 +617,7 @@ const InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := []; insentry:=@instab[i]; + RegMMXSizeMask := 0; RegXMMSizeMask := 0; RegYMMSizeMask := 0; @@ -2958,24 +2961,6 @@ begin Item.Values.Add(' lRec.rByte'); Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); end else if AnsiSameText(sl_Operand, 'MEM16') or AnsiSameText(sl_Operand, 'MEM16_M') then @@ -2994,33 +2979,11 @@ begin Item.Values.Add('word clWord'); Item.Values.Add('word cgWord'); - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - Item.Values.Add(' word lRec'); Item.Values.Add(' word gRec'); - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - Item.Values.Add(' lRec.rWord'); Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - end else if AnsiSameText(sl_Operand, 'MEM32') or AnsiSameText(sl_Operand, 'MEM32_M') or @@ -3040,33 +3003,11 @@ begin Item.Values.Add('dword clDWord'); Item.Values.Add('dword cgDWord'); - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - Item.Values.Add(' dword lRec'); Item.Values.Add(' dword gRec'); - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - Item.Values.Add(' lRec.rDWord'); Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - end else if (AnsiSameText(sl_Operand, 'MEM64')) or (AnsiSameText(sl_Operand, 'MEM64_M')) or @@ -3086,33 +3027,11 @@ begin Item.Values.Add('qword clQWord'); Item.Values.Add('qword cgQWord'); - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - Item.Values.Add(' qword lRec'); Item.Values.Add(' qword gRec'); - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - Item.Values.Add(' lRec.rQWord'); Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - end else if (AnsiSameText(sl_Operand, 'MEM128')) or (AnsiSameText(sl_Operand, 'MEM128_M')) or From 518db35eb075e4bbee9fd9f55324b96d292abe4b Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 18 Dec 2020 16:24:57 +0000 Subject: [PATCH 023/116] working on internal assembler-reader x86 opsize local/global var git-svn-id: branches/tg74/avx512-0037785@47811 - --- compiler/x86/rax86.pas | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 2683c45011..fadc1c774b 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1537,6 +1537,23 @@ procedure Tx86Instruction.SetInstructionOpsize; result := true; end; end; + + if result and (MemRefSize in [msiMultipleMinSize128, msiMultipleMinSize256, msiMultipleMinSize512]) then + begin + for i := 1 to ops do + if tx86operand(operands[i]).opr.typ in [OPR_REGISTER] then + begin + case tx86operand(operands[i]).opsize of + S_XMM: ; + S_YMM:; + S_ZMM:; + end; + //opsize := tx86operand(operands[i]).opsize; + //result := true; + + break; + end; + end; end else if not(MemRefSize in [msiMemRegSize]) then begin From 213f84ad6ce093b49829e9411b597b626fb113b8 Mon Sep 17 00:00:00 2001 From: tg74 Date: Sun, 20 Dec 2020 04:44:37 +0000 Subject: [PATCH 024/116] working on new testmethods and bug-fixing size of (memref-operands | global and local variable - append correct gas-suffix on any vcvt.. opcodes git-svn-id: branches/tg74/avx512-0037785@47821 - --- compiler/x86/rax86.pas | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index fadc1c774b..6c53779037 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1494,8 +1494,10 @@ procedure Tx86Instruction.SetInstructionOpsize; function CheckSSEAVX: Boolean; var i: integer; + iSizeMask: int64; bBroadcastMemRef: boolean; bExistMemRef: boolean; + ValidOpSizes: Set of topsize; begin Result := False; @@ -1538,18 +1540,43 @@ procedure Tx86Instruction.SetInstructionOpsize; end; end; - if result and (MemRefSize in [msiMultipleMinSize128, msiMultipleMinSize256, msiMultipleMinSize512]) then + if (result) and + (ops > 0) and + (MemRefSize in [msiMultipleMinSize128, msiMultipleMinSize256, msiMultipleMinSize512]) and + (gas_needsuffix[opcode] in [AttSufMMS, AttSufMMX]) then begin + // external gas assembler need suffix (different opsizes possible) + // - in fpc not exists datatypes for vector-variables + // =>> all memsize = ok, but any special opcodes (marked with attSufMMS,attSUFMMX) needed in any combination of operandtypes the exact opsize + // =>> check instructions-opsize and use the correct vector-mem-opsize + for i := 1 to ops do if tx86operand(operands[i]).opr.typ in [OPR_REGISTER] then begin + ValidOpSizes := []; + case tx86operand(operands[i]).opsize of - S_XMM: ; - S_YMM:; - S_ZMM:; + S_XMM: iSizeMask := RegXMMSizeMask; + S_YMM: iSizeMask := RegYMMSizeMask; + S_ZMM: iSizeMask := RegZMMSizeMask; + else iSizeMask := 0; end; - //opsize := tx86operand(operands[i]).opsize; - //result := true; + + if iSizemask and OT_BITS128 = OT_BITS128 then include(ValidOpSizes, S_XMM); + if iSizemask and OT_BITS256 = OT_BITS256 then include(ValidOpSizes, S_YMM); + if iSizemask and OT_BITS512 = OT_BITS512 then include(ValidOpSizes, S_ZMM); + + if (ValidOpsizes <> []) then + begin + if not(opsize in ValidOpSizes) then + begin + // instructions-opsize is invalid =>> use smallest valid opsize + if iSizemask and OT_BITS128 = OT_BITS128 then opsize := S_XMM + else if iSizemask and OT_BITS256 = OT_BITS256 then opsize := S_YMM + else if iSizemask and OT_BITS512 = OT_BITS512 then opsize := S_ZMM; + end; + end + else ; // empty ValidOpsize =>> nothing todo??? break; end; From 2ec8145ec543c0babf24ecd8de10d0114a91dca0 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 23 Dec 2020 03:56:23 +0000 Subject: [PATCH 025/116] external gas-assembler - handling special opcodes with multiple memref-size e.g. vfpclassps/pd - if operand-opsize < S_XMM =>> use memref-min-size git-svn-id: branches/tg74/avx512-0037785@47837 - --- compiler/i386/i386atts.inc | 4 ++-- compiler/i8086/i8086atts.inc | 4 ++-- compiler/ppcx64.lpi | 6 +++--- compiler/x86/rax86.pas | 16 +++++++++++++++- compiler/x86/x86ins.dat | 4 ++-- compiler/x86_64/x8664ats.inc | 4 ++-- 6 files changed, 26 insertions(+), 12 deletions(-) diff --git a/compiler/i386/i386atts.inc b/compiler/i386/i386atts.inc index f25a0a1855..c94394e2ec 100644 --- a/compiler/i386/i386atts.inc +++ b/compiler/i386/i386atts.inc @@ -1234,8 +1234,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/i8086/i8086atts.inc b/compiler/i8086/i8086atts.inc index 14d8ee5011..8fb88d59ce 100644 --- a/compiler/i8086/i8086atts.inc +++ b/compiler/i8086/i8086atts.inc @@ -1248,8 +1248,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index 5819327b82..5da9c79f20 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -1,7 +1,7 @@ - + @@ -22,14 +22,14 @@ - + - + diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 6c53779037..7845429bfe 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1519,9 +1519,23 @@ procedure Tx86Instruction.SetInstructionOpsize; if (gas_needsuffix[opcode] = AttSufMMS) and (ops > 0) then begin // special handling = use source operand for calculate instructions-opsize - // e.g. vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss + // e.g. vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss, + // vfpclass.. opsize:=tx86operand(operands[1]).opsize; + + if (MemRefSize in [msiMultipleMinSize128, msiMultipleMinSize256, msiMultipleMinSize512]) and + (not(opsize in [S_XMM, S_YMM, S_ZMM])) then + begin + // special handling for external gas assembler, special opcodes (e.g. vfpclassps/pd) + case MemRefSize of + msiMultipleMinSize128: opsize := S_XMM; + msiMultipleMinSize256: opsize := S_YMM; + msiMultipleMinSize512: opsize := S_ZMM; + else; + end; + end; + result := true; end else if MemRefSize in MemRefMultiples - [msiVMemMultiple] then diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index 56c9989a1a..e3dbe66aa6 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -7643,7 +7643,7 @@ xmmreg_mz,xmmreg,xmmreg_sae,imm8 \350\361\372\1\x55\75\120\27 ; VFPCLASSPD kreg_m,mem256 and mem512 must come first - map MemRefSize 256,512bits correct ; map all other MemrefSize (without broasdcast MemRef) to kreg_m, xmmrm -[VFPCLASSPD,vfpclasspdX] +[VFPCLASSPD,vfpclasspdS] (Ch_All) kreg_m,mem256,imm8 \350\352\361\364\372\1\x66\110\26 AVX512,TFV kreg_m,mem512,imm8 \350\351\352\361\372\1\x66\110\26 AVX512,TFV @@ -7656,7 +7656,7 @@ kreg_m,bmem64,imm8 \350\351\352\361\372\1\x66\110\26 ; VFPCLASSPS kreg_m,mem256 and mem512 must come first - map MemRefSize 256,512bits correct ; map all other MemrefSize (without broasdcast MemRef) to kreg_m, xmmrm -[VFPCLASSPS,vfpclasspsX] +[VFPCLASSPS,vfpclasspsS] (Ch_All) kreg_m,mem256,imm8 \350\361\364\372\1\x66\110\26 AVX512,TFV kreg_m,mem512,imm8 \350\351\361\372\1\x66\110\26 AVX512,TFV diff --git a/compiler/x86_64/x8664ats.inc b/compiler/x86_64/x8664ats.inc index 5b2fade508..65ba2fe8a4 100644 --- a/compiler/x86_64/x8664ats.inc +++ b/compiler/x86_64/x8664ats.inc @@ -1230,8 +1230,8 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufINT, +attsufMMS, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, From a0d21148b453cf1c6e879c4989737b829b0c8229 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 28 Dec 2020 04:35:22 +0000 Subject: [PATCH 026/116] avx512: external gas assembler not supported gather/scatter-opcodes without mask-register =>> not generate testcode git-svn-id: branches/tg74/avx512-0037785@47863 - --- tests/utils/avx/asmtestgenerator.pas | 88 +++++++++++++++++++++------- 1 file changed, 66 insertions(+), 22 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 480e2538b6..b842756266 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -1209,6 +1209,8 @@ var sl_RegCombi1: string; sl_RegCombi2: string; sl_RegCombi3: string; + MaskRegNeeded:boolean; + function PrepareOperandTyp(const aTyp: String): String; begin @@ -1250,6 +1252,18 @@ begin ; + + MaskRegNeeded := (Uppercase(aInst) = 'VGATHERDPD') or + (Uppercase(aInst) = 'VGATHERDPS') or + (Uppercase(aInst) = 'VGATHERDQPD') or + (Uppercase(aInst) = 'VGATHERDQPS') or + (Uppercase(aInst) = 'VPGATHERDD') or + (Uppercase(aInst) = 'VPGATHERDQ') or + (Uppercase(aInst) = 'VPGATHERQD') or + (Uppercase(aInst) = 'VPGATHERQQ') or + (Pos('VPSCATTER', Uppercase(aInst)) = 1) or + (Pos('VSCATTER', Uppercase(aInst)) = 1); + for il_Op := 1 to 4 do @@ -1314,7 +1328,8 @@ begin Item.Values.Add('XMM27' + sSuffix); Item.Values.Add('XMM31' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('XMM0'); Item.Values.Add('XMM9'); @@ -1331,7 +1346,8 @@ begin Item.Values.Add('XMM12' + sSuffix); Item.Values.Add('XMM15' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('XMM0'); Item.Values.Add('XMM4'); @@ -1353,8 +1369,8 @@ begin Item.OpActive := true; if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; + + sSuffix := ''; if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; @@ -1584,7 +1600,8 @@ begin Item.Values.Add('YMM27' + sSuffix); Item.Values.Add('YMM31' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('YMM0'); Item.Values.Add('YMM9'); @@ -1601,7 +1618,8 @@ begin Item.Values.Add('YMM12' + sSuffix); Item.Values.Add('YMM15' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('YMM0'); Item.Values.Add('YMM4'); @@ -1652,7 +1670,8 @@ begin Item.Values.Add('YMM27' + sSuffix); Item.Values.Add('YMM31' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('YMM0'); Item.Values.Add('YMM9'); @@ -1669,7 +1688,8 @@ begin Item.Values.Add('YMM12' + sSuffix); Item.Values.Add('YMM15' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('YMM0'); Item.Values.Add('YMM4'); @@ -1725,7 +1745,8 @@ begin Item.Values.Add('ZMM27' + sSuffix); Item.Values.Add('ZMM31' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('ZMM0'); Item.Values.Add('ZMM9'); @@ -1784,7 +1805,8 @@ begin Item.Values.Add('ZMM27' + sSuffix); Item.Values.Add('ZMM31' + sSuffix); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then begin Item.Values.Add('ZMM0'); Item.Values.Add('ZMM9'); @@ -2063,13 +2085,15 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); end; end @@ -2097,13 +2121,17 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); end; @@ -2132,13 +2160,17 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); end; @@ -2167,13 +2199,17 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); end; @@ -2202,13 +2238,17 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); end; @@ -2237,13 +2277,17 @@ begin if x64 then begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); end else begin VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if sSuffix <> '' then + if (sSuffix <> '') and + (MaskRegNeeded = false) + then VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); end; From 402f0d348e68536880a06507689e175ab7428226 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 28 Dec 2020 04:56:47 +0000 Subject: [PATCH 027/116] avxtestgenerator: add new commandline param '-m', create only these testfile(s) git-svn-id: branches/tg74/avx512-0037785@47864 - --- tests/utils/avx/avxopcodes.pas | 143 +++++++++++++++------------ tests/utils/avx/avxtestgenerator.lpi | 12 ++- tests/utils/avx/avxtestgenerator.pp | 11 ++- tests/utils/avx/options.pas | 4 + 4 files changed, 101 insertions(+), 69 deletions(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 00760c284e..de220e28c9 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -18,13 +18,13 @@ type protected procedure Init; - function InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; + function InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; public constructor Create; destructor Destroy; override; - function MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; + function MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask: String): boolean; procedure ListMemRefState; // function MakeTestFilesMREF(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath: String): boolean; @@ -924,9 +924,9 @@ begin FOpCodeList.Add('vpextrd,1,1,1,RM32,XMMREG,IMM8,'); FOpCodeList.Add('vpextrq,1,1,1,RM64,XMMREG,IMM8,'); FOpCodeList.Add('vpextrw,1,1,1,MEM16,XMMREG,IMM8,'); - FOpCodeList.Add('vpextrw,1,1,1,REG16,XMMREG,IMM8,'); + //FOpCodeList.Add('vpextrw,1,1,1,REG16,XMMREG,IMM8,'); FOpCodeList.Add('vpextrw,1,1,1,REG32,XMMREG,IMM8,'); - FOpCodeList.Add('vpextrw,1,1,1,REG64,XMMREG,IMM8,'); + //FOpCodeList.Add('vpextrw,1,1,1,REG64,XMMREG,IMM8,'); FOpCodeList.Add('vphaddd,1,1,0,XMMREG,XMMREG,XMMRM,'); FOpCodeList.Add('vphaddd,1,1,0,YMMREG,YMMREG,YMMRM,'); FOpCodeList.Add('vphaddsw,1,1,0,XMMREG,XMMREG,XMMRM,'); @@ -1401,20 +1401,20 @@ begin FOpCodeList.Add('vpblendd,1,1,0,XMMREG,XMMREG,XMMRM,IMM8'); FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,MEM8,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,XMMREG,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG8,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG8,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG64,,'); //FOpCodeList.Add('vpbroadcastb,1,1,1,XMMREG_MZ,REG16,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,MEM8,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,XMMREG,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG8,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG8,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG64,,'); //FOpCodeList.Add('vpbroadcastb,1,1,1,YMMREG_MZ,REG16,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,MEM8,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG8,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG8,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG64,,'); //FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,REG16,,'); FOpCodeList.Add('vpbroadcastb,1,1,1,ZMMREG_MZ,XMMREG,,'); FOpCodeList.Add('vpbroadcastd,1,1,1,XMMREG_MZ,MEM32,,'); @@ -1437,18 +1437,18 @@ begin FOpCodeList.Add('vpbroadcastq,1,1,1,ZMMREG_MZ,XMMREG,,'); FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,MEM16,'); FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,XMMREG,,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,REG16,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,REG16,'); FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,XMMREG_MZ,REG64,,'); FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,MEM16,'); FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,XMMREG,,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,REG16,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,REG16,'); FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,YMMREG_MZ,REG64,,'); FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,MEM16,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,REG16,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,REG16,'); FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,REG32,,'); - FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,REG64,,'); + //FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,REG64,,'); FOpCodeList.Add('vpbroadcastw,1,1,1,ZMMREG_MZ,XMMREG,,'); FOpCodeList.Add('vperm2i128,1,1,0,YMMREG,YMMREG,YMMRM,IMM8'); FOpCodeList.Add('vpermd,1,1,1,YMMREG_MZ,YMMREG,YMMRM,'); @@ -1530,7 +1530,7 @@ begin FOpCodeList.Add('vgatherqpd,1,1,1,XMMREG_M,XMEM64,,'); FOpCodeList.Add('vgatherqpd,1,1,0,YMMREG,YMEM64,YMMREG,'); FOpCodeList.Add('vgatherqpd,1,1,1,YMMREG_M,YMEM64,,'); - FOpCodeList.Add('vgatherqpd,1,1,1,ZMMREG_M,ZMEM32,,'); + FOpCodeList.Add('vgatherqpd,1,1,1,ZMMREG_M,ZMEM64,,'); FOpCodeList.Add('vgatherqps,1,1,0,XMMREG,XMEM32,XMMREG,'); FOpCodeList.Add('vgatherqps,1,1,0,XMMREG,YMEM32,XMMREG,'); FOpCodeList.Add('vgatherqps,1,1,1,XMMREG_M,XMEM32,,'); @@ -3260,18 +3260,20 @@ begin end; -function TAVXTestGenerator.InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFileExt: String; +function TAVXTestGenerator.InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; var - i: integer; + i,j: integer; sData: string; sDestFile: string; sLocalVarDataTyp: string; sl: TStringList; slAsm: TStringList; slLocalHeader: TStringList; + slFilemask: TStringList; LastOpCode: String; NewOpCode: String; + FoundNewOpcode: boolean; function SaveFile(aAsmList: TStringList; aOpcode, aDestPath, aFileExt: String; aHeaderList, aFooterList: TStringList): boolean; begin @@ -3295,61 +3297,78 @@ begin try slAsm := TStringList.Create; try - LastOpCode := ''; + slFilemask := TStringList.Create; + try + slFilemask.CommaText := ansilowercase(aFilemask); - for i := 0 to aOpCodeList.Count - 1 do - //for i := 0 to 0 do - begin - sl.Clear; - sl.CommaText := aOpCodeList[i]; + LastOpCode := ''; - while sl.Count < 8 do sl.Add(''); - - NewOpCode := ansilowercase(sl[0]); - if NewOpCode <> '' then + for i := 0 to aOpCodeList.Count - 1 do begin - if (not(aX64) and (sl[1] = '1')) or // i386 - (aX64 and (sl[2] = '1')) then // x86_64 + sl.Clear; + sl.CommaText := aOpCodeList[i]; + + while sl.Count < 8 do sl.Add(''); + + NewOpCode := ansilowercase(sl[0]); + + FoundNewOpcode := false; + for j := 0 to slFilemask.Count - 1 do begin - sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); + if Pos(slFilemask[j], NewOpCode) = 1 then + FoundNewOpcode := true; + end; - slLocalHeader := TStringList.Create; - try - slLocalHeader.Text := aHeaderList.text; + if not(FoundNewOpcode) and (slFilemask.Count > 0) then + NewOpcode := ''; - if (sl[4] = '') and - (sl[5] = '') and - (sl[6] = '') and - (sl[7] = '') then - begin // Opcode with no Params, e.g. VZEROALL - slAsm.Add(' ' + sl[0]); - end - else - begin - if aMREF then + if NewOpCode <> '' then + begin + if (not(aX64) and (sl[1] = '1')) or // i386 + (aX64 and (sl[2] = '1')) then // x86_64 + begin + sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); + + slLocalHeader := TStringList.Create; + try + slLocalHeader.Text := aHeaderList.text; + + if (sl[4] = '') and + (sl[5] = '') and + (sl[6] = '') and + (sl[7] = '') then + begin // Opcode with no Params, e.g. VZEROALL + slAsm.Add(' ' + sl[0]); + end + else begin - sLocalVarDataTyp := ''; - TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); - sDestFile := 'MREF_' + sDestFile; + if aMREF then + begin + sLocalVarDataTyp := ''; + TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + sDestFile := 'MREF_' + sDestFile; - if trim(sLocalVarDataTyp) = '' then - sLocalVarDataTyp := 'byte'; + if trim(sLocalVarDataTyp) = '' then + sLocalVarDataTyp := 'byte'; - slLocalHeader.Text := StringReplace(aHeaderList.Text, '$$$LOCALVARDATATYP$$$', sLocalVarDataTyp, [rfReplaceAll]); - end - else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); - end; + slLocalHeader.Text := StringReplace(aHeaderList.Text, '$$$LOCALVARDATATYP$$$', sLocalVarDataTyp, [rfReplaceAll]); + end + else TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + end; - SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); - writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); + SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); + writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); - finally - FreeAndNil(slLocalHeader); + finally + FreeAndNil(slLocalHeader); + end; + + slAsm.Clear; end; - - slAsm.Clear; end; end; + finally + FreeAndNil(slFilemask); end; finally FreeAndNil(slAsm); @@ -3360,7 +3379,7 @@ begin end; function TAVXTestGenerator.MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; - aDestPath: String): boolean; + aDestPath, aFilemask: String): boolean; var slHeader: TStringList; slFooter: TStringList; @@ -3581,7 +3600,7 @@ begin end; end; - InternalMakeTestFiles(aTyp = tfFPCMRef, aX64, aAVX512, aSAE, aDestPath, Fileext, FOpCodeList, slHeader, slFooter); + InternalMakeTestFiles(aTyp = tfFPCMRef, aX64, aAVX512, aSAE, aDestPath, aFilemask, Fileext, FOpCodeList, slHeader, slFooter); finally FreeAndNil(slFooter); diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index 89266c4b32..e0fadcd6ce 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -22,13 +22,13 @@ - + - + @@ -60,7 +60,15 @@ + + + + + + + + diff --git a/tests/utils/avx/avxtestgenerator.pp b/tests/utils/avx/avxtestgenerator.pp index 6f2f33ea6a..0b2fc0f2b1 100644 --- a/tests/utils/avx/avxtestgenerator.pp +++ b/tests/utils/avx/avxtestgenerator.pp @@ -44,6 +44,7 @@ begin writeln('-h help'); writeln('-f [fpc,fpcmref,nasm,fasm,fpcinc] outputformat'); writeln('-l list opcode-memrefsize-states'); + writeln('-m create only these testfile(s) (e.g. -mvgather,vpgather)'); writeln('-o destination path'); writeln('-p [x8664] codegenerator for x86_64 platform'); writeln('-z avx512'); @@ -56,11 +57,11 @@ begin //exit; case OutputFormat of - 'f': MakeTestFiles(tfFPC, x64, AVX512, false, Path); - 'F': MakeTestFiles(tfFasm, x64, AVX512, false, Path); - 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path); - 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path); - 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path); + 'f': MakeTestFiles(tfFPC, x64, AVX512, false, Path, Filemask); + 'F': MakeTestFiles(tfFasm, x64, AVX512, false, Path, Filemask); + 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path, Filemask); + 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path, Filemask); + 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path, Filemask); 'l': ListMemRefState; end; end; diff --git a/tests/utils/avx/options.pas b/tests/utils/avx/options.pas index 28eab2500a..8e6566b144 100644 --- a/tests/utils/avx/options.pas +++ b/tests/utils/avx/options.pas @@ -36,6 +36,7 @@ type FOutputFormat: Char; FPath: string; FMemRef: boolean; + FFilemask: string; public constructor Create; @@ -47,6 +48,7 @@ type property AVX512: boolean read FAVX512 write FAVX512; property Path: string read FPath write FPath; property MemRef: boolean read FMemref write FMemRef; + property Filemask: string read FFilemask write FFilemask; end; implementation @@ -63,6 +65,7 @@ begin FOutputFormat := '?'; FPath := ''; FMemRef := false; + FFilemask := ''; end; procedure TOptions.LoadParams; @@ -103,6 +106,7 @@ begin else IsInvalidParam := true; 'l': FOutputFormat := 'l'; 'z': FAVX512 := true; + 'm': FFilemask := sValue; 'o': if sValue <> '' then begin FPath := IncludeTrailingBackslash(sValue); From 9b2bed6fdf168b694b7c62751b208bc82d075c16 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 28 Dec 2020 05:00:58 +0000 Subject: [PATCH 028/116] external gas assembler: special handling for correct suffix in vfpclass-opcodes git-svn-id: branches/tg74/avx512-0037785@47865 - --- compiler/x86/rax86.pas | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 7845429bfe..3cbac44ed9 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1521,8 +1521,11 @@ procedure Tx86Instruction.SetInstructionOpsize; // special handling = use source operand for calculate instructions-opsize // e.g. vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss, // vfpclass.. - - opsize:=tx86operand(operands[1]).opsize; + + if (ops > 2) and + (tx86operand(operands[1]).opr.typ = OPR_CONSTANT) then + opsize:=tx86operand(operands[2]).opsize + else opsize:=tx86operand(operands[1]).opsize; if (MemRefSize in [msiMultipleMinSize128, msiMultipleMinSize256, msiMultipleMinSize512]) and (not(opsize in [S_XMM, S_YMM, S_ZMM])) then From 2452e991b86091045a296ca6251b66ca3f6cea5d Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 29 Dec 2020 04:49:52 +0000 Subject: [PATCH 029/116] internal assembler-reader x86 opsize local/global var - cleanup git-svn-id: branches/tg74/avx512-0037785@47885 - --- compiler/x86/aasmcpu.pas | 7 ----- compiler/x86/rax86.pas | 39 ---------------------------- tests/utils/avx/asmtestgenerator.pas | 12 ++------- 3 files changed, 2 insertions(+), 56 deletions(-) diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index bf48134dad..5e5cd3b769 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -1832,13 +1832,6 @@ implementation if (insot and OT_SIZE_MASK) = 0 then begin case insot and (OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of - //OT_XMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize128 - // then insot := insot or OT_BITS128; - //OT_YMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize256 - // then insot := insot or OT_BITS256; - //OT_ZMMRM: if InsTabMemRefSizeInfoCache^[opcode].MemRefSize <> msiMultipleMinSize512 - // then insot := insot or OT_BITS512; - OT_MEM128: insot := insot or OT_BITS128; OT_MEM256: insot := insot or OT_BITS256; OT_MEM512: insot := insot or OT_BITS512; diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 3cbac44ed9..e2e0e1f0f3 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -868,7 +868,6 @@ begin if memoffset = 0 then begin Message3(asmr_w_check_mem_operand_size3, - //std_op2str[opcode], getstring(false), ToStr(memopsize), ToStr(memrefsize) @@ -877,7 +876,6 @@ begin else begin Message4(asmr_w_check_mem_operand_size_offset, - //std_op2str[opcode], getstring(false), ToStr(memopsize), ToStr(memrefsize), @@ -2106,43 +2104,6 @@ begin if asize<>0 then ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; end; - - // if MemRefInfo(opcode).ExistsSSEAVX then - // begin - // asize := 0; - // - // case operands[i].size of - // OS_32,OS_M32: if (operands[i].HasType) or - // (MemRefInfo(opcode).MemRefSize = msiMem32) or - // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) - // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and - // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST32) - // //) - // then - // asize:=OT_BITS32; - // OS_64,OS_M64: if (operands[i].HasType) or - // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) - // (MemRefInfo(opcode).MemRefSize = msiMem64) or - // //(((tx86operand(operands[i]).vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST) and - // // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) - // //) then - // (MemRefInfo(opcode).MemRefSizeBCST = msbBCST64) then - // asize:=OT_BITS64; - // OS_M128: if (operands[i].HasType) or - // (MemRefInfo(opcode).MemRefSize = msiMem128) then - // //asize:=OT_BITS128; - // OS_M256: if (operands[i].HasType) or - // (MemRefInfo(opcode).MemRefSize = msiMem256) then - // //asize:=OT_BITS256; - // OS_M512: if (operands[i].HasType) or - // (MemRefInfo(opcode).MemRefSize = msiMem512) then - // //asize:=OT_BITS512; - // else; - // end; - // - // if asize<>0 then - // ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; - // end; end; OPR_REFERENCE: begin diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index b842756266..055aa37c72 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -1253,19 +1253,11 @@ begin ; - MaskRegNeeded := (Uppercase(aInst) = 'VGATHERDPD') or - (Uppercase(aInst) = 'VGATHERDPS') or - (Uppercase(aInst) = 'VGATHERDQPD') or - (Uppercase(aInst) = 'VGATHERDQPS') or - (Uppercase(aInst) = 'VPGATHERDD') or - (Uppercase(aInst) = 'VPGATHERDQ') or - (Uppercase(aInst) = 'VPGATHERQD') or - (Uppercase(aInst) = 'VPGATHERQQ') or + MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or + (Pos('VPGATHER', Uppercase(aInst)) = 1) or (Pos('VPSCATTER', Uppercase(aInst)) = 1) or (Pos('VSCATTER', Uppercase(aInst)) = 1); - - for il_Op := 1 to 4 do begin sl_Prefix := ''; From 507f0b3362db9513e09255168306a3c46d35f0b3 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 29 Dec 2020 05:12:47 +0000 Subject: [PATCH 030/116] working on internal assembler-reader x86 opsize local/global var git-svn-id: branches/tg74/avx512-0037785@47886 - --- compiler/x86/rax86.pas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index e2e0e1f0f3..262289dc95 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -2091,7 +2091,7 @@ begin begin asize := 0; - if ((operands[i] as tx86operand).vopext <> 0) and + if ((operands[i] as tx86operand).vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST) and (MemRefInfo(opcode).MemRefSizeBCST in [msbBCST32,msbBCST64]) then begin case operands[i].size of From 7bba64854b52c877aac354180ba7928a903ff23f Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 30 Dec 2020 07:10:37 +0000 Subject: [PATCH 031/116] internal assembler-reader x86 opsize local/global var - cleanup git-svn-id: branches/tg74/avx512-0037785@47899 - --- compiler/x86/aasmcpu.pas | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index 5e5cd3b769..280ceee384 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -1825,24 +1825,8 @@ implementation for i:=0 to p^.ops-1 do begin insot:=p^.optypes[i]; - if ((insot and (OT_XMMRM or OT_REG_EXTRA_MASK)) = OT_XMMRM) OR - ((insot and (OT_YMMRM or OT_REG_EXTRA_MASK)) = OT_YMMRM) OR - ((insot and (OT_ZMMRM or OT_REG_EXTRA_MASK)) = OT_ZMMRM) then - begin - if (insot and OT_SIZE_MASK) = 0 then - begin - case insot and (OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of - OT_MEM128: insot := insot or OT_BITS128; - OT_MEM256: insot := insot or OT_BITS256; - OT_MEM512: insot := insot or OT_BITS512; - - else - ; - end; - end; - end; - currot:=oper[i]^.ot; + { Check the operand flags } if (insot and (not currot) and OT_NON_SIZE)<>0 then exit; From f8fc0073248b2be95224d2419bb844b4bec0d5e9 Mon Sep 17 00:00:00 2001 From: tg74 Date: Sat, 2 Jan 2021 22:13:27 +0000 Subject: [PATCH 032/116] internal assembler-reader x86 (local/global var) - validate asm-opcode-attsuffix and memrefsize git-svn-id: branches/tg74/avx512-0037785@47984 - --- compiler/i386/i386atts.inc | 14 +- compiler/i8086/i8086atts.inc | 14 +- compiler/msg/errore.msg | 1 + compiler/msgidx.inc | 5 +- compiler/msgtxt.inc | 776 +++++++++++++++++------------------ compiler/x86/aasmcpu.pas | 24 +- compiler/x86/rax86.pas | 7 +- compiler/x86/x86ins.dat | 8 +- compiler/x86_64/x8664ats.inc | 14 +- 9 files changed, 440 insertions(+), 423 deletions(-) diff --git a/compiler/i386/i386atts.inc b/compiler/i386/i386atts.inc index c94394e2ec..256e241047 100644 --- a/compiler/i386/i386atts.inc +++ b/compiler/i386/i386atts.inc @@ -425,9 +425,9 @@ attsufNONE, attsufNONE, attsufNONE, attsufINT, -attsufINT, attsufNONE, -attsufINT, +attsufNONE, +attsufNONE, attsufNONE, attsufNONE, attsufNONE, @@ -539,11 +539,6 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufNONE, -attsufINT, -attsufNONE, -attsufNONE, attsufNONE, attsufNONE, attsufINT, @@ -607,6 +602,11 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, attsufINT, attsufNONE, attsufNONE, diff --git a/compiler/i8086/i8086atts.inc b/compiler/i8086/i8086atts.inc index 8fb88d59ce..12d9399385 100644 --- a/compiler/i8086/i8086atts.inc +++ b/compiler/i8086/i8086atts.inc @@ -425,9 +425,9 @@ attsufNONE, attsufNONE, attsufNONE, attsufINT, -attsufINT, attsufNONE, -attsufINT, +attsufNONE, +attsufNONE, attsufNONE, attsufNONE, attsufNONE, @@ -539,11 +539,6 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufNONE, -attsufINT, -attsufNONE, -attsufNONE, attsufNONE, attsufNONE, attsufINT, @@ -607,6 +602,11 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, attsufINT, attsufNONE, attsufNONE, diff --git a/compiler/msg/errore.msg b/compiler/msg/errore.msg index 3f9f8bb024..16e317f125 100644 --- a/compiler/msg/errore.msg +++ b/compiler/msg/errore.msg @@ -2907,6 +2907,7 @@ asmr_e_multiple_segment_overrides=07139_E_Cannot use multiple segment overrides asmr_w_multiple_segment_overrides=07140_W_Multiple segment overrides (only the last one will take effect) asmr_w_segment_override_ignored_in_64bit_mode=07141_W_Segment base $1 will be generated, but is ignored by the CPU in 64-bit mode asmr_e_mismatch_broadcasting_elements=07142_E_Mismatch broadcasting elements (expected: {$1} found: {$2}) +asmr_e_not_supported_combination_attsuffix_memrefsize_type=07143_E_Not supported combination opcode: $1 - att-suffix-type {$2} and memrefsize-type {$3} # # Assembler/binary writers # diff --git a/compiler/msgidx.inc b/compiler/msgidx.inc index 373883607f..9bad034d23 100644 --- a/compiler/msgidx.inc +++ b/compiler/msgidx.inc @@ -849,6 +849,7 @@ const asmr_w_multiple_segment_overrides=07140; asmr_w_segment_override_ignored_in_64bit_mode=07141; asmr_e_mismatch_broadcasting_elements=07142; + asmr_e_not_supported_combination_attsuffix_memrefsize_type=07143; asmw_f_too_many_asm_files=08000; asmw_f_assembler_output_not_supported=08001; asmw_f_comp_not_supported=08002; @@ -1127,9 +1128,9 @@ const option_info=11024; option_help_pages=11025; - MsgTxtSize = 85795; + MsgTxtSize = 85888; MsgIdxMax : array[1..20] of longint=( - 28,106,356,130,99,63,143,36,223,68, + 28,106,356,130,99,63,144,36,223,68, 62,20,30,1,1,1,1,1,1,1 ); diff --git a/compiler/msgtxt.inc b/compiler/msgtxt.inc index 8ba502a975..fd711070a8 100644 --- a/compiler/msgtxt.inc +++ b/compiler/msgtxt.inc @@ -1049,359 +1049,363 @@ const msgtxt : array[0..000357,1..240] of char=( '07141_W_Segment base $1 will be generated, but is ignored by the CPU i'+ 'n 64-bit mode'#000+ '07142_E_Mismatch broadcasting elements (expected: ','{$1} found: {$2})'#000+ + '07143_E_Not supported combination opcode: $1 - att-suffix-type {$2} an'+ + 'd memrefsize-type {$3}'#000+ '08000_F_Too many assembler files'#000+ '08001_F_Selected assembler output not supported'#000+ '08002_F_Comp not supported'#000+ - '08003_F_Direct not support for binary writers'#000+ + '08003_F_Direct not su','pport for binary writers'#000+ '08004_E_Allocating of data is only allowed in bss section'#000+ - '08005_F_No',' binary writer selected'#000+ + '08005_F_No binary writer selected'#000+ '08006_E_Asm: Opcode $1 not in table'#000+ '08007_E_Asm: $1 invalid combination of opcode and operands'#000+ - '08008_E_Asm: 16 Bit references not supported'#000+ + '08008_E_Asm: 16 Bit referenc','es not supported'#000+ '08009_E_Asm: Invalid effective address'#000+ - '08010_E_Asm: Immediate or reference e','xpected'#000+ + '08010_E_Asm: Immediate or reference expected'#000+ '08011_E_Asm: $1 value exceeds bounds $2'#000+ '08012_E_Asm: Short jump is out of range $1'#000+ '08013_E_Asm: Undefined label $1'#000+ - '08014_E_Asm: Comp type not supported for this target'#000+ + '08014_E_Asm: Comp type n','ot supported for this target'#000+ '08015_E_Asm: Extended type not supported for this target'#000+ - '08016_E','_Asm: Duplicate label $1'#000+ + '08016_E_Asm: Duplicate label $1'#000+ '08017_E_Asm: Redefined label $1'#000+ '08018_E_Asm: First defined here'#000+ '08019_E_Asm: Invalid register $1'#000+ - '08020_E_Asm: 16 or 32 Bit references not supported'#000+ + '08020_E_Asm: 16 or 32 Bit',' references not supported'#000+ '08021_E_Asm: 64 Bit operands not supported'#000+ - '08022_E_Asm: AH,BH,CH or',' DH cannot be used in an instruction requiri'+ - 'ng REX prefix'#000+ + '08022_E_Asm: AH,BH,CH or DH cannot be used in an instruction requiring'+ + ' REX prefix'#000+ '08023_E_Missing .seh_endprologue directive'#000+ '08024_E_Function prologue exceeds 255 bytes'#000+ - '08025_E_.seh_handlerdata directive without preceding .seh_handler'#000+ - '08026_F_Relocation count for ','section $1 exceeds 65535'#000+ + '08','025_E_.seh_handlerdata directive without preceding .seh_handler'#000+ + '08026_F_Relocation count for section $1 exceeds 65535'#000+ '08027_N_Change of bind type of symbol $1 from $2 to $3 after use'#000+ - '08028_H_Change of bind type of symbol $1 from $2 to $3 after use'#000+ + '08028_H_Change of bind type of symbol $1 from $2 to $3 af','ter use'#000+ '08029_E_Asm: 32 Bit references not supported'#000+ '08030_F_Code segment too large'#000+ - '08031_F_D','ata segment too large'#000+ + '08031_F_Data segment too large'#000+ '08032_E_Instruction not supported by the selected instruction set'#000+ - '08033_E_Asm: conditional branch destination is out of range'#000+ + '08033_E_Asm: conditional branch destination is out of range',#000+ '08034_E_Asm: RIP cannot be used as index register or with another regi'+ 'ster in a reference'#000+ - '08','035_F_Illegal function size for SEH function'#000+ + '08035_F_Illegal function size for SEH function'#000+ '09000_W_Source operating system redefined'#000+ '09001_I_Assembling (pipe) $1'#000+ - '09002_E_Can'#039't create assembler file: $1'#000+ + '09002_E_Can'#039't create assembler ','file: $1'#000+ '09003_E_Can'#039't create object file: $1 (error code: $2)'#000+ - '09004_E_Can'#039't create archive f','ile: $1'#000+ + '09004_E_Can'#039't create archive file: $1'#000+ '09005_E_Assembler $1 not found, switching to external assembling'#000+ '09006_T_Using assembler: $1'#000+ '09007_E_Error while assembling exitcode $1'#000+ - '09008_E_Can'#039't call the assembler, error $1 switching to external a'+ - 'ssembling'#000+ - '09009_I_Assembling $','1'#000+ + '090','08_E_Can'#039't call the assembler, error $1 switching to external'+ + ' assembling'#000+ + '09009_I_Assembling $1'#000+ '09010_I_Assembling with smartlinking $1'#000+ '09011_W_Object $1 not found, Linking may fail !'#000+ '09012_W_Library $1 not found, Linking may fail !'#000+ - '09013_E_Error while linking'#000+ + '09013_E_','Error while linking'#000+ '09014_E_Can'#039't call the linker, switching to external linking'#000+ - '09015_I_Link','ing $1'#000+ + '09015_I_Linking $1'#000+ '09016_E_Util $1 not found, switching to external linking'#000+ '09017_T_Using util $1'#000+ '09018_E_Creation of Executables not supported'#000+ - '09019_E_Creation of Dynamic/Shared Libraries not supported'#000+ - '09035_E_Creation of Static Libraries not supporte','d'#000+ + '09019_E_Creatio','n of Dynamic/Shared Libraries not supported'#000+ + '09035_E_Creation of Static Libraries not supported'#000+ '09020_I_Closing script $1'#000+ '09021_E_Resource compiler "$1" not found, switching to external mode'#000+ '09022_I_Compiling resource $1'#000+ - '09023_T_Unit $1 cannot be statically linked, switching to smart linkin'+ - 'g'#000+ - '09024_T_Unit $1 cannot be smart linked, s','witching to static linking'#000+ + '09023_T_Unit $1 cann','ot be statically linked, switching to smart link'+ + 'ing'#000+ + '09024_T_Unit $1 cannot be smart linked, switching to static linking'#000+ '09025_T_Unit $1 cannot be shared linked, switching to static linking'#000+ '09026_E_Unit $1 cannot be smart or static linked'#000+ - '09027_E_Unit $1 cannot be shared or static linked'#000+ - '09028_D_Calling resource compiler "$1" with "','$2" as command line'#000+ + '09','027_E_Unit $1 cannot be shared or static linked'#000+ + '09028_D_Calling resource compiler "$1" with "$2" as command line'#000+ '09029_E_Error while compiling resources'#000+ '09030_E_Can'#039't call the resource compiler "$1", switching to extern'+ 'al mode'#000+ - '09031_E_Can'#039't open resource file "$1"'#000+ + '09031_E_Can'#039't',' open resource file "$1"'#000+ '09032_E_Can'#039't write resource file "$1"'#000+ - '09033_N_File "$1" not found f','or backquoted cat command'#000+ + '09033_N_File "$1" not found for backquoted cat command'#000+ '09034_W_"$1" not found, this will probably cause a linking failure'#000+ '09128_F_Can'#039't post process executable $1'#000+ - '09129_F_Can'#039't open executable $1'#000+ + '09129_F_Can'#039't',' open executable $1'#000+ '09130_X_Size of Code: $1 bytes'#000+ - '09131_X_Size of initialized data: $1 bytes',#000+ + '09131_X_Size of initialized data: $1 bytes'#000+ '09132_X_Size of uninitialized data: $1 bytes'#000+ '09133_X_Stack space reserved: $1 bytes'#000+ '09134_X_Stack space committed: $1 bytes'#000+ - '09200_F_Executable image size is too big for $1 target.'#000+ - '09201_W_Object file "$1" contains 32-bit absolute relocatio','n to symb'+ - 'ol "$2".'#000+ + '09200_F_Executable ima','ge size is too big for $1 target.'#000+ + '09201_W_Object file "$1" contains 32-bit absolute relocation to symbol'+ + ' "$2".'#000+ '09202_E_Program segment too large (exceeds 64k by $1 bytes)'#000+ '09203_E_Code segment "$1" too large (exceeds 64k by $2 bytes)'#000+ - '09204_E_Data segment "$1" too large (exceeds 64k by $2 bytes)'#000+ - '09205_E_Segment "$1" too large (exceed','s 64k by $2 bytes)'#000+ + '09204_E','_Data segment "$1" too large (exceeds 64k by $2 bytes)'#000+ + '09205_E_Segment "$1" too large (exceeds 64k by $2 bytes)'#000+ '09206_E_Group "$1" too large (exceeds 64k by $2 bytes)'#000+ '09207_E_Cannot create a .COM file, because the program contains segmen'+ - 't relocations'#000+ + 't r','elocations'#000+ '09208_W_Program "$1" uses experimental CheckPointer option'#000+ - '09209_E_Multiple define','d symbol "$1"'#000+ + '09209_E_Multiple defined symbol "$1"'#000+ '09210_E_COMDAT selection mode $1 not supported (section: "$1")'#000+ '09211_E_Associative section expected for COMDAT section "$1"'#000+ - '09212_E_COMDAT section selection mode doesn'#039't match for section "$'+ - '1" and symbol "$2"'#000+ - '09213_E_Associati','ve COMDAT section for section "$1" not found'#000+ + '09212_E_C','OMDAT section selection mode doesn'#039't match for section '+ + '"$1" and symbol "$2"'#000+ + '09213_E_Associative COMDAT section for section "$1" not found'#000+ '09214_D_Discarding duplicate symbol "$1" due to COMDAT selection mode'#000+ - '09215_D_Discarding duplicate symbol "$1" with same size due to COMDAT '+ - 'selection mode'#000+ - '09216_D_Discarding duplicate symbol "$1"',' with same content due to CO'+ - 'MDAT selection mode'#000+ + '09215_D_Discarding duplicate sym','bol "$1" with same size due to COMDA'+ + 'T selection mode'#000+ + '09216_D_Discarding duplicate symbol "$1" with same content due to COMD'+ + 'AT selection mode'#000+ '09217_D_Replacing duplicate symbol "$1" with smaller size due to COMDA'+ 'T selection mode'#000+ - '09218_E_Size of duplicate COMDAT symbol "$1" differs'#000+ - '09219_E_Content of duplicate COMDAT symbol "$1" diff','ers'#000+ + '09218_E_Size',' of duplicate COMDAT symbol "$1" differs'#000+ + '09219_E_Content of duplicate COMDAT symbol "$1" differs'#000+ '09220_E_COMDAT selection mode for symbol "$1" differs'#000+ '09221_E_Undefined symbol: $1 (first seen in $2)'#000+ '09222_E_Undefined symbol: $1'#000+ - '10000_T_Unitsearch: $1'#000+ + '10000_T_Unit','search: $1'#000+ '10001_T_PPU Loading $1'#000+ '10002_U_PPU Name: $1'#000+ '10003_U_PPU Flags: $1'#000+ - '10004_U_PPU Crc:',' $1'#000+ + '10004_U_PPU Crc: $1'#000+ '10005_U_PPU Time: $1'#000+ '10006_U_PPU File too short'#000+ '10007_U_PPU Invalid Header (no PPU at the begin)'#000+ '10008_U_PPU Invalid Version $1'#000+ - '10009_U_PPU is compiled for another processor'#000+ + '10009_U_PPU is ','compiled for another processor'#000+ '10010_U_PPU is compiled for another target'#000+ - '10011_U_PPU Source:',' $1'#000+ + '10011_U_PPU Source: $1'#000+ '10012_U_Writing $1'#000+ '10013_F_Can'#039't Write PPU-File'#000+ '10014_F_Error reading PPU-File'#000+ '10015_F_Unexpected end of PPU-File'#000+ - '10016_F_Invalid PPU-File entry: $1'#000+ + '10016_F_Invalid PPU-File entr','y: $1'#000+ '10017_F_PPU Dbx count problem'#000+ '10018_E_Illegal unit name: $1 (expecting $2)'#000+ - '10019_F_Too ','much units'#000+ + '10019_F_Too much units'#000+ '10020_F_Circular unit reference between $1 and $2'#000+ '10021_F_Can'#039't compile unit $1, no sources available'#000+ - '10022_F_Can'#039't find unit $1 used by $2'#000+ + '10022_F_Can'#039't find unit $1 used by',' $2'#000+ '10023_W_Unit $1 was not found but $2 exists'#000+ '10024_F_Unit $1 searched but $2 found'#000+ - '10025_W','_Compiling the system unit requires the -Us switch'#000+ + '10025_W_Compiling the system unit requires the -Us switch'#000+ '10026_F_There were $1 errors compiling module, stopping'#000+ '10027_U_Load from $1 ($2) unit $3'#000+ - '10028_U_Recompiling $1, checksum changed for $2'#000+ + '10028_','U_Recompiling $1, checksum changed for $2'#000+ '10029_U_Recompiling $1, source found only'#000+ - '10030_U_R','ecompiling unit, static lib is older than ppufile'#000+ + '10030_U_Recompiling unit, static lib is older than ppufile'#000+ '10031_U_Recompiling unit, shared lib is older than ppufile'#000+ - '10032_U_Recompiling unit, obj and asm are older than ppufile'#000+ + '10032_U_Recompiling unit, obj and asm ','are older than ppufile'#000+ '10033_U_Recompiling unit, obj is older than asm'#000+ - '10034_U_Parsing interf','ace of $1'#000+ + '10034_U_Parsing interface of $1'#000+ '10035_U_Parsing implementation of $1'#000+ '10036_U_Second load for unit $1'#000+ '10037_U_PPU Check file $1 time $2'#000+ - '10040_W_Can'#039't recompile unit $1, but found modified include files'#000+ - '10041_U_File $1 is newer than the one used for creating PPU f','ile $2'#000+ + '10040_W_Can'#039't recompile unit $1, b','ut found modified include file'+ + 's'#000+ + '10041_U_File $1 is newer than the one used for creating PPU file $2'#000+ '10042_U_Trying to use a unit which was compiled with a different FPU m'+ 'ode'#000+ '10043_U_Loading interface units from $1'#000+ - '10044_U_Loading implementation units from $1'#000+ + '10044_U_Loading implementa','tion units from $1'#000+ '10045_U_Interface CRC changed for unit $1'#000+ - '10046_U_Implementation CRC chang','ed for unit $1'#000+ + '10046_U_Implementation CRC changed for unit $1'#000+ '10047_U_Finished compiling unit $1'#000+ '10048_U_Adding dependency: $1 depends on $2'#000+ '10049_U_No reload, is caller: $1'#000+ - '10050_U_No reload, already in second compile: $1'#000+ + '10050_U_No reload, a','lready in second compile: $1'#000+ '10051_U_Flag for reload: $1'#000+ '10052_U_Forced reloading'#000+ - '10053_U_Pre','vious state of $1: $2'#000+ + '10053_U_Previous state of $1: $2'#000+ '10054_U_Already compiling $1, setting second compile'#000+ '10055_U_Loading unit $1'#000+ '10056_U_Finished loading unit $1'#000+ - '10057_U_Registering new unit $1'#000+ + '10057_U_Registe','ring new unit $1'#000+ '10058_U_Re-resolving unit $1'#000+ - '10059_U_Skipping re-resolving unit $1, still lo','ading used units'#000+ + '10059_U_Skipping re-resolving unit $1, still loading used units'#000+ '10060_U_Unloading resource unit $1 (not needed)'#000+ '10061_E_Unit $1 was compiled using a different whole program optimizat'+ - 'ion feedback input ($2, $3); recompile it without wpo or use the same '+ - 'wpo feedback input file for this co','mpilation invocation'#000+ + 'ion feedback',' input ($2, $3); recompile it without wpo or use the sam'+ + 'e wpo feedback input file for this compilation invocation'#000+ '10062_U_Indirect interface (objects/classes) CRC changed for unit $1'#000+ '10063_U_PPU is compiled for another i8086 memory model'#000+ - '10064_U_Loading unit $1 from package $2'#000+ - '10065_F_Internal type "$1" was not found. Check if you ','use the corre'+ - 'ct run time library.'#000+ + '10','064_U_Loading unit $1 from package $2'#000+ + '10065_F_Internal type "$1" was not found. Check if you use the correct'+ + ' run time library.'#000+ '10066_F_Internal type "$1" does not look as expected. Check if you use'+ ' the correct run time library.'#000+ - '10067_U_Skipping unit, PPU and compiler have to be both compiled with '+ - 'or without LLVM support'#000+ - '11000_O_$1 ','[options] [options]'#000+ + '10067_U_Skip','ping unit, PPU and compiler have to be both compiled wit'+ + 'h or without LLVM support'#000+ + '11000_O_$1 [options] [options]'#000+ '11001_W_Only one source file supported, changing source file to compil'+ 'e from "$1" into "$2"'#000+ - '11002_W_DEF file can be created only for OS/2'#000+ + '11002_W_DEF file can be',' created only for OS/2'#000+ '11003_E_Nested response files are not supported'#000+ - '11004_F_No source file',' name in command line'#000+ + '11004_F_No source file name in command line'#000+ '11005_N_No option inside $1 config file'#000+ '11006_E_Illegal parameter: $1'#000+ '11007_H_-? writes help pages'#000+ - '11008_F_Too many config files nested'#000+ + '11008_F_Too many config fi','les nested'#000+ '11009_F_Unable to open file $1'#000+ '11010_D_Reading further options from $1'#000+ - '11011_W_Tar','get is already set to: $1'#000+ + '11011_W_Target is already set to: $1'#000+ '11012_W_Shared libs not supported on DOS platform, reverting to static'+ #000+ - '11013_F_In options file $1 at line $2 too many #IF(N)DEFs encountered'#000+ + '11013_F_In options file $1 at line $2 too many #IF','(N)DEFs encountere'+ + 'd'#000+ '11014_F_In options file $1 at line $2 unexpected #ENDIFs encountered'#000+ - '1101','5_F_Open conditional at the end of the options file'#000+ + '11015_F_Open conditional at the end of the options file'#000+ '11016_W_Debug information generation is not supported by this executab'+ 'le'#000+ - '11017_H_Try recompiling with -dGDB'#000+ + '11017_H_Try recompilin','g with -dGDB'#000+ '11018_W_You are using the obsolete switch $1'#000+ - '11019_W_You are using the obsolete ','switch $1, please use $2'#000+ + '11019_W_You are using the obsolete switch $1, please use $2'#000+ '11020_N_Switching assembler to default source writing assembler'#000+ - '11021_W_Assembler output selected "$1" is not compatible with "$2"'#000+ + '11021_W_Assembler output selected "$1" is not compatible w','ith "$2"'#000+ '11022_W_"$1" assembler use forced'#000+ '11026_T_Reading options from file $1'#000+ - '11027_T_Readi','ng options from environment $1'#000+ + '11027_T_Reading options from environment $1'#000+ '11028_D_Handling option "$1"'#000+ '11029_O_*** press enter ***'#000+ '11030_H_Start of reading config file $1'#000+ - '11031_H_End of reading config file $1'#000+ + '11031_H_End of read','ing config file $1'#000+ '11032_D_Interpreting option "$1"'#000+ - '11036_D_Interpreting firstpass option "$1','"'#000+ + '11036_D_Interpreting firstpass option "$1"'#000+ '11033_D_Interpreting file option "$1"'#000+ '11034_D_Reading config file "$1"'#000+ '11035_D_Found source file name "$1"'#000+ '11039_E_Unknown codepage "$1"'#000+ - '11040_F_Config file $1 is a directory'#000+ - '11041_W_Assembler output selected "$1" cannot generate debug in','fo, d'+ - 'ebugging disabled'#000+ + '11040_F_','Config file $1 is a directory'#000+ + '11041_W_Assembler output selected "$1" cannot generate debug info, deb'+ + 'ugging disabled'#000+ '11042_W_Use of ppc386.cfg is deprecated, please use fpc.cfg instead'#000+ - '11043_F_In options file $1 at line $2 #ELSE directive without #IF(N)DE'+ - 'F found'#000+ + '11043_F_In options file $1 at line $2 #ELSE directive wi','thout #IF(N)'+ + 'DEF found'#000+ '11044_F_Option "$1" is not, or not yet, supported on the current targe'+ - 't',' platform'#000+ + 't platform'#000+ '11045_F_The feature "$1" is not, or not yet, supported on the selected'+ ' target platform'#000+ - '11046_N_DWARF debug information cannot be used with smart linking on t'+ - 'his target, switching to static linking'#000+ - '11047_W_Option "$1" is ignored fo','r the current target platform.'#000+ + '11046_N_DWARF debug information cannot be used wit','h smart linking on'+ + ' this target, switching to static linking'#000+ + '11047_W_Option "$1" is ignored for the current target platform.'#000+ '11048_W_Disabling external debug information because it is unsupported'+ - ' for the selected target/debug format combination.'#000+ + ' for the selected target/debug format combinat','ion.'#000+ '11049_N_DWARF debug information cannot be used with smart linking with'+ - ' external assemble','r, disabling static library creation.'#000+ + ' external assembler, disabling static library creation.'#000+ '11050_E_Invalid value for MACOSX_DEPLOYMENT_TARGET environment variabl'+ 'e: $1'#000+ - '11051_E_Invalid value for IPHONEOS_DEPLOYMENT_TARGET environment varia'+ - 'ble: $1'#000+ - '11052_E_You must use a FPU type of VFPV2, VFPV3 ','or VFPV3_D16 when us'+ - 'ing the EABIHF ABI target'#000+ + '11051_E_Invalid value for IPHONEO','S_DEPLOYMENT_TARGET environment var'+ + 'iable: $1'#000+ + '11052_E_You must use a FPU type of VFPV2, VFPV3 or VFPV3_D16 when usin'+ + 'g the EABIHF ABI target'#000+ '11053_W_The selected debug format is not supported on the current targ'+ - 'et, not changing the current setting'#000+ + 'et, not changing the current se','tting'#000+ '11054_E_Argument to "$1" is missing'#000+ '11055_E_Malformed parameter: $1'#000+ - '11056_W_Smart linki','ng requires external linker'#000+ + '11056_W_Smart linking requires external linker'#000+ '11057_E_Creating .COM files is not supported in the current memory mod'+ - 'el. Only the tiny memory model supports making .COM files.'#000+ + 'el. Only the tiny memory model supports making .C','OM files.'#000+ '11058_W_Experimental CheckPointer option not enabled because it is inc'+ - 'omptatible wi','th -Ur option.'#000+ + 'omptatible with -Ur option.'#000+ '11059_E_Unsupported target architecture -P$1, invoke the "fpc" compile'+ 'r driver instead.'#000+ - '11060_E_Feature switches are only supported while compiling the system'+ - ' unit.'#000+ - '11061_N_The selected debug format is not supported by the in','ternal l'+ - 'inker, switching to external linking'#000+ + '11060_E_Feature switches are only supported ','while compiling the syst'+ + 'em unit.'#000+ + '11061_N_The selected debug format is not supported by the internal lin'+ + 'ker, switching to external linking'#000+ '12000_F_Cannot open whole program optimization feedback file "$1"'#000+ - '12001_D_Processing whole program optimization information in wpo feedb'+ - 'ack file "$1"'#000+ - '12002_D_Finished processing the whole program',' optimization informati'+ - 'on in wpo feedback file "$1"'#000+ + '12001_D_Processing whole program opt','imization information in wpo fee'+ + 'dback file "$1"'#000+ + '12002_D_Finished processing the whole program optimization information'+ + ' in wpo feedback file "$1"'#000+ '12003_E_Expected section header, but got "$2" at line $1 of wpo feedba'+ 'ck file'#000+ - '12004_W_No handler registered for whole program optimization section "'+ - '$2" at line $1 of wpo feedback file, ign','oring'#000+ + '12004_W_No handle','r registered for whole program optimization section'+ + ' "$2" at line $1 of wpo feedback file, ignoring'#000+ '12005_D_Found whole program optimization section "$1" with information'+ ' about "$2"'#000+ - '12006_F_The selected whole program optimizations require a previously '+ - 'generated feedback file (use -Fw to specify)'#000+ - '12007_E_No collected information nece','ssary to perform "$1" whole pro'+ - 'gram optimization found'#000+ + '12006_F_The selected whole program optimizations require a ','previousl'+ + 'y generated feedback file (use -Fw to specify)'#000+ + '12007_E_No collected information necessary to perform "$1" whole progr'+ + 'am optimization found'#000+ '12008_F_Specify a whole program optimization feedback file to store th'+ - 'e generated info in (using -FW)'#000+ + 'e generated info in (u','sing -FW)'#000+ '12009_E_Not generating any whole program optimization information, yet'+ - ' a feedback f','ile was specified (using -FW)'#000+ + ' a feedback file was specified (using -FW)'#000+ '12010_E_Not performing any whole program optimizations, yet an input f'+ 'eedback file was specified (using -Fw)'#000+ - '12011_D_Skipping whole program optimization section "$1", because not '+ - 'needed by the requested optimiz','ations'#000+ + '12011_D_','Skipping whole program optimization section "$1", because no'+ + 't needed by the requested optimizations'#000+ '12012_W_Overriding previously read information for "$1" from feedback '+ 'input file using information in section "$2"'#000+ - '12013_E_Cannot extract symbol liveness information from program when s'+ - 'tripping symbols, use -Xs-'#000+ - '12014_E_Cannot extrac','t symbol liveness information from program when'+ - ' when not linking'#000+ + '12013_E_Cannot extract sy','mbol liveness information from program when'+ + ' stripping symbols, use -Xs-'#000+ + '12014_E_Cannot extract symbol liveness information from program when w'+ + 'hen not linking'#000+ '12015_F_Cannot find "$1" or "$2" to extract symbol liveness informatio'+ - 'n from linked program'#000+ + 'n from linke','d program'#000+ '12016_E_Error during reading symbol liveness information produced by "'+ '$1"'#000+ - '12017_F_E','rror executing "$1" (exitcode: $2) to extract symbol inform'+ - 'ation from linked program'#000+ - '12018_E_Collection of symbol liveness information can only help when u'+ - 'sing smart linking, use -CX -XX'#000+ - '12019_E_Cannot create specified whole program optimis','ation feedback '+ - 'file "$1"'#000+ + '12017_F_Error executing "$1" (exitcode: $2) to extract symbol informat'+ + 'ion from linked program'#000+ + '12018_E_Collection of symbol liveness information can only hel','p when'+ + ' using smart linking, use -CX -XX'#000+ + '12019_E_Cannot create specified whole program optimisation feedback fi'+ + 'le "$1"'#000+ '13001_F_Can'#039't find package $1'#000+ '13002_U_PCP file for package $1 found'#000+ '13003_E_Duplicate package $1'#000+ - '13004_E_Unit $1 can not be part of a package'#000+ + '13004_E_Unit $1 can not b','e part of a package'#000+ '13005_N_Unit $1 is implicitely imported into package $2'#000+ - '13006_F_Failed to',' create PCP file $2 for package $1'#000+ + '13006_F_Failed to create PCP file $2 for package $1'#000+ '13007_F_Failed to read PCP file for package $1'#000+ '13008_T_PCP loading $1'#000+ '13009_U_PCP Name: $1'#000+ - '13010_U_PCP Flags: $1'#000+ + '13010_U_PCP Flags: $1',#000+ '13011_U_PCP Crc: $1'#000+ '13012_U_PCP Time: $1'#000+ '13013_U_PCP File too short'#000+ - '13014_U_PCP Invalid Head','er (no PCP at the begin)'#000+ + '13014_U_PCP Invalid Header (no PCP at the begin)'#000+ '13015_U_PCP Invalid Version $1'#000+ '13016_U_PCP is compiled for another processor'#000+ '13017_U_PCP is compiled for another target'#000+ - '13018_U_Writing $1'#000+ + '13','018_U_Writing $1'#000+ '13019_F_Can'#039't Write PCP-File'#000+ '13020_F_Error reading PCP-File'#000+ - '13021_F_Unexpect','ed end of PCP-File'#000+ + '13021_F_Unexpected end of PCP-File'#000+ '13022_F_Invalid PCP-File entry: $1'#000+ '13023_U_Trying to use a unit which was compiled with a different FPU m'+ 'ode'#000+ - '13024_T_Packagesearch: $1'#000+ + '13024_T_Packagesear','ch: $1'#000+ '13025_U_Required package $1'#000+ '13026_U_Contained unit $1'#000+ - '13027_E_Unit $1 is already conta','ined in package $2'#000+ + '13027_E_Unit $1 is already contained in package $2'#000+ '13028_W_Unit $1 is imported from indirectly required package $2'#000+ '13029_U_PPL filename $1'#000+ - '11023_Free Pascal Compiler version $FPCFULLVERSION [$FPCDATE] for $FPC'+ - 'CPU'#010+ + '11023_Free Pascal Compiler version $FPCF','ULLVERSION [$FPCDATE] for $F'+ + 'PCCPU'#010+ 'Copyright (c) 1993-2020 by Florian Klaempfl and others'#000+ - '1102','4_Free Pascal Compiler version $FPCVERSION'#010+ + '11024_Free Pascal Compiler version $FPCVERSION'#010+ #010+ 'Compiler date : $FPCDATE'#010+ 'Compiler CPU target: $FPCCPU'#010+ #010+ - 'Supported targets (targets marked with '#039'{*}'#039' are under develop'+ + 'Supported targets (targets marked with '#039'{*}',#039' are under develop'+ 'ment):'#010+ ' $OSTARGETS'#010+ #010+ 'Supported CPU instruction sets:'#010+ ' $INSTRUCTIONSETS'#010+ #010+ - 'S','upported FPU instruction sets:'#010+ + 'Supported FPU instruction sets:'#010+ ' $FPUINSTRUCTIONSETS'#010+ #010+ 'Supported inline assembler modes:'#010+ ' $ASMMODES'#010+ #010+ 'Recognized compiler and RTL features:'#010+ - ' $FEATURELIST'#010+ + ' $FEATU','RELIST'#010+ #010+ 'Recognized modeswitches:'#010+ ' $MODESWITCHES'#010+ @@ -1409,7 +1413,7 @@ const msgtxt : array[0..000357,1..240] of char=( 'Supported ABI targets:'#010+ ' $ABITARGETS'#010+ #010+ - 'Suppo','rted Optimizations:'#010+ + 'Supported Optimizations:'#010+ ' $OPTIMIZATIONS'#010+ #010+ 'Supported Whole Program Optimizations:'#010+ @@ -1417,407 +1421,405 @@ const msgtxt : array[0..000357,1..240] of char=( ' $WPOPTIMIZATIONS'#010+ #010+ 'Code Generation Backend'#010+ - ' $CODEGENERATIONBACKEND'#010+ + ' $CODEGENERATIONBAC','KEND'#010+ #010+ 'Supported Microcontroller types:$\n $CONTROLLERTYPES$\n'#010+ - 'This program comes under the G','NU General Public Licence'#010+ + 'This program comes under the GNU General Public Licence'#010+ 'For more information read COPYING.v2'#010+ #010+ 'Please report bugs in our bug tracker on:'#010+ - ' https://bugs.freepascal.org'#010+ + ' https://bugs.freepascal.','org'#010+ #010+ 'More information may be found on our WWW pages (including directions'#010+ - 'for mailing lists u','seful for asking questions or discussing potentia'+ - 'l'#010+ + 'for mailing lists useful for asking questions or discussing potential'#010+ 'new features, etc.):'#010+ ' https://www.freepascal.org'#000+ - '11025_F*0*_Only options valid for the default or selected platform are'+ - ' listed.'#010+ - '**0*_Put + after a boolean switch option to e','nable it, - to disable '+ - 'it.'#010+ + '11025_F*0*_Only options valid f','or the default or selected platform a'+ + 're listed.'#010+ + '**0*_Put + after a boolean switch option to enable it, - to disable it'+ + '.'#010+ '**1@_Read compiler options from in addition to the default fpc.'+ 'cfg'#010+ - '**1a_The compiler does not delete the generated assembler file'#010+ + '**1a_The compiler does not delete the generate','d assembler file'#010+ '**2a5_Don'#039't generate Big Obj COFF files for GNU Binutils older tha'+ - 'n 2.25 (Wi','ndows, NativeNT)'#010+ + 'n 2.25 (Windows, NativeNT)'#010+ '**2al_List sourcecode lines in assembler file'#010+ '**2an_List node info in assembler file (-dEXTDEBUG compiler)'#010+ - '**2ao_Add an extra option to external assembler call (ignored for inte'+ - 'rnal)'#010+ - '*L2ap_Use pipes instead of creating temp','orary assembler files'#010+ + '**2ao_Add an extra opti','on to external assembler call (ignored for in'+ + 'ternal)'#010+ + '*L2ap_Use pipes instead of creating temporary assembler files'#010+ '**2ar_List register allocation/release info in assembler file'#010+ '**2at_List temp allocation/release info in assembler file'#010+ - '**1A_Output format:'#010+ + '**1A<','x>_Output format:'#010+ '**2Adefault_Use default assembler'#010+ '3*2Aas_Assemble using GNU AS'#010+ - '3*2Aas-darwi','n_Assemble Darwin Mach-O using GNU GAS'#010+ + '3*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ '3*2Amacho_Mach-O (Darwin, Intel 32 bit) using internal writer'#010+ '8*2Anasm_Assemble using Nasm'#010+ - '8*2Anasmobj_Assemble using Nasm'#010+ + '8*2Anasmobj_Assem','ble using Nasm'#010+ '3*2Anasm_Assemble using Nasm'#010+ '3*2Anasmcoff_COFF (Go32v2) file using Nasm'#010+ - '3*2Ana','smelf_ELF32 (Linux) file using Nasm'#010+ + '3*2Anasmelf_ELF32 (Linux) file using Nasm'#010+ '3*2Anasmwin32_Win32 object file using Nasm'#010+ '3*2Anasmwdosx_Win32/WDOSX object file using Nasm'#010+ - '3*2Anasmdarwin_macho32 object file using Nasm (experimental)'#010+ + '3*2Anasmdarwin_mach','o32 object file using Nasm (experimental)'#010+ '3*2Awasm_Obj file using Wasm (Watcom)'#010+ - '3*2Anasmobj_O','bj file using Nasm'#010+ + '3*2Anasmobj_Obj file using Nasm'#010+ '3*2Amasm_Obj file using Masm (Microsoft)'#010+ '3*2Atasm_Obj file using Tasm (Borland)'#010+ '3*2Aelf_ELF (Linux) using internal writer'#010+ - '3*2Acoff_COFF (Go32v2) using internal writer'#010+ + '3*2Aco','ff_COFF (Go32v2) using internal writer'#010+ '3*2Apecoff_PE-COFF (Win32) using internal writer'#010+ - '3*2Ay','asm_Assemble using Yasm (experimental)'#010+ + '3*2Ayasm_Assemble using Yasm (experimental)'#010+ '4*2Aas_Assemble using GNU AS'#010+ '4*2Agas_Assemble using GNU GAS'#010+ - '4*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ + '4*2Aas-darwin_Assemble Darwin Mach-O using GNU G','AS'#010+ '4*2Amasm_Win64 object file using ml64 (Microsoft)'#010+ - '4*2Apecoff_PE-COFF (Win64) using interna','l writer'#010+ + '4*2Apecoff_PE-COFF (Win64) using internal writer'#010+ '4*2Aelf_ELF (Linux-64bit) using internal writer'#010+ '4*2Ayasm_Assemble using Yasm (experimental)'#010+ '4*2Anasm_Assemble using Nasm (experimental)'#010+ - '4*2Anasmwin64_Assemble Win64 object file using Nasm (experimental)'#010+ - '4*2Anasmelf_Assemble Linux-6','4bit object file using Nasm (experimenta'+ - 'l)'#010+ + '4*','2Anasmwin64_Assemble Win64 object file using Nasm (experimental)'#010+ + '4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental)'+ + #010+ '4*2Anasmdarwin_Assemble darwin macho64 object file using Nasm (experim'+ 'ental)'#010+ - '6*2Aas_Unix o-file using GNU AS'#010+ + '6*2Aas_Unix o-file using GN','U AS'#010+ '6*2Agas_GNU Motorola assembler'#010+ '6*2Amit_MIT Syntax (old GAS)'#010+ - '6*2Amot_Standard Motorola as','sembler'#010+ + '6*2Amot_Standard Motorola assembler'#010+ '6*2Avasm_Use vasm to assemble'#010+ 'A*2Aas_Assemble using GNU AS'#010+ 'P*2Aas_Assemble using GNU AS'#010+ 'S*2Aas_Assemble using GNU AS'#010+ - 'Z*2Asdcc-sdasz80_Assemble using SDCC-SDASZ80'#010+ + 'Z*2Asdcc-sdasz80_Assem','ble using SDCC-SDASZ80'#010+ 'Z*2Az80asm_Assemble using z80asm'#010+ '**1b_Generate browser info'#010+ - '**2bl_Gene','rate local symbol info'#010+ + '**2bl_Generate local symbol info'#010+ '**1B_Build all modules'#010+ '**1C_Code generation options:'#010+ '**2C3_Turn on ieee error checking for constants'#010+ - '**2Ca_Select ABI; see fpc -i or fpc -ia for possible values'#010+ - '**2Cb_Generate code for a big-endian variant of th','e target architect'+ - 'ure'#010+ + '**2Ca_Select ABI;',' see fpc -i or fpc -ia for possible values'#010+ + '**2Cb_Generate code for a big-endian variant of the target architectur'+ + 'e'#010+ '**2Cc_Set default calling convention to '#010+ '**2CD_Create also dynamic library (not supported)'#010+ - '**2Ce_Compilation with emulated floating point opcodes'#010+ + '**2Ce_Compilation with emula','ted floating point opcodes'#010+ '**2CE_Generate FPU code which can raise exceptions'#010+ - '**2Cf_Select',' fpu instruction set to use; see fpc -i or fpc -if fo'+ - 'r possible values'#010+ + '**2Cf_Select fpu instruction set to use; see fpc -i or fpc -if for '+ + 'possible values'#010+ '**2CF_Minimal floating point constant precision (default, 32, 64)'#010+ - '**2Cg_Generate PIC code'#010+ + '**2Cg_G','enerate PIC code'#010+ '**2Ch[,m]_ bytes min heap size (between 1023 and 67107840) and o'+ - 'ptiona','lly [m] max heap size'#010+ + 'ptionally [m] max heap size'#010+ '**2Ci_IO-checking'#010+ 'A*2CI_Select instruction set on ARM: ARM or THUMB'#010+ 'L*2Cl_LLVM code generation options'#010+ - 'L*3Clflto_Enable Link-time optimisation (needed both when compiling un'+ - 'its and programs/libraries)'#010+ - 'L*3Clfltono','system_Disable LTO for the system unit (needed with at le'+ - 'ast Xcode 10.2 and earlier due to linker bugs)'#010+ - 'L*3Clv_LLVM target version: Xcode-10.1, 7.0, 8.0, .., 10.0'#010+ + 'L*3Clflto_Enable',' Link-time optimisation (needed both when compiling '+ + 'units and programs/libraries)'#010+ + 'L*3Clfltonosystem_Disable LTO for the system unit (needed with at leas'+ + 't Xcode 10.2 and earlier due to linker bugs)'#010+ + 'L*3Clv_LLVM target version: Xcode-10.1, ','7.0, 8.0, .., 10.0'#010+ '**2Cn_Omit linking stage'#010+ 'P*2CN_Generate nil-pointer checks (AIX-only)'#010+ - '**2C','o_Check overflow of integer operations'#010+ + '**2Co_Check overflow of integer operations'#010+ '**2CO_Check for possible overflow of integer operations'#010+ - '**2Cp_Select instruction set; see fpc -i or fpc -ic for possible va'+ - 'lues'#010+ + '**2Cp_Select instruction set; see fpc -i or fpc -','ic for possible '+ + 'values'#010+ '**2CP=_ packing settings'#010+ - '**3CPPACKSET=_ set allocation: 0',', 1 or DEFAULT or NORMAL, 2, '+ - '4 and 8'#010+ + '**3CPPACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, 4 '+ + 'and 8'#010+ '**3CPPACKENUM=_ enum packing: 0, 1, 2 and 4 or DEFAULT or NORMA'+ 'L'#010+ - '**3CPPACKRECORD=_ record packing: 0 or DEFAULT or NORMAL, 1, 2,'+ - ' 4, 8, 16 and 32'#010+ + '**3CPPACKRECORD=_ record packin','g: 0 or DEFAULT or NORMAL, 1, '+ + '2, 4, 8, 16 and 32'#010+ '**2Cr_Range checking'#010+ - '**2CR_Verify object met','hod call validity'#010+ + '**2CR_Verify object method call validity'#010+ '**2Cs_Set stack checking size to '#010+ '**2Ct_Stack checking (for testing only, see manual)'#010+ - '8*2CT_Target-specific code generation options'#010+ + '8*2CT_Target-specific code generat','ion options'#010+ '3*2CT_Target-specific code generation options'#010+ - '4*2CT_Target-specific code ge','neration options'#010+ + '4*2CT_Target-specific code generation options'#010+ 'p*2CT_Target-specific code generation options'#010+ 'P*2CT_Target-specific code generation options'#010+ - 'J*2CT_Target-specific code generation options'#010+ + 'J*2CT_Target-specific code ge','neration options'#010+ 'A*2CT_Target-specific code generation options'#010+ - 'p*3CTsmalltoc_ Generate sma','ller TOCs at the expense of execution spe'+ - 'ed (AIX)'#010+ + 'p*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ + ' (AIX)'#010+ 'P*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ ' (AIX)'#010+ - 'J*3CTautogetterprefix=X_ Automatically create getters for properties '+ - 'with prefix X (empty string disables)'#010+ - 'J*3CT','autosetterprefix=X_ Automatically create setters for propertie'+ + 'J*3CTautogetterprefi','x=X_ Automatically create getters for propertie'+ 's with prefix X (empty string disables)'#010+ - '8*3CTcld_ Emit a CLD instruction before using the x86 '+ - 'string instructions'#010+ - '3*3CTcld_ Emit a CLD instructio','n before using the x8'+ + 'J*3CTautosetterprefix=X_ Automatically create setters for properties '+ + 'with prefix X (empty string disables)'#010+ + '8*3CTcld_ Emit a CLD instruc','tion before using the x8'+ '6 string instructions'#010+ + '3*3CTcld_ Emit a CLD instruction before using the x86 '+ + 'string instructions'#010+ '4*3CTcld_ Emit a CLD instruction before using the x86 '+ 'string instructions'#010+ - '8*3CTfarprocspushoddbp_ Increment BP before pushing it in the pr'+ - 'ologue of far functions'#010+ - 'J*3CTcompacti','ntarrayinit_ Generate smaller (but potentially slower) '+ - 'code for initializing integer array constants'#010+ - 'J*3CTenumfieldinit_ Initialize enumeration fields in constructor'+ - 's to enumtype(0), after calling inherited constructors'#010+ - 'J*3CTinitlocal','s_ Initialize local variables that trigger a '+ - 'JVM bytecode verification error if used uninitialized (slows down code'+ - ')'#010+ - 'J*3CTlowercaseprocstart_ Lowercase the first character of procedure/f'+ - 'unction/method names'#010+ - 'A*3CTthumbinterworking_',' Generate Thumb interworking-safe code if pos'+ - 'sible'#010+ + '8*3CTfarprocsp','ushoddbp_ Increment BP before pushing it in the '+ + 'prologue of far functions'#010+ + 'J*3CTcompactintarrayinit_ Generate smaller (but potentially slower) co'+ + 'de for initializing integer array constants'#010+ + 'J*3CTenumfieldinit_ Initialize enumerati','on fields in construct'+ + 'ors to enumtype(0), after calling inherited constructors'#010+ + 'J*3CTinitlocals_ Initialize local variables that trigger a JV'+ + 'M bytecode verification error if used uninitialized (slows down code)'#010+ + 'J*3CTlowercaseprocsta','rt_ Lowercase the first character of procedure'+ + '/function/method names'#010+ + 'A*3CTthumbinterworking_ Generate Thumb interworking-safe code if possi'+ + 'ble'#010+ 'J*2Cv_Var/out parameter copy-out checking'#010+ 'A*2CV_Set section threadvar model to '#010+ - '**2CX_Create also smartlinked library'#010+ + '**2CX_Crea','te also smartlinked library'#010+ '**1d_Defines the symbol '#010+ '**1D_Generate a DEF file'#010+ - '**2Dd_','Set description to '#010+ + '**2Dd_Set description to '#010+ '**2Dv_Set DLL version to '#010+ '*O2Dw_PM application'#010+ '**1e_Set path to executable'#010+ '**1E_Same as -Cn'#010+ '**1fPIC_Same as -Cg'#010+ - '**1F_Set file names and paths:'#010+ - '**2Fa[,y]_(for a program) load units and [y] before use','s is p'+ - 'arsed'#010+ + '**1','F_Set file names and paths:'#010+ + '**2Fa[,y]_(for a program) load units and [y] before uses is par'+ + 'sed'#010+ '**2Fc_Set input codepage to '#010+ '**2FC_Set RC compiler binary name to '#010+ '**2Fd_Disable the compiler'#039's internal directory cache'#010+ - '**2FD_Set the directory where to search for compiler utilities'#010+ - '**2Fe_Redirect error outpu','t to '#010+ + '**','2FD_Set the directory where to search for compiler utilities'#010+ + '**2Fe_Redirect error output to '#010+ '**2FE_Set exe/unit output path to '#010+ '**2Ff_Add to framework path (Darwin only), or set IDF path to <'+ 'x> (Xtensa-FreeRTOS)'#010+ - '**2FF_Use fpcres as RC to RES compiler instead of windres or gorc'#010+ - '**2Fi_Add to include path'#010, + '**2FF_','Use fpcres as RC to RES compiler instead of windres or gorc'#010+ + '**2Fi_Add to include path'#010+ '**2Fl_Add to library path'#010+ '**2FL_Use as dynamic linker'#010+ '**2Fm_Load unicode conversion table from .txt in the compiler di'+ 'r'#010+ - '**2FM_Set the directory where to search for unicode binary files'#010+ - '**2FN_Add to list of defa','ult unit scopes (namespaces)'#010+ + '**2FM_Set the directory where to search for unicode binary files'#010+ + '**2FN_Add to list of default unit scopes (namespaces)'#010+ '**2Fo_Add to object path'#010+ '**2Fr_Load error message file '#010+ '**2FR_Set resource (.res) linker to '#010+ - '**2Fu_Add to unit path'#010+ + '**2Fu<','x>_Add to unit path'#010+ '**2FU_Set unit output path to , overrides -FE'#010+ - '**2FW_Store ge','nerated whole-program optimization feedback in '#010+ + '**2FW_Store generated whole-program optimization feedback in '#010+ '**2Fw_Load previously stored whole-program optimization feedback fr'+ 'om '#010+ - '*g1g_Generate debug information (default format for target)'#010+ - '*g2gc_Generate checks for pointers (experimental, on','ly available on '+ - 'some targets, might generate false positive)'#010+ + '*g1g_Generate debug',' information (default format for target)'#010+ + '*g2gc_Generate checks for pointers (experimental, only available on so'+ + 'me targets, might generate false positive)'#010+ '*g2gh_Use heaptrace unit (for memory leak/corruption debugging)'#010+ - '*g2gl_Use line info unit (show more info with backtraces)'#010+ - '*g2gm_Generate Microsoft CodeView debug information (expe','rimental)'#010+ + '*g2gl_Use line info un','it (show more info with backtraces)'#010+ + '*g2gm_Generate Microsoft CodeView debug information (experimental)'#010+ '*g2go_Set debug information options'#010+ '*g3godwarfsets_ Enable DWARF '#039'set'#039' type debug information (bre'+ 'aks gdb < 6.5)'#010+ - '*g3gostabsabsincludes_ Store absolute/full include file paths in Stabs'+ - #010+ - '*g3godwarfmethodclassprefix_ Prefix method ','names in DWARF with class'+ - ' name'#010+ + '*g3gostabsabsincludes','_ Store absolute/full include file paths in Sta'+ + 'bs'#010+ + '*g3godwarfmethodclassprefix_ Prefix method names in DWARF with class n'+ + 'ame'#010+ '*g3godwarfcpp_ Simulate C++ debug information in DWARF'#010+ - '*g3godwarfomflinnum_ Generate line number information in OMF LINNUM re'+ - 'cords in MS LINK format in addition to the DWARF debug information (Op'+ - 'en Watcom Debu','gger/Linker compatibility)'#010+ + '*g3godwarfomflinnum_ Generate line number information in OMF ','LINNUM '+ + 'records in MS LINK format in addition to the DWARF debug information ('+ + 'Open Watcom Debugger/Linker compatibility)'#010+ '*g2gp_Preserve case in stabs symbol names'#010+ '*g2gs_Generate Stabs debug information'#010+ - '*g2gt_Trash local variables (to detect uninitialized uses; multiple '#039+ - 't'#039' changes the trashing value)'#010+ - '*g2gv_Generates programs traceab','le with Valgrind'#010+ + '*g2gt_Trash local variables (to detect ','uninitialized uses; multiple '+ + #039't'#039' changes the trashing value)'#010+ + '*g2gv_Generates programs traceable with Valgrind'#010+ '*g2gw_Generate DWARFv2 debug information (same as -gw2)'#010+ '*g2gw2_Generate DWARFv2 debug information'#010+ - '*g2gw3_Generate DWARFv3 debug information'#010+ + '*g2gw3_Generate DWARFv3 debug in','formation'#010+ '*g2gw4_Generate DWARFv4 debug information (experimental)'#010+ '**1i_Information'#010+ - '**2iD_Ret','urn compiler date'#010+ + '**2iD_Return compiler date'#010+ '**2iSO_Return compiler OS'#010+ '**2iSP_Return compiler host processor'#010+ '**2iTO_Return target OS'#010+ '**2iTP_Return target processor'#010+ - '**2iV_Return short compiler version'#010+ + '**2iV_Retu','rn short compiler version'#010+ '**2iW_Return full compiler version'#010+ - '**2ia_Return list of supported A','BI targets'#010+ + '**2ia_Return list of supported ABI targets'#010+ '**2ib_Return the used code generation backend type'#010+ '**2ic_Return list of supported CPU instruction sets'#010+ - '**2if_Return list of supported FPU instruction sets'#010+ + '**2if_Return list of supported FP','U instruction sets'#010+ '**2ii_Return list of supported inline assembler modes'#010+ - '**2im_Return list of',' supported modeswitches'#010+ + '**2im_Return list of supported modeswitches'#010+ '**2io_Return list of supported optimizations'#010+ '**2ir_Return list of recognized compiler and RTL features'#010+ - '**2it_Return list of supported targets'#010+ + '**2it_Return list of',' supported targets'#010+ '**2iu_Return list of supported microcontroller types'#010+ - '**2iw_Return list of ','supported whole program optimizations'#010+ + '**2iw_Return list of supported whole program optimizations'#010+ '**1I_Add to include path'#010+ '**1k_Pass to the linker'#010+ '**1l_Write logo'#010+ - '**1M_Set language mode to / enable modeswitch (see option -'+ - 'im)'#010+ + '**1M_Set language mode to <','x> / enable modeswitch (see option'+ + ' -im)'#010+ '**2Mfpc_Free Pascal dialect (default)'#010+ - '**2Mobjfpc_','FPC mode with Object Pascal support'#010+ + '**2Mobjfpc_FPC mode with Object Pascal support'#010+ '**2Mdelphi_Delphi 7 compatibility mode'#010+ '**2Mtp_TP/BP 7.0 compatibility mode'#010+ - '**2Mmacpas_Macintosh Pascal dialects compatibility mode'#010+ + '**2Mmacpas_Macintosh Pascal dialects',' compatibility mode'#010+ '**2Miso_ISO 7185 mode'#010+ '**2Mextendedpascal_ISO 10206 mode'#010+ - '**2Mdelphiunicode','_Delphi 2009 and later compatibility mode'#010+ + '**2Mdelphiunicode_Delphi 2009 and later compatibility mode'#010+ '**2*_Each mode (as listed above) enables its default set of modeswitch'+ 'es.'#010+ - '**2*_Other modeswitches are disabled and need to be enabled one by ano'+ - 'ther.'#010+ - '**1M-_Disable modeswitch (see option -im)',#010+ + '**2*_Other modeswitches are dis','abled and need to be enabled one by a'+ + 'nother.'#010+ + '**1M-_Disable modeswitch (see option -im)'#010+ '**1n_Do not read the default config files'#010+ '**1o_Change the name of the executable produced to '#010+ '**1O_Optimizations:'#010+ - '**2O-_Disable optimizations'#010+ + '**2O-_Disable optimizat','ions'#010+ '**2O1_Level 1 optimizations (quick and debugger friendly)'#010+ - '**2O2_Level 2 optimizations (-','O1 + quick optimizations)'#010+ + '**2O2_Level 2 optimizations (-O1 + quick optimizations)'#010+ '**2O3_Level 3 optimizations (-O2 + slow optimizations)'#010+ - '**2O4_Level 4 optimizations (-O3 + optimizations which might have unex'+ - 'pected side effects)'#010+ + '**2O4_Level 4 optimizations (-O3 + optimizations which might have ','un'+ + 'expected side effects)'#010+ '**2Oa=_Set alignment'#010+ - '**2Oo[NO]_Enable or disable optimizati','ons; see fpc -i or fpc -io '+ - 'for possible values'#010+ + '**2Oo[NO]_Enable or disable optimizations; see fpc -i or fpc -io fo'+ + 'r possible values'#010+ '**2Op_Set target cpu for optimizing; see fpc -i or fpc -ic for poss'+ 'ible values'#010+ - '**2OW_Generate whole-program optimization feedback for optimization'+ - ' ; see fpc -i or fpc -iw for possible ','values'#010+ + '**2OW_Generate ','whole-program optimization feedback for optimizati'+ + 'on ; see fpc -i or fpc -iw for possible values'#010+ '**2Ow_Perform whole-program optimization ; see fpc -i or fpc -iw'+ ' for possible values'#010+ '**2Os_Optimize for size rather than speed'#010+ - '**1pg_Generate profile code for gprof (defines FPC_PROFILE)'#010+ - 'F*1P_Target CPU / compiler related op','tions:'#010+ + '**1pg_G','enerate profile code for gprof (defines FPC_PROFILE)'#010+ + 'F*1P_Target CPU / compiler related options:'#010+ 'F*2PB_Show default compiler binary'#010+ 'F*2PP_Show default target cpu'#010+ 'F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipse'+ - 'l,powerpc,powerpc64,sparc,x86_64)'#010+ + 'l,pow','erpc,powerpc64,sparc,x86_64)'#010+ '**1R_Assembler reading style:'#010+ - '**2Rdefault_Use default assembl','er for target'#010+ + '**2Rdefault_Use default assembler for target'#010+ '3*2Ratt_Read AT&T style assembler'#010+ '3*2Rintel_Read Intel style assembler'#010+ '4*2Ratt_Read AT&T style assembler'#010+ - '4*2Rintel_Read Intel style assembler'#010+ + '4*2Rintel_Read Intel style a','ssembler'#010+ '8*2Ratt_Read AT&T style assembler'#010+ '8*2Rintel_Read Intel style assembler'#010+ - '6*2RMOT_Read ','Motorola style assembler'#010+ + '6*2RMOT_Read Motorola style assembler'#010+ '**1S_Syntax options:'#010+ '**2S2_Same as -Mobjfpc'#010+ '**2Sc_Support operators like C (*=,+=,/= and -=)'#010+ '**2Sa_Turn on assertions'#010+ - '**2Sd_Same as -Mdelphi'#010+ + '*','*2Sd_Same as -Mdelphi'#010+ '**2Se_Error options. is a combination of the following:'#010+ - '**3*_',' : Compiler halts after the errors (default is 1)'#010+ + '**3*_ : Compiler halts after the errors (default is 1)'#010+ '**3*_w : Compiler also halts after warnings'#010+ '**3*_n : Compiler also halts after notes'#010+ - '**3*_h : Compiler also halts after hints'#010+ - '**2Sf_Enable certain features in compiler and RTL; see fpc -','i or fpc'+ - ' -ir for possible values)'#010+ + '**3*_h :',' Compiler also halts after hints'#010+ + '**2Sf_Enable certain features in compiler and RTL; see fpc -i or fpc -'+ + 'ir for possible values)'#010+ '**2Sg_Enable LABEL and GOTO (default in -Mtp and -Mdelphi)'#010+ - '**2Sh_Use reference counted strings (ansistring by default) instead of'+ - ' shortstrings'#010+ - '**2Si_Turn on inlining of procedures/functions declared as "inl','ine"'#010+ + '**2Sh_Use reference counted strings (ansistring by def','ault) instead '+ + 'of shortstrings'#010+ + '**2Si_Turn on inlining of procedures/functions declared as "inline"'#010+ '**2Sj_Allows typed constants to be writeable (default in all modes)'#010+ '**2Sk_Load fpcylix unit'#010+ '**2SI_Set interface style to '#010+ - '**3SIcom_COM compatible interface (default)'#010+ + '**3SIcom_COM c','ompatible interface (default)'#010+ '**3SIcorba_CORBA compatible interface'#010+ - '**2Sm_Support macros like',' C (global)'#010+ + '**2Sm_Support macros like C (global)'#010+ '**2So_Same as -Mtp'#010+ '**2Sr_Transparent file names in ISO mode'#010+ '**2Ss_Constructor name must be init (destructor must be done)'#010+ - '**2Sv_Support vector processing (use CPU vector extensions if availabl'+ - 'e)'#010+ - '**2Sx_Enable exception keywords (','default in Delphi/ObjFPC modes)'#010+ + '**2Sv_Support',' vector processing (use CPU vector extensions if availa'+ + 'ble)'#010+ + '**2Sx_Enable exception keywords (default in Delphi/ObjFPC modes)'#010+ '**2Sy_@ returns a typed pointer, same as $T+'#010+ '**1s_Do not call assembler and linker'#010+ - '**2sh_Generate script to link on host'#010+ + '**2sh_Generate script t','o link on host'#010+ '**2st_Generate script to link on target'#010+ - '**2sr_Skip register allocation phase (','use with -alr)'#010+ + '**2sr_Skip register allocation phase (use with -alr)'#010+ '**1T_Target operating system:'#010+ '3*2Tandroid_Android'#010+ '3*2Taros_AROS'#010+ '3*2Tbeos_BeOS'#010+ '3*2Tdarwin_Darwin/Mac OS X'#010+ '3*2Tembedded_Embedded'#010+ - '3*2Temx_OS/2 via EMX (including EMX/RSX extender)'#010+ + '3*','2Temx_OS/2 via EMX (including EMX/RSX extender)'#010+ '3*2Tfreebsd_FreeBSD'#010+ - '3*2Tgo32v2_Version 2 of D','J Delorie DOS extender'#010+ + '3*2Tgo32v2_Version 2 of DJ Delorie DOS extender'#010+ '3*2Thaiku_Haiku'#010+ '3*2Tiphonesim_iPhoneSimulator from iOS SDK 3.2+ (older versions: -Tdar'+ 'win)'#010+ '3*2Tlinux_Linux'#010+ - '3*2Tnativent_Native NT API (experimental)'#010+ + '3*2Tnativent_Nati','ve NT API (experimental)'#010+ '3*2Tnetbsd_NetBSD'#010+ '3*2Tnetware_Novell Netware Module (clib)'#010+ - '3*2Tnetwl','ibc_Novell Netware Module (libc)'#010+ + '3*2Tnetwlibc_Novell Netware Module (libc)'#010+ '3*2Topenbsd_OpenBSD'#010+ '3*2Tos2_OS/2 / eComStation'#010+ '3*2Tsymbian_Symbian OS'#010+ '3*2Tsolaris_Solaris'#010+ - '3*2Twatcom_Watcom compatible DOS extender'#010+ + '3*2Twatcom_Watcom compat','ible DOS extender'#010+ '3*2Twdosx_WDOSX DOS extender'#010+ '3*2Twin32_Windows 32 Bit'#010+ - '3*2Twince_Windows CE'#010, + '3*2Twince_Windows CE'#010+ '4*2Tandroid_Android'#010+ '4*2Taros_AROS'#010+ '4*2Tdarwin_Darwin/Mac OS X'#010+ '4*2Tdragonfly_DragonFly BSD'#010+ '4*2Tembedded_Embedded'#010+ '4*2Tfreebsd_FreeBSD'#010+ - '4*2Thaiku_Haiku'#010+ + '4*2Thaiku_Haiku'#010, '4*2Tiphonesim_iPhoneSimulator'#010+ '4*2Tlinux_Linux'#010+ '4*2Tnetbsd_NetBSD'#010+ '4*2Topenbsd_OpenBSD'#010+ - '4*2Tsolar','is_Solaris'#010+ + '4*2Tsolaris_Solaris'#010+ '4*2Twin64_Win64 (64 bit Windows systems)'#010+ '6*2Tamiga_Commodore Amiga'#010+ '6*2Tatari_Atari ST/STe/TT'#010+ '6*2Tembedded_Embedded'#010+ '6*2Tlinux_Linux'#010+ - '6*2Tnetbsd_NetBSD'#010+ + '6*2Tn','etbsd_NetBSD'#010+ '6*2Tmacosclassic_Classic Mac OS'#010+ '6*2Tpalmos_PalmOS'#010+ '8*2Tembedded_Embedded'#010+ - '8*2Tmsdo','s_MS-DOS (and compatible)'#010+ + '8*2Tmsdos_MS-DOS (and compatible)'#010+ '8*2Twin16_Windows 16 Bit'#010+ 'A*2Tandroid_Android'#010+ 'A*2Taros_AROS'#010+ 'A*2Tdarwin_Darwin/iPhoneOS/iOS'#010+ 'A*2Tembedded_Embedded'#010+ - 'A*2Tfreertos_FreeRTOS'#010+ + 'A*2Tfreer','tos_FreeRTOS'#010+ 'A*2Tgba_Game Boy Advance'#010+ 'A*2Tlinux_Linux'#010+ 'A*2Tnds_Nintendo DS'#010+ 'A*2Tnetbsd_NetBSD'#010+ - 'A','*2Tpalmos_PalmOS'#010+ + 'A*2Tpalmos_PalmOS'#010+ 'A*2Tsymbian_Symbian'#010+ 'A*2Twince_Windows CE'#010+ 'a*2Tandroid_Android'#010+ 'a*2Tdarwin_Darwin/iOS'#010+ 'a*2Tlinux_Linux'#010+ 'a*2Twin64_Windows 64'#010+ - 'J*2Tandroid_Android'#010+ + 'J*2Tandroi','d_Android'#010+ 'J*2Tjava_Java'#010+ 'm*2Tandroid_Android'#010+ 'm*2Tembedded_Embedded'#010+ 'm*2Tlinux_Linux'#010+ - 'M*2Tembedde','d_Embedded'#010+ + 'M*2Tembedded_Embedded'#010+ 'M*2Tlinux_Linux'#010+ 'P*2Taix_AIX'#010+ 'P*2Tamiga_AmigaOS'#010+ 'P*2Tdarwin_Darwin/Mac OS X'#010+ 'P*2Tembedded_Embedded'#010+ 'P*2Tlinux_Linux'#010+ - 'P*2Tmacosclassic_Classic Mac OS'#010+ + 'P*2Tmacosclassic_Classic ','Mac OS'#010+ 'P*2Tmorphos_MorphOS'#010+ 'P*2Tnetbsd_NetBSD'#010+ 'P*2Twii_Wii'#010+ 'p*2Taix_AIX'#010+ - 'p*2Tdarwin_Darwin/Mac OS',' X'#010+ + 'p*2Tdarwin_Darwin/Mac OS X'#010+ 'p*2Tembedded_Embedded'#010+ 'p*2Tlinux_Linux'#010+ 'R*2Tlinux_Linux'#010+ @@ -1825,162 +1827,160 @@ const msgtxt : array[0..000357,1..240] of char=( 'r*2Tlinux_Linux'#010+ 'r*2Tembedded_Embedded'#010+ 'S*2Tlinux_Linux'#010+ - 'S*2Tsolaris_Solaris'#010+ + 'S*2Tsolaris_So','laris'#010+ 's*2Tlinux_Linux'#010+ 'V*2Tembedded_Embedded'#010+ 'x*2Tembedded_Embedded'#010+ 'x*2Tfreertos_FreeRTOS'#010+ - 'x*2Tl','inux_Linux'#010+ + 'x*2Tlinux_Linux'#010+ 'Z*2Tembedded_Embedded'#010+ 'Z*2Tzxspectrum_ZX Spectrum'#010+ 'Z*2Tmsxdos_MSX-DOS'#010+ '**1u_Undefines the symbol '#010+ '**1U_Unit options:'#010+ - '**2Un_Do not check where the unit name matches the file name'#010+ - '**2Ur_Generate release unit files (never automat','ically recompiled)'#010+ + '**2Un_Do not che','ck where the unit name matches the file name'#010+ + '**2Ur_Generate release unit files (never automatically recompiled)'#010+ '**2Us_Compile a system unit'#010+ '**1v_Be verbose. is a combination of the following letters:'#010+ - '**2*_e : Show errors (default) 0 : Show nothing (except errors)'#010+ - '**2*_w : Show warnings u : Show unit info'#010, + '**2*_e : Show errors (default) ',' 0 : Show nothing (except errors'+ + ')'#010+ + '**2*_w : Show warnings u : Show unit info'#010+ '**2*_n : Show notes t : Show tried/used files'#010+ '**2*_h : Show hints c : Show conditionals'#010+ - '**2*_i : Show general info d : Show debug info'#010+ - '**2*_l : Show linenumbers r : Rhide/GCC compatibil','ity mod'+ - 'e'#010+ + '**2*_i : Show general inf','o d : Show debug info'#010+ + '**2*_l : Show linenumbers r : Rhide/GCC compatibility mode'#010+ '**2*_s : Show time stamps q : Show message numbers'#010+ '**2*_a : Show everything x : Show info about invoked tools'+ #010+ - '**2*_b : Write file names messages p : Write tree.log with parse tre'+ - 'e'#010+ - '**2*_ with full path ',' v : Write fpcdebug.txt with'#010+ + '**2*_','b : Write file names messages p : Write tree.log with parse t'+ + 'ree'#010+ + '**2*_ with full path v : Write fpcdebug.txt with'#010+ '**2*_z : Write output to stderr lots of debugging info'#010+ - '**2*_m, : Do not show messages numbered and '#010+ + '**2*_m, : Do not show messages numbere','d and '#010+ 'F*1V_Append '#039'-'#039' to the used compiler binary name (e.g. f'+ 'or version)'#010+ - '**1W<','x>_Target-specific options (targets)'#010+ + '**1W_Target-specific options (targets)'#010+ '3*2WA_Specify native type application (Windows)'#010+ '4*2WA_Specify native type application (Windows)'#010+ - 'A*2WA_Specify native type application (Windows)'#010+ + 'A*2WA_Specify ','native type application (Windows)'#010+ '3*2Wb_Create a bundle instead of a library (Darwin)'#010+ - 'P*2Wb_C','reate a bundle instead of a library (Darwin)'#010+ + 'P*2Wb_Create a bundle instead of a library (Darwin)'#010+ 'p*2Wb_Create a bundle instead of a library (Darwin)'#010+ - 'a*2Wb_Create a bundle instead of a library (Darwin)'#010+ + 'a*2Wb_Create a bundle instead of a library (Darwin',')'#010+ 'A*2Wb_Create a bundle instead of a library (Darwin)'#010+ - '4*2Wb_Create a bundle instead of a libr','ary (Darwin)'#010+ + '4*2Wb_Create a bundle instead of a library (Darwin)'#010+ '3*2WB_Create a relocatable image (Windows, Symbian)'#010+ '3*2WB_Set image base to (Windows, Symbian)'#010+ - '4*2WB_Create a relocatable image (Windows)'#010+ + '4*2WB_Create a relocatable image',' (Windows)'#010+ '4*2WB_Set image base to (Windows)'#010+ - 'A*2WB_Create a relocatable image (Windows',', Symbian)'#010+ + 'A*2WB_Create a relocatable image (Windows, Symbian)'#010+ 'A*2WB_Set image base to (Windows, Symbian)'#010+ 'Z*2WB_Set image base to (ZX Spectrum)'#010+ - '3*2WC_Specify console type application (EMX, OS/2, Windows)'#010+ + '3*2WC_Specify console type application (E','MX, OS/2, Windows)'#010+ '4*2WC_Specify console type application (Windows)'#010+ - 'A*2WC_Specify console typ','e application (Windows)'#010+ + 'A*2WC_Specify console type application (Windows)'#010+ 'P*2WC_Specify console type application (Classic Mac OS)'#010+ '3*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ - '4*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ - 'A*2WD_Use DEFFILE to export function','s of DLL or EXE (Windows)'#010+ + '4*2WD','_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ + 'A*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ '3*2We_Use external resources (Darwin)'#010+ '4*2We_Use external resources (Darwin)'#010+ 'a*2We_Use external resources (Darwin)'#010+ - 'A*2We_Use external resources (Darwin)'#010+ + 'A*2We_U','se external resources (Darwin)'#010+ 'P*2We_Use external resources (Darwin)'#010+ - 'p*2We_Use external resou','rces (Darwin)'#010+ + 'p*2We_Use external resources (Darwin)'#010+ '3*2WF_Specify full-screen type application (EMX, OS/2)'#010+ '3*2WG_Specify graphic type application (EMX, OS/2, Windows)'#010+ - '4*2WG_Specify graphic type application (Windows)'#010+ + '4*2WG_Specify grap','hic type application (Windows)'#010+ 'A*2WG_Specify graphic type application (Windows)'#010+ - 'P*2WG_Specify',' graphic type application (Classic Mac OS)'#010+ + 'P*2WG_Specify graphic type application (Classic Mac OS)'#010+ '3*2Wi_Use internal resources (Darwin)'#010+ '4*2Wi_Use internal resources (Darwin)'#010+ - 'a*2Wi_Use internal resources (Darwin)'#010+ + 'a*2Wi_Use internal resources',' (Darwin)'#010+ 'A*2Wi_Use internal resources (Darwin)'#010+ 'P*2Wi_Use internal resources (Darwin)'#010+ - 'p*2Wi_U','se internal resources (Darwin)'#010+ + 'p*2Wi_Use internal resources (Darwin)'#010+ '3*2WI_Turn on/off the usage of import sections (Windows)'#010+ '4*2WI_Turn on/off the usage of import sections (Windows)'#010+ - 'A*2WI_Turn on/off the usage of import sections (Windows)'#010+ - '8*2Wh_Use huge code for units (ignored',' for models with CODE in a uni'+ - 'que segment)'#010+ + 'A*','2WI_Turn on/off the usage of import sections (Windows)'#010+ + '8*2Wh_Use huge code for units (ignored for models with CODE in a uniqu'+ + 'e segment)'#010+ '8*2Wm_Set memory model'#010+ '8*3WmTiny_Tiny memory model'#010+ '8*3WmSmall_Small memory model (default)'#010+ - '8*3WmMedium_Medium memory model'#010+ + '8*3WmMediu','m_Medium memory model'#010+ '8*3WmCompact_Compact memory model'#010+ '8*3WmLarge_Large memory model'#010+ - '8*3WmHu','ge_Huge memory model'#010+ + '8*3WmHuge_Huge memory model'#010+ '3*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ - '4*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ - 'n)'#010+ + '4*2WM_Minimum Mac OS X deployment version: 10.4, 1','0.5.1, ... (Dar'+ + 'win)'#010+ 'p*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ - 'n)'#010, + 'n)'#010+ 'P*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ '3*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ - '4*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ - 'A*2WN_Do not generate reloc','ation code, needed for debugging (Windows'+ + '4*2W','N_Do not generate relocation code, needed for debugging (Windows'+ ')'#010+ + 'A*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ 'A*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ - 'm*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ - 'le values'#010+ - 'R*2Wp_Specify the controller type;',' see fpc -i or fpc -iu for poss'+ + 'm*2Wp_Specify the con','troller type; see fpc -i or fpc -iu for poss'+ 'ible values'#010+ + 'R*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ + 'le values'#010+ 'V*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ - 'x*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ - 'le values'#010+ - '3*2WP_Minimum iOS deployment versi','on: 3.0, 5.0.1, ... (iphonesim)'+ - #010+ + 'x*2Wp_Specify the con','troller type; see fpc -i or fpc -iu for poss'+ + 'ible values'#010+ + '3*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (iphonesim)'#010+ '4*2WP_Minimum iOS deployment version: 8.0, 8.0.2, ... (iphonesim)'#010+ - 'a*2WP_Minimum iOS deployment version: 7.0, 7.1.2, ... (Darwin)'#010+ + 'a*2WP_Minimum iOS deployment version: 7.0, ','7.1.2, ... (Darwin)'#010+ 'A*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (Darwin)'#010+ - '3*2WR_G','enerate relocation code (Windows)'#010+ + '3*2WR_Generate relocation code (Windows)'#010+ '4*2WR_Generate relocation code (Windows)'#010+ 'A*2WR_Generate relocation code (Windows)'#010+ - '8*2Wt_Set the target executable format'#010+ + '8*2Wt_Set the target executa','ble format'#010+ '8*3Wtexe_Create a DOS .EXE file (default)'#010+ - '8*3Wtcom_Create a DOS .COM file (require','s tiny memory model)'#010+ + '8*3Wtcom_Create a DOS .COM file (requires tiny memory model)'#010+ 'P*2WT_Specify MPW tool type application (Classic Mac OS)'#010+ '**2WX_Enable executable stack (Linux)'#010+ '**1X_Executable options:'#010+ - '**2X9_Generate linkerscript for GNU Binutils ld older than version 2.1'+ - '9.1 (Linux)'#010+ - '**2Xc_Pass --shar','ed/-dynamic to the linker (BeOS, Darwin, FreeBSD, L'+ - 'inux)'#010+ + '**2X9_','Generate linkerscript for GNU Binutils ld older than version 2'+ + '.19.1 (Linux)'#010+ + '**2Xc_Pass --shared/-dynamic to the linker (BeOS, Darwin, FreeBSD, Lin'+ + 'ux)'#010+ '**2Xd_Do not search default library path (sometimes required for cross'+ - '-compiling when not using -XR)'#010+ + '-compiling when not ','using -XR)'#010+ '**2Xe_Use external linker'#010+ - '**2Xf_Substitute pthread library name for linking (BSD)'#010, + '**2Xf_Substitute pthread library name for linking (BSD)'#010+ '**2Xg_Create debuginfo in a separate file and add a debuglink section '+ 'to executable'#010+ - '**2XD_Try to link units dynamically (defines FPC_LINK_DYNAMIC)'#010+ + '**2XD_Try to link units dynamically (defines FPC_LINK_DYNA','MIC)'#010+ '**2Xi_Use internal linker'#010+ - 'L*2XlS_LLVM utilties suffix (e.g. -7 in case clang is calle','d clan'+ - 'g-7)'#010+ + 'L*2XlS_LLVM utilties suffix (e.g. -7 in case clang is called clang-'+ + '7)'#010+ '**2XLA_Define library substitutions for linking'#010+ '**2XLO_Define order of library linking'#010+ - '**2XLD_Exclude default order of standard libraries'#010+ + '**2XLD_Exclude default order of standard librarie','s'#010+ '**2Xm_Generate link map'#010+ '**2XM_Set the name of the '#039'main'#039' program routine (default i'+ - 's '#039'ma','in'#039')'#010+ + 's '#039'main'#039')'#010+ '**2Xn_Use target system native linker instead of GNU ld (Solaris, AIX)'+ #010+ 'F*2Xp_First search for the compiler binary in the directory '#010+ - '**2XP_Prepend the binutils names with the prefix '#010+ - '**2Xr_Set the linker'#039's rlink-path to <','x> (needed for cross co'+ - 'mpile, see the ld manual for more information) (BeOS, Linux)'#010+ - '**2XR_Prepend to all linker search paths (BeOS, Darwin, FreeBSD'+ - ', Linux, Mac OS, Solaris)'#010+ + '**2X','P_Prepend the binutils names with the prefix '#010+ + '**2Xr_Set the linker'#039's rlink-path to (needed for cross comp'+ + 'ile, see the ld manual for more information) (BeOS, Linux)'#010+ + '**2XR_Prepend to all linker search paths (BeOS, Darwin, ','FreeB'+ + 'SD, Linux, Mac OS, Solaris)'#010+ '**2Xs_Strip all symbols from executable'#010+ - '**2XS_Try to link un','its statically (default, defines FPC_LINK_STATIC'+ - ')'#010+ + '**2XS_Try to link units statically (default, defines FPC_LINK_STATIC)'#010+ '**2Xt_Link with static libraries (-static is passed to linker)'#010+ - '**2Xv_Generate table for Virtual Entry calls'#010+ + '**2Xv_Generate table for Virtual E','ntry calls'#010+ '**2XV_Use VLink as external linker (default on Amiga, MorphOS)'#010+ - '**2XX_Try to ','smartlink units (defines FPC_LINK_SMART)'#010+ + '**2XX_Try to smartlink units (defines FPC_LINK_SMART)'#010+ '**1*_'#010+ '**1?_Show this help'#010+ '**1h_Shows this help without waiting' diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index 280ceee384..6254a43c43 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -685,6 +685,7 @@ interface implementation uses + typinfo, cutils, globals, systems, @@ -2307,7 +2308,7 @@ implementation function is_16_bit_ref(const ref:treference):boolean; var ir,br : Tregister; - isub,bsub : tsubregister; + isub,bsub : cgbase.tsubregister; begin if (ref.index<>NR_NO) and (getregtype(ref.index)=R_MMREGISTER) then exit(false); @@ -2467,15 +2468,15 @@ implementation // ax cx dx bx si di bp sp -- in x86reg.dat // ax cx dx bx sp bp si di -- needed order (0, 1, 2, 3, 6, 7, 5, 4); - maxsupreg: array[tregistertype] of tsuperregister= + maxsupreg: array[cgbase.tregistertype] of cgbase.tsuperregister= {$ifdef x86_64} (0, 16, 9, 8, 32, 32, 8, 0, 0, 0); {$else x86_64} (0, 8, 9, 8, 8, 32, 8, 0, 0, 0); {$endif x86_64} var - rs: tsuperregister; - rt: tregistertype; + rs: cgbase.tsuperregister; + rt: cgbase.tregistertype; begin rs:=getsupreg(r); rt:=getregtype(r); @@ -2532,7 +2533,7 @@ implementation base,index,scalefactor, o : longint; ir,br : Tregister; - isub,bsub : tsubregister; + isub,bsub : cgbase.tsubregister; begin result:=false; ir:=input.ref^.index; @@ -4617,7 +4618,7 @@ implementation end; - function taicpu.is_same_reg_move(regtype: Tregistertype):boolean; + function taicpu.is_same_reg_move(regtype: cgbase.Tregistertype):boolean; begin result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and (regtype = R_INTREGISTER) and @@ -5479,6 +5480,17 @@ implementation InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask; InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask; + if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and + (gas_needsuffix[AsmOp] <> AttSufNONE) and + (not(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples)) then + begin + // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat'); + //InternalError(20210102); + Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type, + std_op2str[AsmOp], + GetEnumName(typeinfo(TAttSuffix), ord(gas_needsuffix[AsmOp])), + GetEnumName(typeinfo(TMemRefSizeInfo), ord(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize))); + end; end; end; diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 262289dc95..30e6a27d07 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1597,9 +1597,12 @@ procedure Tx86Instruction.SetInstructionOpsize; end; end; end - else if not(MemRefSize in [msiMemRegSize]) then + else if + (gas_needsuffix[opcode] = AttSufNone) and + (not(MemRefSize in [msiMemRegSize])) then begin - //bExistMemRef:=false; + // external gnu-assembler: no suffix =>> use instructions.opsize to define memory-reference size + // Tx86Instruction: local variable: operand.opsize for i := 1 to ops do if tx86operand(operands[i]).opr.typ in [OPR_REFERENCE,OPR_LOCAL] then diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index e3dbe66aa6..4b115d933b 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -2344,7 +2344,7 @@ mmxreg,xmmreg \331\2\x0F\x2D\110 KATMAI,SSE,MMX xmmreg,rm32 \333\321\2\x0F\x2A\110 KATMAI,SSE xmmreg,rm64 \333\321\2\x0F\x2A\110 KATMAI,SSE,X86_64 -[CVTSS2SI,cvtss2siX] +[CVTSS2SI] (Ch_Wop2, Ch_Rop1) reg32|64,mem32 \333\320\2\x0F\x2D\110 KATMAI,SSE reg32|64,xmmreg \333\320\2\x0F\x2D\110 KATMAI,SSE @@ -2354,7 +2354,7 @@ reg32|64,xmmreg \333\320\2\x0F\x2D\110 KATMAI,SSE mmxreg,mem64 \331\2\x0F\x2C\110 KATMAI,SSE,MMX mmxreg,xmmreg \331\2\x0F\x2C\110 KATMAI,SSE,MMX -[CVTTSS2SI,cvttss2siX] +[CVTTSS2SI] (Ch_Wop2, Ch_Rop1) reg32|64,mem32 \333\320\2\x0F\x2C\110 KATMAI,SSE reg32|64,xmmreg \333\320\2\x0F\x2C\110 KATMAI,SSE @@ -2866,7 +2866,7 @@ xmmreg,xmmrm \361\2\x0F\x5B\110 WILLAMETTE,SSE2,SM xmmreg,xmmreg \2\x0F\x5A\110 WILLAMETTE,SSE2 ;,SQ xmmreg,mem64 \2\x0F\x5A\110 WILLAMETTE,SSE2 ;,SQ -[CVTSD2SI,cvtsd2siX] +[CVTSD2SI] (Ch_Wop2, Ch_Rop1) reg32,xmmreg \334\2\x0F\x2D\110 WILLAMETTE,SSE2 reg32,mem64 \334\2\x0F\x2D\110 WILLAMETTE,SSE2 @@ -2900,7 +2900,7 @@ xmmreg,xmmrm \361\2\x0F\xE6\110 WILLAMETTE,SSE2,SM (Ch_Wop2, Ch_Rop1) xmmreg,xmmrm \333\2\x0F\x5B\110 WILLAMETTE,SSE2,SM -[CVTTSD2SI,cvttsd2siX] +[CVTTSD2SI] (Ch_Wop2, Ch_Rop1) reg32|64,xmmreg \334\320\2\x0F\x2C\110 WILLAMETTE,SSE2 reg32|64,mem64 \334\320\2\x0F\x2C\110 WILLAMETTE,SSE2 diff --git a/compiler/x86_64/x8664ats.inc b/compiler/x86_64/x8664ats.inc index 65ba2fe8a4..c64c9f9b95 100644 --- a/compiler/x86_64/x8664ats.inc +++ b/compiler/x86_64/x8664ats.inc @@ -411,9 +411,9 @@ attsufNONE, attsufNONE, attsufNONE, attsufINT, -attsufINT, attsufNONE, -attsufINT, +attsufNONE, +attsufNONE, attsufNONE, attsufNONE, attsufNONE, @@ -525,11 +525,6 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, -attsufNONE, -attsufINT, -attsufNONE, -attsufNONE, attsufNONE, attsufNONE, attsufINT, @@ -593,6 +588,11 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, +attsufNONE, attsufINT, attsufNONE, attsufNONE, From 09c009868604cb1a9a065ea9c739a37c41c93923 Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 5 Jan 2021 13:13:43 +0000 Subject: [PATCH 033/116] =?UTF-8?q?--=20R=C3=BCckw=C3=A4rtiges=20Zusammenf?= =?UTF-8?q?=C3=BChren=20von=20r47837=20bis=20r47033=20in=20=C2=BBppcx64.lp?= =?UTF-8?q?i=C2=AB:=20U=20=20=20=20ppcx64.lpi=20--=20Aufzeichnung=20der=20?= =?UTF-8?q?Informationen=20f=C3=BCr=20r=C3=BCckw=C3=A4rtiges=20Zusammenf?= =?UTF-8?q?=C3=BChren=20von=20r47837=20bis=20r47033=20in=20=C2=BBppcx64.lp?= =?UTF-8?q?i=C2=AB:=20=20G=20=20=20ppcx64.lpi=20--=20Entfernung=20der=20Zu?= =?UTF-8?q?sammenf=C3=BChrungsinformationen=20von=20=C2=BBppcx64.lpi=C2=AB?= =?UTF-8?q?:=20=20U=20=20=20ppcx64.lpi?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: branches/tg74/avx512-0037785@48084 - --- compiler/ppcx64.lpi | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index 5da9c79f20..a28f04cf21 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -1,7 +1,7 @@ - + - + @@ -19,30 +19,26 @@ + + + - - + + - - - - - - - - - + + @@ -75,6 +71,7 @@ + From c3b5d0d5d5b522e8d1a594183e2b49dce34decfb Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 5 Jan 2021 13:52:29 +0000 Subject: [PATCH 034/116] * use str(...) instead of typinfo unit git-svn-id: branches/tg74/avx512-0037785@48085 - --- compiler/x86/aasmcpu.pas | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index 6254a43c43..dd53ebbf8a 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -685,7 +685,6 @@ interface implementation uses - typinfo, cutils, globals, systems, @@ -4929,6 +4928,8 @@ implementation ExistsCode337 : boolean; ExistsSSEAVXReg : boolean; + hs1,hs2 : String; + function bitcnt(aValue: int64): integer; var i: integer; @@ -5486,10 +5487,10 @@ implementation begin // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat'); //InternalError(20210102); + Str(gas_needsuffix[AsmOp],hs1); + Str(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize,hs2); Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type, - std_op2str[AsmOp], - GetEnumName(typeinfo(TAttSuffix), ord(gas_needsuffix[AsmOp])), - GetEnumName(typeinfo(TMemRefSizeInfo), ord(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize))); + std_op2str[AsmOp],hs1,hs2); end; end; end; From 64e796ace2f58eda26c7c732c8d592029f5cf297 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 12 Jan 2021 09:47:18 +0000 Subject: [PATCH 035/116] cleanup bugfix 0037785 git-svn-id: branches/tg74/avx512-0037785@48145 - --- compiler/x86/aasmcpu.pas | 8 +++++++- compiler/x86/rax86.pas | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index fb2384c25f..c1b37e3f32 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -4910,6 +4910,7 @@ implementation var AsmOp: TasmOp; i,j: longint; + iCntOpcodeValError: longint; insentry : PInsEntry; MRefInfo: TMemRefSizeInfo; @@ -4971,6 +4972,7 @@ implementation new(InsTabMemRefSizeInfoCache); FillChar(InsTabMemRefSizeInfoCache^,sizeof(TInsTabMemRefSizeInfoCache),0); + iCntOpcodeValError := 0; for AsmOp := low(TAsmOp) to high(TAsmOp) do begin i := InsTabCache^[AsmOp]; @@ -5506,7 +5508,8 @@ implementation (not(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples)) then begin // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat'); - //InternalError(20210102); + + inc(iCntOpcodeValError); Str(gas_needsuffix[AsmOp],hs1); Str(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize,hs2); Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type, @@ -5515,6 +5518,9 @@ implementation end; end; + if iCntOpcodeValError > 0 then + InternalError(2021011201); + for AsmOp := low(TAsmOp) to high(TAsmOp) do begin diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 1e4eccddf2..5f06215607 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1682,8 +1682,8 @@ begin ; end; end; - A_MOVSS, - A_VMOVSS, + //A_MOVSS, + //A_VMOVSS, A_MOVD : { movd is a move from a mmx register to a 32 bit register or memory, so no opsize is correct here PM } exit; From db2051e2d2c07c5190c93d7f19409b2eec5c11c3 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 12 Jan 2021 10:57:15 +0000 Subject: [PATCH 036/116] bugfix testcases 0037785 git-svn-id: branches/tg74/avx512-0037785@48146 - --- tests/utils/avx/avxopcodes.pas | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index ad34accb74..9915b8d80a 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -101,6 +101,23 @@ begin FOpCodeList.Add('COMISS,1,1,0,XMMREG,XMMREG,,,'); FOpCodeList.Add('COMISS,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('cvtsd2si,1,1,0,REG32,MEM64,,'); + FOpCodeList.Add('cvtsd2si,1,1,0,REG32,XMMREG_ER,,'); + FOpCodeList.Add('cvtsd2si,1,1,0,REG64,MEM64,,'); + FOpCodeList.Add('cvtsd2si,1,1,0,REG64,XMMREG_ER,,'); + FOpCodeList.Add('cvtss2si,1,1,0,REG32,MEM32,,'); + FOpCodeList.Add('cvtss2si,1,1,0,REG32,XMMREG_ER,,'); + FOpCodeList.Add('cvtss2si,1,1,0,REG64,MEM32,,'); + FOpCodeList.Add('cvtss2si,1,1,0,REG64,XMMREG_ER,,'); + FOpCodeList.Add('cvttsd2si,1,1,0,REG32,MEM64,,'); + FOpCodeList.Add('cvttsd2si,1,1,0,REG32,XMMREG_SAE,,'); + FOpCodeList.Add('cvttsd2si,1,1,0,REG64,MEM64,,'); + FOpCodeList.Add('cvttsd2si,1,1,0,REG64,XMMREG_SAE,,'); + FOpCodeList.Add('cvttss2si,1,1,0,REG32,MEM32,,'); + FOpCodeList.Add('cvttss2si,1,1,0,REG32,XMMREG_SAE,,'); + FOpCodeList.Add('cvttss2si,1,1,0,REG64,MEM32,,'); + FOpCodeList.Add('cvttss2si,1,1,0,REG64,XMMREG_SAE,,'); + FOpCodeList.Add('DIVSS,1,1,0,XMMREG,XMMREG,,,'); FOpCodeList.Add('DIVSS,1,1,0,XMMREG,MEM32,,,'); @@ -109,6 +126,10 @@ begin FOpCodeList.Add('MINSS,1,1,0,XMMREG,XMMREG,,,'); FOpCodeList.Add('MINSS,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('MOVSS,1,1,0,XMMREG,XMMREG,,,'); + FOpCodeList.Add('MOVSS,1,1,0,XMMREG,MEM32,,,'); + FOpCodeList.Add('MOVSS,1,1,0,MEM32,XMMREG,,,'); + FOpCodeList.Add('MULSS,1,1,0,XMMREG,XMMREG,,,'); FOpCodeList.Add('MULSS,1,1,0,XMMREG,MEM32,,,'); @@ -943,7 +964,6 @@ begin FOpCodeList.Add('vpinsrb,1,1,1,XMMREG,XMMREG,REG32,IMM8'); FOpCodeList.Add('vpinsrb,1,1,1,XMMREG,XMMREG,MEM8,IMM8'); FOpCodeList.Add('vpinsrd,1,1,1,XMMREG,XMMREG,RM32,IMM8'); - FOpCodeList.Add('vpinsrq,1,1,1,XMMREG,XMMREG,RM64,IMM8'); FOpCodeList.Add('vpinsrw,1,1,1,XMMREG,XMMREG,MEM16,IMM8'); FOpCodeList.Add('vpinsrw,1,1,1,XMMREG,XMMREG,REG32,IMM8'); FOpCodeList.Add('vpmaddubsw,1,1,1,XMMREG_MZ,XMMREG,XMMRM,'); From 7a536df60e1acc939157b2608c7a68f33223c9b4 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 12 Jan 2021 11:01:31 +0000 Subject: [PATCH 037/116] avxtestgenerator add attsuffix in 'opcode-memrefsize-state - list' (command-line option '-l') git-svn-id: branches/tg74/avx512-0037785@48147 - --- tests/utils/avx/asmtestgenerator.pas | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 055aa37c72..21423df5ff 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -108,6 +108,7 @@ uses SysUtils, Dialogs, typinfo; type TAsmOp={$i ../../../compiler/x86_64/x8664op.inc} + TAttSuffix = (AttSufNONE,AttSufINT,AttSufFPU,AttSufFPUint,AttSufINTdual,AttSufMM,AttSufMMX,AttSufMMS); TMemRefSizeInfo = (msiUnknown, msiUnsupported, msiNoSize, msiNoMemRef, msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, @@ -148,6 +149,7 @@ type const instabentries = {$i ../../../compiler/x86_64/x8664nop.inc} + gas_needsuffix:array[tasmop] of TAttSuffix={$i ../../../compiler/x86_64/x8664ats.inc} MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, @@ -4072,6 +4074,7 @@ end; class procedure TAsmTestGenerator.ListMemRefState; var i: integer; + sGasSufffix: string; mrsize: TMemRefSizeInfo; opcode: tasmop; sl: TStringList; @@ -4090,7 +4093,13 @@ begin for opcode:=low(tasmop) to high(tasmop) do begin if InsTabMemRefSizeInfoCache^[opcode].MemRefSize = mrsize then - sl.add(format('%-25s: %s', [GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize)), std_op2str[opcode]])); + begin + sGasSufffix:=''; + if gas_needsuffix[opcode] <> AttSufNone then + sGasSufffix:=GetEnumName(Typeinfo(TAttSuffix), ord(gas_needsuffix[opcode])); + + sl.add(format('%-25s: %s: %s', [GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize)), std_op2str[opcode], sGasSufffix])); + end; end; sl.Sort; From ecdac1dd399df3d5dade5151e320686db821ef9e Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 12 Jan 2021 16:19:53 +0000 Subject: [PATCH 038/116] cleanup + add internal error if all asmr_e_not_supported_combination_attsuffix_memrefsize_type are reported git-svn-id: branches/tg74/avx512-0037785@48148 - --- compiler/x86/aasmcpu.pas | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index c1b37e3f32..699e009466 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -2307,7 +2307,7 @@ implementation function is_16_bit_ref(const ref:treference):boolean; var ir,br : Tregister; - isub,bsub : cgbase.tsubregister; + isub,bsub : tsubregister; begin if (ref.index<>NR_NO) and (getregtype(ref.index)=R_MMREGISTER) then exit(false); @@ -2467,15 +2467,15 @@ implementation // ax cx dx bx si di bp sp -- in x86reg.dat // ax cx dx bx sp bp si di -- needed order (0, 1, 2, 3, 6, 7, 5, 4); - maxsupreg: array[cgbase.tregistertype] of cgbase.tsuperregister= + maxsupreg: array[tregistertype] of tsuperregister= {$ifdef x86_64} (0, 16, 9, 8, 32, 32, 8, 0, 0, 0); {$else x86_64} (0, 8, 9, 8, 8, 32, 8, 0, 0, 0); {$endif x86_64} var - rs: cgbase.tsuperregister; - rt: cgbase.tregistertype; + rs: tsuperregister; + rt: tregistertype; begin rs:=getsupreg(r); rt:=getregtype(r); @@ -2532,7 +2532,7 @@ implementation base,index,scalefactor, o : longint; ir,br : Tregister; - isub,bsub : cgbase.tsubregister; + isub,bsub : tsubregister; begin result:=false; ir:=input.ref^.index; @@ -4617,7 +4617,7 @@ implementation end; - function taicpu.is_same_reg_move(regtype: cgbase.Tregistertype):boolean; + function taicpu.is_same_reg_move(regtype: Tregistertype):boolean; begin result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and (regtype = R_INTREGISTER) and From 54ea8468fc0fa0c2775c82a10ad62785c2a8f11a Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 12 Jan 2021 16:27:07 +0000 Subject: [PATCH 039/116] cleanup git-svn-id: branches/tg74/avx512-0037785@48149 - --- compiler/x86/rax86.pas | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index 5f06215607..0c077535c2 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -1682,21 +1682,11 @@ begin ; end; end; - //A_MOVSS, - //A_VMOVSS, A_MOVD : { movd is a move from a mmx register to a 32 bit register or memory, so no opsize is correct here PM } exit; A_MOVQ : opsize:=S_IQ; - //A_VCVTPD2DQ, - //A_VCVTPD2PS, - //A_VCVTTPD2DQ, - //A_VCVTPD2UDQ, - //A_VCVTQQ2PS, - //A_VCVTTPD2UDQ, - //A_VCVTUQQ2PS, - A_OUT : opsize:=tx86operand(operands[1]).opsize; else @@ -1704,26 +1694,8 @@ begin opsize:=tx86operand(operands[2]).opsize; end; end; - 3 : - begin - //case opcode of - //A_VCVTSI2SS, - //A_VCVTSI2SD, - //A_VCVTUSI2SS, - //A_VCVTUSI2SD: - // opsize:=tx86operand(operands[1]).opsize; - //A_VFPCLASSPD, - //A_VFPCLASSPS: - // iops:=tx86operand(operands[2]).opsize; - //else - begin - if not CheckSSEAVX then - opsize:=tx86operand(operands[ops]).opsize; - end; - //end; - end; - 4 : if not CheckSSEAVX then - opsize:=tx86operand(operands[ops]).opsize; + 3,4 : if not CheckSSEAVX then + opsize:=tx86operand(operands[ops]).opsize; end; end; From 555ecd826bd9b6d28784f7e285eb648d49e251ee Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 19 Jan 2021 05:12:39 +0000 Subject: [PATCH 040/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48187 - --- tests/utils/avx/asmtestgenerator.pas | 1074 ++++++++++++++++++++++++++ tests/utils/avx/avxopcodes.pas | 209 ++++- tests/utils/avx/avxtestgenerator.pp | 3 +- 3 files changed, 1271 insertions(+), 15 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 21423df5ff..01df2c3afc 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -32,6 +32,8 @@ type otXMEM32, otXMEM64, otYMEM32, otYMEM64, otZMEM32, otZMEM64, otB32, otB64, otKREG); + TOpMemType = Set of TOpType; + TOperandListItem = class(TObject) private FOpActive: boolean; @@ -89,12 +91,15 @@ type function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + function InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; public constructor Create; destructor Destroy; override; class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestDataCDisp8(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestInstFile; class procedure ListMemRefState; @@ -161,6 +166,9 @@ const msiZMem32, msiZMem64, msiVMemMultiple, msiVMemRegSize]; + OTMEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, + otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, + otRM32, otRM64, otB32, otB64]; var InsTabCache : PInsTabCache; @@ -3548,6 +3556,1050 @@ begin end; end; +function TAsmTestGenerator.InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, + aOp3, aOp4: String): TStringList; +var + i: integer; + Item: TOperandListItem; + OItem1: TOperandListItem; + OItem2: TOperandListItem; + OItem3: TOperandListItem; + OItem4: TOperandListItem; + + il_Op: integer; + il_Op1: integer; + il_Op2: integer; + il_Op3: integer; + il_Op4: integer; + + sSuffix: string; + sl_Operand: String; + sl_Inst : String; + sl_RegCombi: String; + sl_Prefix: String; + UsePrefix: boolean; + il_Operands: integer; + UsedParams: cardinal; + UseDefault: boolean; + sl_RegCombi1: string; + sl_RegCombi2: string; + sl_RegCombi3: string; + MaskRegNeeded:boolean; + + + function PrepareOperandTyp(const aTyp: String): String; + begin + result := aTyp; + if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); + if result = 'XMMRM128' then result := 'XMMRM'; + if result = 'YMMRM256' then result := 'YMMRM'; + end; + + +begin + result := TStringList.Create; + + OItem1 := TOperandListItem.Create; + try + OItem2 := TOperandListItem.Create; + try + OItem3 := TOperandListItem.Create; + try + OItem4 := TOperandListItem.Create; + try + + UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR + (UpperCase(aInst) = 'VCVTPD2PS') OR + (UpperCase(aInst) = 'VCVTSI2SD') OR + (UpperCase(aInst) = 'VCVTSI2SS') OR + (UpperCase(aInst) = 'VCVTTPD2DQ') or + (UpperCase(aInst) = 'VPMOVZXWQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTTPD2UDQ') or + (UpperCase(aInst) = 'VCVTUQQ2PS') or + (UpperCase(aInst) = 'VCVTQQ2PS') or + (UpperCase(aInst) = 'VCVTUSI2SD') or + (UpperCase(aInst) = 'VCVTUSI2SS') or + (UpperCase(aInst) = 'VFPCLASSPD') or + (UpperCase(aInst) = 'VFPCLASSPS') or + (UpperCase(aInst) = 'VCMPSS') + + ; + + + MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or + (Pos('VPGATHER', Uppercase(aInst)) = 1) or + (Pos('VPSCATTER', Uppercase(aInst)) = 1) or + (Pos('VSCATTER', Uppercase(aInst)) = 1); + + for il_Op := 1 to 4 do + begin + sl_Prefix := ''; + + case il_Op of + 1: begin + Item := OItem1; + sl_Operand := aOp1; + end; + 2: begin + Item := OItem2; + sl_Operand := aOp2; + end; + 3: begin + Item := OItem3; + sl_Operand := aOp3; + end; + 4: begin + Item := OItem4; + sl_Operand := aOp4; + end; + end; + + sl_Operand := PrepareOperandTyp(sl_Operand); + + if (AnsiSameText(sl_Operand, 'XMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + Item.Values.Add('XMM0'); + end + else if (AnsiSameText(sl_Operand, 'XMMREG_M')) or + (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'XMMREG_ER')) or + (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('XMM0' + sSuffix); + if (sSuffix <> '') and + (MaskRegNeeded = false) then Item.Values.Add('XMM0'); + end + else if (AnsiSameText(sl_Operand, 'XMMRM')) or + (AnsiSameText(sl_Operand, 'XMMRM_M')) or + (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'XMMRM8')) or + (AnsiSameText(sl_Operand, 'XMMRM8_M')) or + (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'XMMRM16')) or + (AnsiSameText(sl_Operand, 'XMMRM16_M')) or + (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'YMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + Item.Values.Add('YMM0'); + end + else if (AnsiSameText(sl_Operand, 'YMMREG_M')) or + (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'YMMREG_ER')) or + (AnsiSameText(sl_Operand, 'YMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('YMM0' + sSuffix); + if (sSuffix <> '') and + (MaskRegNeeded = false) then Item.Values.Add('YMM0'); + end + else if (AnsiSameText(sl_Operand, 'YMMRM')) or + (AnsiSameText(sl_Operand, 'YMMRM_M')) or + (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'YMMRM_ER')) or + (AnsiSameText(sl_Operand, 'YMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'ZMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + Item.Values.Add('ZMM0'); + end + else if (AnsiSameText(sl_Operand, 'ZMMREG_M')) or + (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or + (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'ZMMRM')) or + (AnsiSameText(sl_Operand, 'ZMMRM_M')) or + (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM8; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'byte '; + + + sSuffix := ''; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM16') or + AnsiSameText(sl_Operand, 'MEM16_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM32') or + AnsiSameText(sl_Operand, 'MEM32_M') or + AnsiSameText(sl_Operand, 'MEM32_MZ') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'dword '; + + sSuffix := ''; + + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM64')) or + (AnsiSameText(sl_Operand, 'MEM64_M')) or + (AnsiSameText(sl_Operand, 'MEM64_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'qword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM128')) or + (AnsiSameText(sl_Operand, 'MEM128_M')) or + (AnsiSameText(sl_Operand, 'MEM128_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM128; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM256')) or + (AnsiSameText(sl_Operand, 'MEM256_M')) or + (AnsiSameText(sl_Operand, 'MEM256_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM256; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM512')) or + (AnsiSameText(sl_Operand, 'MEM512_M')) or + (AnsiSameText(sl_Operand, 'MEM512_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM512; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'REG8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG8; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg8); + end + else Item.Values.AddStrings(FReg8); + end + else if AnsiSameText(sl_Operand, 'REG16') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG16; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg16); + end + else Item.Values.AddStrings(FReg16); + end + else if AnsiSameText(sl_Operand, 'REG32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG32; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg32Base); + end + else Item.Values.AddStrings(FReg32Base); + end + else if AnsiSameText(sl_Operand, 'REG64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG64; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + end; + end + else if AnsiSameText(sl_Operand, 'RM32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + Item.Values.AddStrings(FReg32Base); + + if UsePrefix then sl_Prefix := 'dword '; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'RM64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'qword '; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'IMM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otIMM8; + Item.OpActive := true; + + Item.Values.Add('0'); + end + else if AnsiSameText(sl_Operand, 'XMEM32') or + AnsiSameText(sl_Operand, 'XMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + end + else if AnsiSameText(sl_Operand, 'XMEM64') or + AnsiSameText(sl_Operand, 'XMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM64; + Item.OpActive := true; + + //if UsePrefix then sl_Prefix := 'oword '; + // + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM32') or + AnsiSameText(sl_Operand, 'YMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM64') or + AnsiSameText(sl_Operand, 'YMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM32') or + AnsiSameText(sl_Operand, 'ZMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM64') or + AnsiSameText(sl_Operand, 'ZMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, '2B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '2B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'KREG') or + AnsiSameText(sl_Operand, 'KREG_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otKREG; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if UsePrefix then sl_Prefix := ''; + + for i := 0 to FRegKREG.Count - 1 do + Item.Values.Add(FRegKREG[i] + sSuffix); + end + else if trim(sl_Operand) = '' then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add(''); + end + else + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add('?' + sl_Operand); + end + + end; + + sl_RegCombi := ''; + + + il_Operands := 0; + UsedParams := 0; + + if OItem1.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 1; + end; + + if OItem2.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 2; + end; + + if OItem3.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 4; + end; + + if OItem4.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 8; + end; + + case il_Operands of + 1: UseDefault := UsedParams <> 1; + 2: UseDefault := UsedParams <> 3; + 3: UseDefault := UsedParams <> 7; + 4: UseDefault := UsedParams <> 15; + else UseDefault := true; + end; + + //UseDefault := true; + + if UseDefault then + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sl_RegCombi := ''; + + if OItem1.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + end; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end + else + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + if OItem1.OpActive then + begin + sl_RegCombi1 := OItem1.Values[il_Op1]; + end + else sl_RegCombi1 := ''; + + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + if OItem2.OpActive then + begin + sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + end + else sl_RegCombi2 := sl_RegCombi1; + + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + if OItem3.OpActive then + begin + sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + end + else sl_RegCombi3 := sl_RegCombi2; + + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + if OItem4.OpActive then + begin + sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + end + else sl_RegCombi := sl_RegCombi3; + + if (sl_RegCombi <> '') and + ( + (OItem1.OpActive and (OItem1.OpTyp in OTMEMTYPES)) or + (OItem2.OpActive and (OItem2.OpTyp in OTMEMTYPES)) or + (OItem3.OpActive and (OItem3.OpTyp in OTMEMTYPES)) or + (OItem4.OpActive and (OItem4.OpTyp in OTMEMTYPES)) + ) then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + + + + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end; + finally + FreeAndNil(OItem4); + end; + finally + FreeAndNil(OItem3); + end; + finally + FreeAndNil(OItem2); + end; + finally + FreeAndNil(OItem1); + end; +end; + constructor TAsmTestGenerator.Create; begin @@ -3921,6 +4973,28 @@ begin end; end; +class procedure TAsmTestGenerator.CalcTestDataCDisp8(aX64, aAVX512, + aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); +var + sl: TStringList; +begin + with TAsmTestGenerator.Create do + try + Fx64 := aX64; + FAVX512 := aAVX512; + FSAE := aSAE; + + sl := InternalCalcTestDataCDisp8(aInst, aOp1, aOp2, aOp3, aOp4); + try + aSL.AddStrings(sl); + finally + FreeAndNil(sl); + end; + finally + Free; + end; +end; + class procedure TAsmTestGenerator.CalcTestInstFile; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 9915b8d80a..4c4b6ba7db 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -8,7 +8,7 @@ uses Classes; type - TTestFileTyp = (tfNasm, tfFPC, tfFasm, tfFPCInc, tfFPCMRef); + TTestFileTyp = (tfNasm, tfFPC, tfFasm, tfFPCInc, tfFPCMRef, tfFPCCDisp8); { TAVXTestGenerator } @@ -18,7 +18,10 @@ type protected procedure Init; + function SaveFile(aAsmList: TStringList; aOpcode, aDestPath, aFileExt: String; aHeaderList, aFooterList: TStringList): boolean; + function InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; + function InternalMakeTestFilesCDisp8(aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; public constructor Create; @@ -3277,6 +3280,22 @@ begin FOpCodeList.Add('VPSHUFBITQMB,1,1,1,kreg_m,zmmreg,zmmrm,'); end; +function TAVXTestGenerator.SaveFile(aAsmList: TStringList; aOpcode, aDestPath, + aFileExt: String; aHeaderList, aFooterList: TStringList): boolean; +begin + begin + result := false; + + if aAsmList.Count > 0 then + begin + aAsmList.Insert(0, StringReplace(aHeaderList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); + aAsmList.AddStrings(StringReplace(aFooterList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); + + aAsmList.SaveToFile(IncludeTrailingBackslash(aDestPath) + aOpCode + aFileExt); + end; + end; +end; + function TAVXTestGenerator.InternalMakeTestFiles(aMRef, aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, aHeaderList, aFooterList: TStringList): boolean; var @@ -3292,18 +3311,18 @@ var NewOpCode: String; FoundNewOpcode: boolean; - function SaveFile(aAsmList: TStringList; aOpcode, aDestPath, aFileExt: String; aHeaderList, aFooterList: TStringList): boolean; - begin - result := false; - - if aAsmList.Count > 0 then - begin - aAsmList.Insert(0, StringReplace(aHeaderList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); - aAsmList.AddStrings(StringReplace(aFooterList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); - - aAsmList.SaveToFile(IncludeTrailingBackslash(aDestPath) + aOpCode + aFileExt); - end; - end; + //function SaveFile(aAsmList: TStringList; aOpcode, aDestPath, aFileExt: String; aHeaderList, aFooterList: TStringList): boolean; + //begin + // result := false; + // + // if aAsmList.Count > 0 then + // begin + // aAsmList.Insert(0, StringReplace(aHeaderList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); + // aAsmList.AddStrings(StringReplace(aFooterList.Text, '$$$OPCODE$$$', aOpCode, [rfReplaceAll])); + // + // aAsmList.SaveToFile(IncludeTrailingBackslash(aDestPath) + aOpCode + aFileExt); + // end; + //end; begin result := false; @@ -3395,6 +3414,101 @@ begin end; end; +function TAVXTestGenerator.InternalMakeTestFilesCDisp8(aX64, aAVX512, + aSAE: boolean; aDestPath, aFilemask, aFileExt: String; aOpCodeList, + aHeaderList, aFooterList: TStringList): boolean; +var + i,j: integer; + sData: string; + sDestFile: string; + sLocalVarDataTyp: string; + sl: TStringList; + slAsm: TStringList; + slLocalHeader: TStringList; + slFilemask: TStringList; + LastOpCode: String; + NewOpCode: String; + FoundNewOpcode: boolean; + +begin + result := false; + + aOpCodeList.Sort; + + sl := TStringList.Create; + try + slAsm := TStringList.Create; + try + slFilemask := TStringList.Create; + try + slFilemask.CommaText := ansilowercase(aFilemask); + + LastOpCode := ''; + + for i := 0 to aOpCodeList.Count - 1 do + begin + sl.Clear; + sl.CommaText := aOpCodeList[i]; + + while sl.Count < 8 do sl.Add(''); + + NewOpCode := ansilowercase(sl[0]); + + FoundNewOpcode := false; + for j := 0 to slFilemask.Count - 1 do + begin + if Pos(slFilemask[j], NewOpCode) = 1 then + FoundNewOpcode := true; + end; + + if not(FoundNewOpcode) and (slFilemask.Count > 0) then + NewOpcode := ''; + + if NewOpCode <> '' then + begin + if (not(aX64) and (sl[1] = '1')) or // i386 + (aX64 and (sl[2] = '1')) then // x86_64 + begin + sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); + + slLocalHeader := TStringList.Create; + try + slLocalHeader.Text := aHeaderList.text; + + if (sl[4] = '') and + (sl[5] = '') and + (sl[6] = '') and + (sl[7] = '') then + begin // Opcode with no Params, e.g. VZEROALL + slAsm.Add(' ' + sl[0]); + end + else + begin + TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + end; + + SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); + writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); + + finally + FreeAndNil(slLocalHeader); + end; + + slAsm.Clear; + end; + end; + end; + finally + FreeAndNil(slFilemask); + end; + finally + FreeAndNil(slAsm); + end; + finally + FreeAndNil(sl); + end; +end; + function TAVXTestGenerator.MakeTestFiles(aTyp: TTestFileTyp; aX64, aAVX512, aSAE: boolean; aDestPath, aFilemask: String): boolean; var @@ -3542,6 +3656,70 @@ begin slFooter.Add('begin'); slFooter.Add('end.'); end; + tfFPCCDisp8: + begin + writeln(format('outputformat: fpc platform: %s path: %s', + [cPlatform[aX64], aDestPath])); + + FileExt := '.pp'; + + slHeader.Add('Program $$$OPCODE$$$;'); + slHeader.Add('{$asmmode intel}'); + + slHeader.Add('const'); + slHeader.Add(' cDataBlockByte: Array[0..255] of byte = ( $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0A, $0B, $0C, $0D, $0E, $0F,'); + slHeader.Add(' $10, $11, $12, $13, $14, $15, $16, $17, $18, $19, $1A, $1B, $1C, $1D, $1E, $1F,'); + slHeader.Add(' $20, $21, $22, $23, $24, $25, $26, $27, $28, $29, $2A, $2B, $2C, $2D, $2E, $2F,'); + slHeader.Add(' $30, $31, $32, $33, $34, $35, $36, $37, $38, $39, $3A, $3B, $3C, $3D, $3E, $3F,'); + slHeader.Add(' $40, $41, $42, $43, $44, $45, $46, $47, $48, $49, $4A, $4B, $4C, $4D, $4E, $4F,'); + slHeader.Add(' $50, $51, $52, $53, $54, $55, $56, $57, $58, $59, $5A, $5B, $5C, $5D, $5E, $5F,'); + slHeader.Add(' $60, $61, $62, $63, $64, $65, $66, $67, $68, $69, $6A, $6B, $6C, $6D, $6E, $6F,'); + slHeader.Add(' $70, $71, $72, $73, $74, $75, $76, $77, $78, $79, $7A, $7B, $7C, $7D, $7E, $7F,'); + slHeader.Add(' $80, $81, $82, $83, $84, $85, $86, $87, $88, $89, $8A, $8B, $8C, $8D, $8E, $8F,'); + slHeader.Add(' $90, $91, $92, $93, $94, $95, $96, $97, $98, $99, $9A, $9B, $9C, $9D, $9E, $9F,'); + slHeader.Add(' $A0, $A1, $A2, $A3, $A4, $A5, $A6, $A7, $A8, $A9, $AA, $AB, $AC, $AD, $AE, $AF,'); + slHeader.Add(' $B0, $B1, $B2, $B3, $B4, $B5, $B6, $B7, $B8, $B9, $BA, $BB, $BC, $BD, $BE, $BF,'); + slHeader.Add(' $C0, $C1, $C2, $C3, $C4, $C5, $C6, $C7, $C8, $C9, $CA, $CB, $CC, $CD, $CE, $CF,'); + slHeader.Add(' $D0, $D1, $D2, $D3, $D4, $D5, $D6, $D7, $D8, $D9, $DA, $DB, $DC, $DD, $DE, $DF,'); + slHeader.Add(' $E0, $E1, $E2, $E3, $E4, $E5, $E6, $E7, $E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF,'); + slHeader.Add(' $F0, $F1, $F2, $F3, $F4, $F5, $F6, $F7, $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF);'); + + + + slHeader.Add('begin'); + slHeader.Add(' asm'); + + slHeader.Add(' vpxord zmm0, zmm0, zmm0'); + slHeader.Add(' vpxord xmm1, xmm1, xmm1'); + slHeader.Add(' vpxord xmm2, xmm2, xmm2'); + slHeader.Add(' vpxord xmm3, xmm3, xmm3'); + slHeader.Add(' vpxord xmm4, xmm4, xmm4'); + slHeader.Add(' vpcmpeqb k1, zmm0, zmm0'); + + if aX64 then + begin + slHeader.Add(' lea rax, cDataBlockByte'); + slHeader.Add(' push rax'); + end + else + begin + slHeader.Add(' lea eax, cDataBlockByte'); + slHeader.Add(' push eax'); + end; + + for i := 1 to 10 do + slHeader.Add('NOP'); + + if aX64 then slFooter.Add(' pop rax') + else slFooter.Add(' pop eax'); + + for i := 1 to 10 do + slFooter.Add('NOP'); + + slFooter.Add(' end;'); + slFooter.Add('end.'); + + end; tfFPCInc: begin writeln(format('outputformat: fpc platform: %s path: %s', [cPlatform[aX64], aDestPath])); @@ -3617,7 +3795,10 @@ begin end; end; - InternalMakeTestFiles(aTyp = tfFPCMRef, aX64, aAVX512, aSAE, aDestPath, aFilemask, Fileext, FOpCodeList, slHeader, slFooter); + case aTyp of + tfFPCCDisp8: InternalMakeTestFilesCDisp8(aX64, aAVX512, aSAE, aDestPath, aFilemask, Fileext, FOpCodeList, slHeader, slFooter); + else InternalMakeTestFiles(aTyp = tfFPCMRef, aX64, aAVX512, aSAE, aDestPath, aFilemask, Fileext, FOpCodeList, slHeader, slFooter); + end; finally FreeAndNil(slFooter); diff --git a/tests/utils/avx/avxtestgenerator.pp b/tests/utils/avx/avxtestgenerator.pp index 0b2fc0f2b1..680c7a1ed6 100644 --- a/tests/utils/avx/avxtestgenerator.pp +++ b/tests/utils/avx/avxtestgenerator.pp @@ -42,7 +42,7 @@ begin writeln('make avx assembler-testfiles'); writeln(''); writeln('-h help'); - writeln('-f [fpc,fpcmref,nasm,fasm,fpcinc] outputformat'); + writeln('-f [fpc,fpcmref,fpccd8,nasm,fasm,fpcinc] outputformat'); writeln('-l list opcode-memrefsize-states'); writeln('-m create only these testfile(s) (e.g. -mvgather,vpgather)'); writeln('-o destination path'); @@ -62,6 +62,7 @@ begin 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path, Filemask); 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path, Filemask); 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path, Filemask); + 'd': MakeTestFiles(tfFPCCDisp8, x64, AVX512, false, Path, Filemask); 'l': ListMemRefState; end; end; From c2a3f03093d6a4814d0d740244afa7800194781d Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 19 Jan 2021 11:01:32 +0000 Subject: [PATCH 041/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48189 - --- tests/utils/avx/asmtestgenerator.pas | 295 ++++++++++++++++----------- tests/utils/avx/avxopcodes.pas | 8 +- tests/utils/avx/avxtestgenerator.lpi | 3 - 3 files changed, 181 insertions(+), 125 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 01df2c3afc..2789a550f9 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3575,7 +3575,11 @@ var sSuffix: string; sl_Operand: String; sl_Inst : String; - sl_RegCombi: String; + sRegCombi0: String; + sRegCombi1: String; + sRegCombi2: String; + sRegCombi3: String; + sRegCombi4: String; sl_Prefix: String; UsePrefix: boolean; il_Operands: integer; @@ -3585,7 +3589,7 @@ var sl_RegCombi2: string; sl_RegCombi3: string; MaskRegNeeded:boolean; - + slRegCombi: TStringList; function PrepareOperandTyp(const aTyp: String): String; begin @@ -3664,7 +3668,7 @@ begin Item.OpTyp := otXMMReg; Item.OpActive := true; - Item.Values.Add('XMM0'); + Item.Values.Add('XMM16|XMM1'); end else if (AnsiSameText(sl_Operand, 'XMMREG_M')) or (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or @@ -3675,16 +3679,18 @@ begin Item.OpTyp := otXMMReg; Item.OpActive := true; - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + // + //Item.Values.Add('XMM0' + sSuffix); + //if (sSuffix <> '') and + // (MaskRegNeeded = false) then Item.Values.Add('XMM0'); - if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('XMM0' + sSuffix); - if (sSuffix <> '') and - (MaskRegNeeded = false) then Item.Values.Add('XMM0'); + Item.Values.Add('XMM16|XMM1'); end else if (AnsiSameText(sl_Operand, 'XMMRM')) or (AnsiSameText(sl_Operand, 'XMMRM_M')) or @@ -3738,7 +3744,7 @@ begin Item.OpTyp := otYMMReg; Item.OpActive := true; - Item.Values.Add('YMM0'); + Item.Values.Add('YMM16|XMM1|XMM2'); end else if (AnsiSameText(sl_Operand, 'YMMREG_M')) or (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or @@ -3750,16 +3756,18 @@ begin Item.OpTyp := otYMMReg; Item.OpActive := true; - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + // + //Item.Values.Add('YMM0' + sSuffix); + //if (sSuffix <> '') and + // (MaskRegNeeded = false) then Item.Values.Add('YMM0'); - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('YMM0' + sSuffix); - if (sSuffix <> '') and - (MaskRegNeeded = false) then Item.Values.Add('YMM0'); + Item.Values.Add('YMM16|XMM1|XMM2'); end else if (AnsiSameText(sl_Operand, 'YMMRM')) or (AnsiSameText(sl_Operand, 'YMMRM_M')) or @@ -3774,12 +3782,12 @@ begin if UsePrefix then sl_Prefix := 'yword '; - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); @@ -3790,7 +3798,7 @@ begin Item.OpTyp := otZMMReg; Item.OpActive := true; - Item.Values.Add('ZMM0'); + Item.Values.Add('ZMM16,XMM1,XMM2,XMM3,XMM4'); end else if (AnsiSameText(sl_Operand, 'ZMMREG_M')) or (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or @@ -3802,12 +3810,12 @@ begin Item.OpTyp := otZMMReg; Item.OpActive := true; - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); @@ -4441,7 +4449,7 @@ begin end; - sl_RegCombi := ''; + //sl_RegCombi := ''; il_Operands := 0; @@ -4493,38 +4501,89 @@ begin begin for il_Op4 := 0 to OItem4.Values.Count - 1 do begin - sl_RegCombi := ''; + slRegCombi := TStringList.Create; + try + while slRegCombi.Count < 5 do + slRegCombi.Add(''); - if OItem1.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; + if OItem1.OpActive then + begin + + + end; + finally + FreeAndNil(slRegCombi); end; - if OItem2.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; - end; - - if OItem3.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; - end; - - if OItem4.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; - end; - - if sl_RegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - sl_RegCombi := ''; - end; + //sRegCombi0 := ''; + //sRegCombi1 := ''; + //sRegCombi2 := ''; + //sRegCombi3 := ''; + //sRegCombi4 := ''; + // + //if OItem1.OpActive then + //begin + // if sRegCombi0 <> '' then + // begin + // sRegCombi0 := sRegCombi0 + ', '; + // sRegCombi1 := sRegCombi1 + ', '; + // sRegCombi2 := sRegCombi2 + ', '; + // sRegCombi3 := sRegCombi3 + ', '; + // sRegCombi4 := sRegCombi4 + ', '; + // end; + // + // if Pos('|', OItem1.Values[il_Op1]) > 0 then + // begin + // with TStringList.Create do + // try + // Text := Stringreplace(OItem1.Values[il_Op1], '|', #13#10,[rfReplaceAll]); + // iCnt := Count; + // while Count < 5 do Add(''); + // + // sRegCombi0 := sRegCombi0 + Strings[0]; + // sRegCombi1 := sRegCombi1 + Strings[1]; + // sRegCombi2 := sRegCombi2 + Strings[2]; + // sRegCombi3 := sRegCombi3 + Strings[3]; + // sRegCombi4 := sRegCombi4 + Strings[4]; + // + // finally + // Free; + // end; + // end + // else + // begin + // sRegCombi0 := sRegCombi0 + OItem1.Values[il_Op1]; + // sRegCombi1 := sRegCombi1 + OItem1.Values[il_Op1]; + // sRegCombi2 := sRegCombi2 + OItem1.Values[il_Op1]; + // sRegCombi3 := sRegCombi3 + OItem1.Values[il_Op1]; + // sRegCombi4 := sRegCombi4 + OItem1.Values[il_Op1]; + // end; + //end; + // + //if OItem2.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + //end; + // + //if OItem3.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + //end; + // + //if OItem4.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + //end; + // + //if sl_RegCombi <> '' then + //begin + // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + // result.Add(sl_Inst + sl_RegCombi); + // sl_RegCombi := ''; + //end; end; end; end; @@ -4532,59 +4591,59 @@ begin end else begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - if OItem1.OpActive then - begin - sl_RegCombi1 := OItem1.Values[il_Op1]; - end - else sl_RegCombi1 := ''; - - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - if OItem2.OpActive then - begin - sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; - end - else sl_RegCombi2 := sl_RegCombi1; - - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - if OItem3.OpActive then - begin - sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; - end - else sl_RegCombi3 := sl_RegCombi2; - - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - if OItem4.OpActive then - begin - sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; - end - else sl_RegCombi := sl_RegCombi3; - - if (sl_RegCombi <> '') and - ( - (OItem1.OpActive and (OItem1.OpTyp in OTMEMTYPES)) or - (OItem2.OpActive and (OItem2.OpTyp in OTMEMTYPES)) or - (OItem3.OpActive and (OItem3.OpTyp in OTMEMTYPES)) or - (OItem4.OpActive and (OItem4.OpTyp in OTMEMTYPES)) - ) then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - - - - sl_RegCombi := ''; - end; - end; - end; - end; - end; + //sl_Inst := format('%-20s', [aInst]); + // + //for il_Op1 := 0 to OItem1.Values.Count - 1 do + //begin + // if OItem1.OpActive then + // begin + // sl_RegCombi1 := OItem1.Values[il_Op1]; + // end + // else sl_RegCombi1 := ''; + // + // for il_Op2 := 0 to OItem2.Values.Count - 1 do + // begin + // if OItem2.OpActive then + // begin + // sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + // end + // else sl_RegCombi2 := sl_RegCombi1; + // + // for il_Op3 := 0 to OItem3.Values.Count - 1 do + // begin + // if OItem3.OpActive then + // begin + // sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + // end + // else sl_RegCombi3 := sl_RegCombi2; + // + // for il_Op4 := 0 to OItem4.Values.Count - 1 do + // begin + // if OItem4.OpActive then + // begin + // sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + // end + // else sl_RegCombi := sl_RegCombi3; + // + // if (sl_RegCombi <> '') and + // ( + // (OItem1.OpActive and (OItem1.OpTyp in OTMEMTYPES)) or + // (OItem2.OpActive and (OItem2.OpTyp in OTMEMTYPES)) or + // (OItem3.OpActive and (OItem3.OpTyp in OTMEMTYPES)) or + // (OItem4.OpActive and (OItem4.OpTyp in OTMEMTYPES)) + // ) then + // begin + // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + // result.Add(sl_Inst + sl_RegCombi); + // + // + // + // sl_RegCombi := ''; + // end; + // end; + // end; + // end; + //end; end; finally FreeAndNil(OItem4); diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 4c4b6ba7db..3407637aca 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -42,7 +42,7 @@ uses SysUtils, AsmTestGenerator, Dialogs; constructor TAVXTestGenerator.Create; var - i: integer; + i: integer; begin inherited; @@ -3546,7 +3546,7 @@ begin slFooter.Add(' end;'); slFooter.Add('end.'); end; - tfFPCMRef: + tfFPCMRef: begin writeln(format('outputformat: fpc platform: %s path: %s', [cPlatform[aX64], aDestPath])); @@ -3646,8 +3646,8 @@ begin slHeader.Add(' asm'); for i := 1 to 10 do slHeader.Add(' NOP'); - - + + for i := 1 to 10 do slFooter.Add(' NOP'); diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index e0fadcd6ce..df0cac5f89 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -21,9 +21,6 @@ - - - From 149f8ddfe9965e73e3e0acb94b46c623a9c0c087 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 20 Jan 2021 16:30:38 +0000 Subject: [PATCH 042/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48230 - --- tests/utils/avx/asmtestgenerator.pas | 49 +++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 2789a550f9..b35b622690 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3599,6 +3599,41 @@ var if result = 'YMMRM256' then result := 'YMMRM'; end; + procedure SplitOperands(const aOperand1, aOperand2, aOperand3, aOperand4: string; var aRegCombi0, aRegCombi1, aRegCombi2, aRegCombi3, aRegCombi4: string); + var + s1: string; + s2: string; + s3: string; + s4: string; + iCnt1: integer; + iCnt2: integer; + iCnt3: integer; + iCnt4: integer; + iMaxCnt: integer; + begin + with TStringList.Create do + try + Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); + iCnt1 := Count; + + Text := StringReplace(trim(aOperand2), '|', #13#10, [rfReplaceAll]); + iCnt2 := Count; + + Text := StringReplace(trim(aOperand3), '|', #13#10, [rfReplaceAll]); + iCnt3 := Count; + + Text := StringReplace(trim(aOperand4), '|', #13#10, [rfReplaceAll]); + iCnt4 := Count; + + iMaxCnt := iCnt1; + if iCnt2 > iMaxCnt then iMaxCnt := iCnt2; + if iCnt3 > iMaxCnt then iMaxCnt := iCnt3; + if iCnt4 > iMaxCnt then iMaxCnt := iCnt4; + + finally + Free; + end; + end; begin result := TStringList.Create; @@ -4506,11 +4541,17 @@ begin while slRegCombi.Count < 5 do slRegCombi.Add(''); - if OItem1.OpActive then - begin + sRegCombi0 := ''; + sRegCombi1 := ''; + sRegCombi2 := ''; + sRegCombi3 := ''; + sRegCombi4 := ''; - - end; + //if OItem1.OpActive then + //begin + // SplitOperand(OItem1.Values[il_Op1], sRegCombi0,sRegCombi1,sRegCombi2,sRegCombi3,sRegCombi4); + // + //end; finally FreeAndNil(slRegCombi); end; From 22e8cd3fd3ebf6b1747cb17064419d9d90450985 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 21 Jan 2021 04:57:47 +0000 Subject: [PATCH 043/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48261 - --- tests/utils/avx/asmtestgenerator.pas | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index b35b622690..e780170d8d 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3601,6 +3601,7 @@ var procedure SplitOperands(const aOperand1, aOperand2, aOperand3, aOperand4: string; var aRegCombi0, aRegCombi1, aRegCombi2, aRegCombi3, aRegCombi4: string); var + i: integer; s1: string; s2: string; s3: string; @@ -3630,6 +3631,51 @@ var if iCnt3 > iMaxCnt then iMaxCnt := iCnt3; if iCnt4 > iMaxCnt then iMaxCnt := iCnt4; + + if (aOperand1 <> '') and (aRegCombi0 <> '') then + begin + aRegCombi0 := aRegCombi0 + ','; + aRegCombi1 := aRegCombi1 + ','; + aRegCombi2 := aRegCombi2 + ','; + aRegCombi3 := aRegCombi3 + ','; + aRegCombi4 := aRegCombi4 + ','; + end; + + + Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); + if Count = iMaxCnt then + begin + for i := 0 to iMaxCnt - 1 do + begin + case i of + 0: aRegCombi0 := aRegCombi0 + ',' + Strings[i]; + 1: aRegCombi1 := aRegCombi1 + ',' + Strings[i]; + 2: aRegCombi2 := aRegCombi2 + ',' + Strings[i]; + 3: aRegCombi3 := aRegCombi3 + ',' + Strings[i]; + 4: aRegCombi4 := aRegCombi4 + ',' + Strings[i]; + end; + end; + end + else + begin + if Count = 1 then + begin + for i := 0 to iMaxCnt - 1 do + begin + case i of + 0: aRegCombi0 := aRegCombi0 + ',' + Strings[0]; + 1: aRegCombi1 := aRegCombi1 + ',' + Strings[0]; + 2: aRegCombi2 := aRegCombi2 + ',' + Strings[0]; + 3: aRegCombi3 := aRegCombi3 + ',' + Strings[0]; + 4: aRegCombi4 := aRegCombi4 + ',' + Strings[0]; + end; + end; + end + else + begin + // TODO log + end; + end; finally Free; end; From 0a254b46bc0c01773778e93497609b5e27d139a9 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 25 Jan 2021 05:24:29 +0000 Subject: [PATCH 044/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48416 - --- tests/utils/avx/asmtestgenerator.pas | 158 ++++++++++++++++++++++----- tests/utils/avx/avxopcodes.pas | 3 +- tests/utils/avx/avxtestgenerator.lpi | 5 +- tests/utils/avx/options.pas | 1 + 4 files changed, 140 insertions(+), 27 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index e780170d8d..32d3b419bc 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -34,6 +34,8 @@ type TOpMemType = Set of TOpType; + TOpMode = (omUnknown, omXXM, omYYM, omZZM); + TOperandListItem = class(TObject) private FOpActive: boolean; @@ -166,9 +168,9 @@ const msiZMem32, msiZMem64, msiVMemMultiple, msiVMemRegSize]; - OTMEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, - otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, - otRM32, otRM64, otB32, otB64]; + MEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, + otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, + otRM32, otRM64, otB32, otB64]; var InsTabCache : PInsTabCache; @@ -3575,7 +3577,7 @@ var sSuffix: string; sl_Operand: String; sl_Inst : String; - sRegCombi0: String; + sRegCombi: String; sRegCombi1: String; sRegCombi2: String; sRegCombi3: String; @@ -3588,8 +3590,10 @@ var sl_RegCombi1: string; sl_RegCombi2: string; sl_RegCombi3: string; + sInstruction: string; MaskRegNeeded:boolean; slRegCombi: TStringList; + OpMode: TOpMode; function PrepareOperandTyp(const aTyp: String): String; begin @@ -3611,6 +3615,7 @@ var iCnt3: integer; iCnt4: integer; iMaxCnt: integer; + begin with TStringList.Create do try @@ -3749,7 +3754,7 @@ begin Item.OpTyp := otXMMReg; Item.OpActive := true; - Item.Values.Add('XMM16|XMM1'); + Item.Values.Add('XMM16'); end else if (AnsiSameText(sl_Operand, 'XMMREG_M')) or (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or @@ -3771,7 +3776,7 @@ begin //if (sSuffix <> '') and // (MaskRegNeeded = false) then Item.Values.Add('XMM0'); - Item.Values.Add('XMM16|XMM1'); + Item.Values.Add('XMM16'); end else if (AnsiSameText(sl_Operand, 'XMMRM')) or (AnsiSameText(sl_Operand, 'XMMRM_M')) or @@ -3825,7 +3830,7 @@ begin Item.OpTyp := otYMMReg; Item.OpActive := true; - Item.Values.Add('YMM16|XMM1|XMM2'); + Item.Values.Add('YMM16'); end else if (AnsiSameText(sl_Operand, 'YMMREG_M')) or (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or @@ -3848,7 +3853,7 @@ begin //if (sSuffix <> '') and // (MaskRegNeeded = false) then Item.Values.Add('YMM0'); - Item.Values.Add('YMM16|XMM1|XMM2'); + Item.Values.Add('YMM16'); end else if (AnsiSameText(sl_Operand, 'YMMRM')) or (AnsiSameText(sl_Operand, 'YMMRM_M')) or @@ -3879,7 +3884,7 @@ begin Item.OpTyp := otZMMReg; Item.OpActive := true; - Item.Values.Add('ZMM16,XMM1,XMM2,XMM3,XMM4'); + Item.Values.Add('ZMM16'); end else if (AnsiSameText(sl_Operand, 'ZMMREG_M')) or (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or @@ -3898,8 +3903,7 @@ begin //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + Item.Values.Add('ZMM16'); end else if (AnsiSameText(sl_Operand, 'ZMMRM')) or (AnsiSameText(sl_Operand, 'ZMMRM_M')) or @@ -3914,12 +3918,12 @@ begin if UsePrefix then sl_Prefix := 'zword '; - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); @@ -4568,6 +4572,7 @@ begin else UseDefault := true; end; + // TODO deaktivieren //UseDefault := true; if UseDefault then @@ -4587,17 +4592,13 @@ begin while slRegCombi.Count < 5 do slRegCombi.Add(''); - sRegCombi0 := ''; - sRegCombi1 := ''; - sRegCombi2 := ''; - sRegCombi3 := ''; - sRegCombi4 := ''; - //if OItem1.OpActive then - //begin + //SplitOperands(OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4] + if OItem1.OpActive then + begin // SplitOperand(OItem1.Values[il_Op1], sRegCombi0,sRegCombi1,sRegCombi2,sRegCombi3,sRegCombi4); // - //end; + end; finally FreeAndNil(slRegCombi); end; @@ -4678,6 +4679,113 @@ begin end else begin + OpMode := omUnknown; + + case il_Operands of + 3: if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM + + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM + + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omZZM + else + begin + + end; + else; + end; + + + sInstruction := format('%20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sRegCombi := ''; + + if OItem1.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem4.Values[il_Op4]; + end; + + if sRegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(format('%-20s%s', [sInstruction, sRegCombi])); + + case OpMode of + omXXM: begin + result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); + result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', xmm1'); + result.Add(' kandq k1, k1, k2'); + result.Add(''); + end; + omYYM: begin + result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); + result.Add(sInstruction + 'XMM2, XMM2, ' + OItem3.Values[il_Op3] + ' + $10'); + + result.Add(' vinserti32x4 ymm1, ymm1, xmm2, 01'); + result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', ymm1'); + result.Add(' kandq k1, k1, k2'); + result.Add(''); + end; + omZZM: begin + result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); + result.Add(sInstruction + 'XMM2, XMM2, ' + OItem3.Values[il_Op3] + ' + $10'); + result.Add(sInstruction + 'XMM3, XMM3, ' + OItem3.Values[il_Op3] + ' + $20'); + result.Add(sInstruction + 'XMM4, XMM4, ' + OItem3.Values[il_Op3] + ' + $30'); + + result.Add(' vinserti32x4 zmm1, zmm1, xmm2, 01'); + result.Add(' vinserti32x4 zmm1, zmm1, xmm3, 02'); + result.Add(' vinserti32x4 zmm1, zmm1, xmm4, 03'); + + result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', zmm1'); + result.Add(' kandq k1, k1, k2'); + result.Add(''); + + end; + + + end; + + sRegCombi := ''; + end; + end; + end; + end; + end; + + + //sl_Inst := format('%-20s', [aInst]); // //for il_Op1 := 0 to OItem1.Values.Count - 1 do diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 3407637aca..7ac99be1e7 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3484,9 +3484,10 @@ begin end else begin - TAsmTestGenerator.CalcTestData(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); + TAsmTestGenerator.CalcTestDataCDisp8(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); end; + sDestFile := 'CDISP8_' + sDestFile; SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index df0cac5f89..e1fc55dd9c 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -21,11 +21,14 @@ + + + - + diff --git a/tests/utils/avx/options.pas b/tests/utils/avx/options.pas index 8e6566b144..91e6890256 100644 --- a/tests/utils/avx/options.pas +++ b/tests/utils/avx/options.pas @@ -97,6 +97,7 @@ begin else if sValue = 'fasm' then FOutputFormat := 'F' else if sValue = 'fpcinc' then FOutputFormat := 'I' else if sValue = 'fpcmref' then FOutputFormat := 'm' + else if sValue = 'fpccd8' then FOutputFormat := 'd' else IsInvalidParam := true; 'p': if sValue = 'x8664' then From 684bdb0245b603c5c116d90f5fe2438089e1201f Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 25 Jan 2021 16:01:01 +0000 Subject: [PATCH 045/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48419 - --- tests/utils/avx/asmtestgenerator.pas | 324 ++++++++++++++++++++++++--- tests/utils/avx/avxtestgenerator.lpi | 4 +- 2 files changed, 293 insertions(+), 35 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 32d3b419bc..12f5fd9c40 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -34,7 +34,11 @@ type TOpMemType = Set of TOpType; - TOpMode = (omUnknown, omXXM, omYYM, omZZM); + TOpMode = (omUnknown, + omKXM, omKYM, omKZM, + omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, + omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, + omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I); TOperandListItem = class(TObject) private @@ -170,7 +174,8 @@ const MEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, - otRM32, otRM64, otB32, otB64]; + otRM32, otRM64]; + BMEMTYPES: TOpMemType = [otB32, otB64]; var InsTabCache : PInsTabCache; @@ -3591,6 +3596,8 @@ var sl_RegCombi2: string; sl_RegCombi3: string; sInstruction: string; + sMREF: string; + sLogMsg: string; MaskRegNeeded:boolean; slRegCombi: TStringList; OpMode: TOpMode; @@ -3686,6 +3693,46 @@ var end; end; + function MapOperand(aOpTyp: TOpType): String; + begin + case aOpTyp of + otXMMReg: result := 'X'; + otYMMReg: result := 'Y'; + otZMMReg: result := 'Z'; + otEAX, + otRAX, + otREG64, + otREG32, + otREG16, + otREG8: result := 'R'; + otRM32, + otRM64, + otXMMRM, + otXMMRM8, + otXMMRM16, + otYMMRM, + otZMMRM, + otMem32, + otMem8, + otMem16, + otMem64, + otMem128, + otMem256, + otMem512: result := 'M'; + otIMM8: result := 'I'; + otXMEM32: result := 'X32'; + otXMEM64: result := 'X64'; + otYMEM32: result := 'Y32'; + otYMEM64: result := 'Y64'; + otZMEM32: result := 'Z32'; + otZMEM64: result := 'Z64'; + otB32: result := 'B32'; + otB64: result := 'B64'; + otKREG: result := 'K'; + else result := ''; + end; + end; + begin result := TStringList.Create; @@ -4682,20 +4729,103 @@ begin OpMode := omUnknown; case il_Operands of - 3: if (OItem1.OpTyp = otXMMReg) and + 3: if (OItem1.OpTyp = otKReg) and (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM + (OItem3.OpTyp in MEMTYPES) then OpMode := omKXM + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omKYM + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omKZM + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omXXB32 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omXXB64 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omXB32I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omXB64I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omXMI else if (OItem1.OpTyp = otYMMReg) and (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM + (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omYYB32 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omYYB64 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omYB32I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omYB64I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omYMI else if (OItem1.OpTyp = otZMMReg) and (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omZZM + (OItem3.OpTyp in MEMTYPES) then OpMode := omZZM + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omZZB32 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omZZB64 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omZB32I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omZB64I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omZMI + + else begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + if sLogMsg <> '' then + begin + if (sLogMsg <> 'RMI') and + (sLogMsg <> 'RRM') and + (sLogMsg <> 'RMR') and + (sLogMsg <> 'KKK') and + (sLogMsg <> 'KKI') and + (sLogMsg <> 'XXX') and + (sLogMsg <> 'YYY') and + (sLogMsg <> 'ZZZ') and + (sLogMsg <> 'XXI') and + (sLogMsg <> 'YYI') and + (sLogMsg <> 'ZZI') and + (sLogMsg <> 'XYI') and + (sLogMsg <> 'YZI') and + (sLogMsg <> 'XZI') and + (sLogMsg <> 'RXI') and + (sLogMsg <> 'RYI') and + (sLogMsg <> 'RZI') and + + (sLogMsg <> 'XXR') then + + writeln('offen: ' + sLogMsg); + end; end; else; end; @@ -4740,40 +4870,168 @@ begin if sRegCombi <> '' then begin //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(format('%-20s%s', [sInstruction, sRegCombi])); + result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); case OpMode of - omXXM: begin - result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); - result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', xmm1'); - result.Add(' kandq k1, k1, k2'); - result.Add(''); - end; - omYYM: begin - result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); - result.Add(sInstruction + 'XMM2, XMM2, ' + OItem3.Values[il_Op3] + ' + $10'); + omKXM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXB32I, + omXB64I: begin + sMREF := OItem2.Values[il_Op2]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(' vinserti32x4 ymm1, ymm1, xmm2, 01'); - result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', ymm1'); - result.Add(' kandq k1, k1, k2'); - result.Add(''); - end; - omZZM: begin - result.Add(sInstruction + 'XMM1, XMM1, ' + OItem3.Values[il_Op3] + ' + $00'); - result.Add(sInstruction + 'XMM2, XMM2, ' + OItem3.Values[il_Op3] + ' + $10'); - result.Add(sInstruction + 'XMM3, XMM3, ' + OItem3.Values[il_Op3] + ' + $20'); - result.Add(sInstruction + 'XMM4, XMM4, ' + OItem3.Values[il_Op3] + ' + $30'); + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXXM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXXB32, + omXXB64: begin + sMREF := OItem3.Values[il_Op3]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(' vinserti32x4 zmm1, zmm1, xmm2, 01'); - result.Add(' vinserti32x4 zmm1, zmm1, xmm3, 02'); - result.Add(' vinserti32x4 zmm1, zmm1, xmm4, 03'); + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; - result.Add(' vpcmpeqb k2, ' + OItem1.Values[il_Op1] + ', zmm1'); - result.Add(' kandq k1, k1, k2'); - result.Add(''); + omYB32I, + omYB64I: begin + sMREF := OItem2.Values[il_Op2]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - end; + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + + omYYM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omYYB32, + omYYB64: begin + sMREF := OItem3.Values[il_Op3]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omYMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZB32I, + omZB64I: + begin + sMREF := OItem2.Values[il_Op2]; + if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + + omZZM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZZB32, + omZZB64: begin + sMREF := OItem3.Values[il_Op3]; + if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; end; diff --git a/tests/utils/avx/avxtestgenerator.lpi b/tests/utils/avx/avxtestgenerator.lpi index e1fc55dd9c..e0fadcd6ce 100644 --- a/tests/utils/avx/avxtestgenerator.lpi +++ b/tests/utils/avx/avxtestgenerator.lpi @@ -22,13 +22,13 @@ - + - + From ae97668967c8d2dd3ddc05e8ae7e4e54519bb6a0 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 25 Jan 2021 16:23:56 +0000 Subject: [PATCH 046/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48420 - --- tests/utils/avx/asmtestgenerator.pas | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 12f5fd9c40..f7bcafeb29 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4900,9 +4900,6 @@ begin omXXB32, omXXB64: begin sMREF := OItem3.Values[il_Op3]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); From 1bcf50ce701c200fb6962226b2f48274d8a68985 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 27 Jan 2021 15:48:20 +0000 Subject: [PATCH 047/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48437 - --- tests/utils/avx/asmtestgenerator.pas | 328 ++++++++++++++------------- tests/utils/avx/avxopcodes.pas | 21 +- tests/utils/avx/avxtestgenerator.pp | 2 +- 3 files changed, 181 insertions(+), 170 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index f7bcafeb29..ecbd0a6694 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4740,8 +4740,8 @@ begin (OItem3.OpTyp in MEMTYPES) then OpMode := omKZM else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM else if (OItem1.OpTyp = otXMMReg) and (OItem2.OpTyp = otXMMReg) and (OItem3.OpTyp = otB32) then OpMode := omXXB32 @@ -4830,148 +4830,197 @@ begin else; end; - - sInstruction := format('%20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do + if OpMode <> omUnknown then begin - for il_Op2 := 0 to OItem2.Values.Count - 1 do + sInstruction := format('%20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do begin - for il_Op3 := 0 to OItem3.Values.Count - 1 do + for il_Op2 := 0 to OItem2.Values.Count - 1 do begin - for il_Op4 := 0 to OItem4.Values.Count - 1 do + for il_Op3 := 0 to OItem3.Values.Count - 1 do begin - sRegCombi := ''; - - if OItem1.OpActive then + for il_Op4 := 0 to OItem4.Values.Count - 1 do begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem1.Values[il_Op1]; - end; + sRegCombi := ''; - if OItem2.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem2.Values[il_Op2]; - end; + if OItem1.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem1.Values[il_Op1]; + end; - if OItem3.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem3.Values[il_Op3]; - end; + if OItem2.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem2.Values[il_Op2]; + end; - if OItem4.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem4.Values[il_Op4]; - end; + if OItem3.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem3.Values[il_Op3]; + end; - if sRegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); + if OItem4.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem4.Values[il_Op4]; + end; - case OpMode of - omKXM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omXB32I, - omXB64I: begin - sMREF := OItem2.Values[il_Op2]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + if sRegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omXXM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omXXB32, - omXXB64: begin - sMREF := OItem3.Values[il_Op3]; - - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omXMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - - omYB32I, - omYB64I: begin + case OpMode of + omKXM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXB32I, + omXB64I: begin sMREF := OItem2.Values[il_Op2]; if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXXM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXXB32, + omXXB64: begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omXMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + + omYB32I, + omYB64I: begin + sMREF := OItem2.Values[il_Op2]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + + omYYM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); result.Add(''); end; + omYYB32, + omYYB64: begin + sMREF := OItem3.Values[il_Op3]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - omYYM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omYYB32, - omYYB64: begin - sMREF := OItem3.Values[il_Op3]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omYMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZB32I, + omZB64I: + begin + sMREF := OItem2.Values[il_Op2]; + if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omYMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omZB32I, - omZB64I: - begin - sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + + omZZM: begin + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZZB32, + omZZB64: begin + sMREF := OItem3.Values[il_Op3]; if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); + result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); + + result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(''); + end; + omZMI: begin + result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); @@ -4982,57 +5031,10 @@ begin result.Add(''); end; - omZZM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); - - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omZZB32, - omZZB64: begin - sMREF := OItem3.Values[il_Op3]; - if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); - - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; - omZMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); - end; + end; + sRegCombi := ''; end; - - sRegCombi := ''; end; end; end; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 7ac99be1e7..50b8571065 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3466,8 +3466,15 @@ begin if NewOpCode <> '' then begin - if (not(aX64) and (sl[1] = '1')) or // i386 - (aX64 and (sl[2] = '1')) then // x86_64 + if ( + (not(aX64) and (sl[1] = '1')) or // i386 + (aX64 and (sl[2] = '1')) + ) and + ( + sl[3] = '1' + ) + + then // x86_64 begin sDestFile := format('%s_%d%s', [NewOpcode, i, trim(copy(sl[4],1,1) + copy(sl[5],1,1) + copy(sl[6],1,1) + copy(sl[7],1,1))]); @@ -3487,10 +3494,12 @@ begin TAsmTestGenerator.CalcTestDataCDisp8(aX64, aAVX512 and (sl[3] = '1'), aSAE, sl[0], sl[4], sl[5], sl[6], sl[7], slAsm); end; - sDestFile := 'CDISP8_' + sDestFile; - SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); - writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); - + if trim(slAsm.Text) <> '' then + begin + sDestFile := 'CDISP8_' + sDestFile; + SaveFile(slAsm, sDestFile, aDestPath, aFileExt, slLocalHeader, aFooterList); + writeln(format('%s%s%s', [aDestPath, sDestFile, aFileExt])); + end; finally FreeAndNil(slLocalHeader); end; diff --git a/tests/utils/avx/avxtestgenerator.pp b/tests/utils/avx/avxtestgenerator.pp index 680c7a1ed6..dd483c2cf3 100644 --- a/tests/utils/avx/avxtestgenerator.pp +++ b/tests/utils/avx/avxtestgenerator.pp @@ -62,7 +62,7 @@ begin 'n': MakeTestFiles(tfNasm, x64, AVX512, false, Path, Filemask); 'I': MakeTestFiles(tfFPCInc, x64, AVX512, false, Path, Filemask); 'm': MakeTestFiles(tfFPCMRef, x64, AVX512, false, Path, Filemask); - 'd': MakeTestFiles(tfFPCCDisp8, x64, AVX512, false, Path, Filemask); + 'd': MakeTestFiles(tfFPCCDisp8, x64, true, false, Path, Filemask); 'l': ListMemRefState; end; end; From 6eb2cd6dfde2bb99e1bf7dac9fc7b963497f09e4 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 1 Feb 2021 14:54:18 +0000 Subject: [PATCH 048/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48491 - --- tests/utils/avx/avxopcodes.pas | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 50b8571065..06354ab3a8 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3693,10 +3693,15 @@ begin slHeader.Add(' $D0, $D1, $D2, $D3, $D4, $D5, $D6, $D7, $D8, $D9, $DA, $DB, $DC, $DD, $DE, $DF,'); slHeader.Add(' $E0, $E1, $E2, $E3, $E4, $E5, $E6, $E7, $E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF,'); slHeader.Add(' $F0, $F1, $F2, $F3, $F4, $F5, $F6, $F7, $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF);'); - + slHeader.Add('var'); + slHeader.Add(' DataBlock: Array[0..$FFFF) of byte;'); + slheader.Add(' i: integer;'); slHeader.Add('begin'); + slHeader.Add(' for i := 0 to high(DataBlock) do + slHeader.Add(' DataBlock[i] := cDataBlockByte[i mod 256];'); + slHeader.Add(' asm'); slHeader.Add(' vpxord zmm0, zmm0, zmm0'); From e844f748825dc710c80277804bddfe65b90e1ec9 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 1 Feb 2021 16:16:06 +0000 Subject: [PATCH 049/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48492 - --- tests/utils/avx/asmtestgenerator.pas | 17 +++++++++++++++-- tests/utils/avx/avxopcodes.pas | 4 ++-- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index ecbd0a6694..84fff5a2dd 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3578,6 +3578,7 @@ var il_Op2: integer; il_Op3: integer; il_Op4: integer; + iAsmCounter: integer; sSuffix: string; sl_Operand: String; @@ -3736,6 +3737,8 @@ var begin result := TStringList.Create; + iAsmCounter := 0; + OItem1 := TOperandListItem.Create; try OItem2 := TOperandListItem.Create; @@ -4873,9 +4876,12 @@ begin //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); + inc(iAsmCounter); case OpMode of omKXM: begin result.Add(format('%20s%6s,%6s, %s + $00', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); + + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); result.Add(''); @@ -4894,8 +4900,15 @@ begin end; omXXM: begin result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s%6s', [' push', 'EDX'])); + result.Add(format('%20s%6s,%s', [' mov', 'EDX', str(iAsmCounter)])); + result.Add(format('%20s%6s', [' push', 'EDX'])); + result.Add(format('%20s%6s,%6s', [' kmovd', 'EDX', 'K2'])); + result.Add(format('%20s%6s,%6s', [' cmp', 'EDX', '$03'])); + result.Add(format('%20s%6s', [' pop', 'EDX'])); + result.Add(format('%20s%6s', [' jne', '@@CHECKRESULT'])); + result.Add(format('%20s%6s', [' pop', 'EDX'])); result.Add(''); end; omXXB32, diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 06354ab3a8..fd2cca74bc 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3713,12 +3713,12 @@ begin if aX64 then begin - slHeader.Add(' lea rax, cDataBlockByte'); + slHeader.Add(' lea rax, DataBlock'); slHeader.Add(' push rax'); end else begin - slHeader.Add(' lea eax, cDataBlockByte'); + slHeader.Add(' lea eax, DataBlock'); slHeader.Add(' push eax'); end; From 66cdab722370350681f7b381b815a23033ce7602 Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 2 Feb 2021 16:24:36 +0000 Subject: [PATCH 050/116] avxtestgenerator: working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48500 - --- tests/utils/avx/asmtestgenerator.pas | 24 +++++++++++++++--------- tests/utils/avx/avxopcodes.pas | 5 +++++ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 84fff5a2dd..37c48e060a 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3581,6 +3581,7 @@ var iAsmCounter: integer; sSuffix: string; + sReg: string; sl_Operand: String; sl_Inst : String; sRegCombi: String; @@ -4900,15 +4901,20 @@ begin end; omXXM: begin result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s', [' push', 'EDX'])); - result.Add(format('%20s%6s,%s', [' mov', 'EDX', str(iAsmCounter)])); - result.Add(format('%20s%6s', [' push', 'EDX'])); - result.Add(format('%20s%6s,%6s', [' kmovd', 'EDX', 'K2'])); - result.Add(format('%20s%6s,%6s', [' cmp', 'EDX', '$03'])); - result.Add(format('%20s%6s', [' pop', 'EDX'])); - result.Add(format('%20s%6s', [' jne', '@@CHECKRESULT'])); - result.Add(format('%20s%6s', [' pop', 'EDX'])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + case Fx64 of + true: sReg := 'RAX'; + else sReg := 'EAX'; + end; + + result.Add(format('%20s%6s', [' push', sReg])); + result.Add(format('%20s%6s,%s', [' mov', sReg, str(iAsmCounter)])); + result.Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); + result.Add(format('%20s%6s', [' pop', sReg])); + + result.Add(format('%20s%6s,%6s', ['kortestb', 'K1', 'K2'])); + result.Add(format('%20s%6s', [' jnc', '@@CHECKRESULT'])); result.Add(''); end; omXXB32, diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index fd2cca74bc..da4b76801a 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3722,9 +3722,14 @@ begin slHeader.Add(' push eax'); end; + for i := 1 to 10 do slHeader.Add('NOP'); + slFooter.Add(' xor eax, eax'); + slFooter.Add(' @@CHECKRESULT: '); + + if aX64 then slFooter.Add(' pop rax') else slFooter.Add(' pop eax'); From bc9629c446de8fbfec27dcd77e348adca0b1c218 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 3 Feb 2021 09:03:04 +0000 Subject: [PATCH 051/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48505 - --- tests/utils/avx/asmtestgenerator.pas | 57 ++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 37c48e060a..443d75442a 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -94,6 +94,7 @@ type procedure MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); + function ParseBaseIndexReg(const aOp: string; var aBaseReg, aIndexReg: string): boolean; function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; @@ -3589,6 +3590,9 @@ var sRegCombi2: String; sRegCombi3: String; sRegCombi4: String; + sBaseReg : String; + sIndexReg : String; + sl_Prefix: String; UsePrefix: boolean; il_Operands: integer; @@ -4900,6 +4904,11 @@ begin result.Add(''); end; omXXM: begin + if ParseBaseIndexReg(OItem3.Values[il_Op3], sBaseReg, sIndexReg) then + begin + + end; + result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); @@ -5459,6 +5468,54 @@ begin end; end; +function TAsmTestGenerator.ParseBaseIndexReg(const aOp: string; var aBaseReg, + aIndexReg: string): boolean; +var + iStartPos: integer; + iEndPos: integer; + iPos: integer; + sOp: string; + sBaseReg: string; + sIndexReg: string; +begin + result := false; + + iStartPos := Pos('[', aOp); + iEndPos := Pos(']', aOp); + + if (iStartPos > 0) and + (iEndPos > 0) and + (iStartPos < iEndPos) then + begin + sOp := trim(copy(aOp, iStartPos + 1, iEndPos - iStartPos - 1)); + + with TStringList.Create do + try + CommaText := StringReplace(sOp, '+', ',', [rfReplaceAll]); + + while Count < 2 do Add(''); + + sBaseReg := trim(Strings[0]); + + if (FReg32Base.IndexOf(sBasereg) >= 0) or + (FReg64Base.IndexOf(sBasereg) >= 0) or + (FReg6432Base.IndexOf(sBasereg) >= 0) then + aBaseReg := sBaseReg; + + sIndexReg := trim(Strings[1]); + + if (FReg32Index.IndexOf(sIndexReg) >= 0) or + (FReg64Index.IndexOf(sIndexReg) >= 0) or + (FReg6432Index.IndexOf(sIndexReg) >= 0) then + aIndexReg := sIndex; + + result := trim(aBasereg) <> ''; + finally + Free; + end; + end; +end; + class procedure TAsmTestGenerator.CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); var From c43787f7f8f30126563b9189d33f178916b47c1f Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 3 Feb 2021 16:30:41 +0000 Subject: [PATCH 052/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48506 - --- tests/utils/avx/asmtestgenerator.pas | 218 +++++++++++++++++---------- tests/utils/avx/avxopcodes.pas | 4 +- 2 files changed, 144 insertions(+), 78 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 443d75442a..8ef3afc89e 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -93,6 +93,7 @@ type FSAE: boolean; procedure MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); + procedure MemRegBaseIndexCombiCDISP8N(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); function ParseBaseIndexReg(const aOp: string; var aBaseReg, aIndexReg: string): boolean; @@ -3607,6 +3608,7 @@ var MaskRegNeeded:boolean; slRegCombi: TStringList; OpMode: TOpMode; + iOpNumMRef: integer; function PrepareOperandTyp(const aTyp: String): String; begin @@ -3739,6 +3741,25 @@ var end; end; + function AsmCodeBlockCompare(aAsmCounter: integer): String; + var + sReg: string; + begin + result := ''; + + case Fx64 of + true: sReg := 'RAX'; + else sReg := 'EAX'; + end; + + result := result + format('%20s%6s ', [' push', sReg]) + #13#10 + + format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)]) + #13#10 + + format('%20s%6s,%s', [' kmovd', 'K7', 'EAX']) + #13#10 + + format('%20s%6s', [' pop', sReg]) + #13#10 + + format('%20s%6s, %s', ['kortestb', 'K1', 'K2']) + #13#10 + + format('%20s %6s', [' jnc', '@@CHECKRESULT']) + #13#10 + #13#10; + end; + begin result := TStringList.Create; @@ -3845,8 +3866,8 @@ begin if UsePrefix then sl_Prefix := 'oword '; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'XMMRM8')) or (AnsiSameText(sl_Operand, 'XMMRM8_M')) or @@ -3860,8 +3881,8 @@ begin if UsePrefix then sl_Prefix := 'byte '; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'XMMRM16')) or (AnsiSameText(sl_Operand, 'XMMRM16_M')) or @@ -3876,8 +3897,8 @@ begin if UsePrefix then sl_Prefix := 'word '; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'YMMREG')) then begin @@ -3930,8 +3951,8 @@ begin //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'ZMMREG')) then begin @@ -3998,10 +4019,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'MEM16') or AnsiSameText(sl_Operand, 'MEM16_M') then @@ -4017,10 +4038,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'MEM32') or AnsiSameText(sl_Operand, 'MEM32_M') or @@ -4040,10 +4061,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'MEM64')) or (AnsiSameText(sl_Operand, 'MEM64_M')) or @@ -4061,10 +4082,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'MEM128')) or (AnsiSameText(sl_Operand, 'MEM128_M')) or @@ -4082,10 +4103,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'MEM256')) or (AnsiSameText(sl_Operand, 'MEM256_M')) or @@ -4104,10 +4125,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if (AnsiSameText(sl_Operand, 'MEM512')) or (AnsiSameText(sl_Operand, 'MEM512_M')) or @@ -4126,10 +4147,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'REG8') then begin @@ -4190,10 +4211,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'RM64') then begin @@ -4208,10 +4229,10 @@ begin if x64 then begin Item.Values.AddStrings(FReg64Base); - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'IMM8') then begin @@ -4452,10 +4473,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '4B32') then begin @@ -4466,10 +4487,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '8B32') then begin @@ -4480,10 +4501,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '16B32') then begin @@ -4494,10 +4515,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '2B64') then begin @@ -4508,10 +4529,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '4B64') then begin @@ -4522,10 +4543,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '8B64') then begin @@ -4536,10 +4557,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, '16B64') then begin @@ -4550,10 +4571,10 @@ begin if x64 then begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); end - else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'KREG') or AnsiSameText(sl_Operand, 'KREG_M') then @@ -4736,6 +4757,16 @@ begin begin OpMode := omUnknown; + iOpNumMRef := -1; + if (OItem1.OpTyp in MEMTYPES) or + (OItem1.OpTyp in BMEMTYPES) then iOpNumMRef := 1 + else if (OItem2.OpTyp in MEMTYPES) or + (OItem2.OpTyp in BMEMTYPES) then iOpNumMRef := 2 + else if (OItem3.OpTyp in MEMTYPES) or + (OItem3.OpTyp in BMEMTYPES) then iOpNumMRef := 3 + else if (OItem4.OpTyp in MEMTYPES) or + (OItem4.OpTyp in BMEMTYPES) then iOpNumMRef := 4; + case il_Operands of 3: if (OItem1.OpTyp = otKReg) and (OItem2.OpTyp = otXMMReg) and @@ -4878,15 +4909,32 @@ begin if sRegCombi <> '' then begin + case iOpNumMRef of + 1: sMRef := OItem1.Values[il_Op1]; + 2: sMRef := OItem2.Values[il_Op2]; + 3: sMRef := OItem3.Values[il_Op3]; + 4: sMRef := OItem1.Values[il_Op4]; + else sMRef := ''; + end; + + if ParseBaseIndexReg(OItem3.Values[il_Op3], sBaseReg, sIndexReg) then + begin + result.Add(format('%20s %s', [' pop', sBaseReg])); + result.Add(format('%20s %s', [' push', sBaseReg])); + + if trim(sIndexReg) <> '' then + result.Add(format('%20s%6s, %s', [' xor', sIndexReg, sIndexReg])); + end; + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); inc(iAsmCounter); case OpMode of omKXM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); - + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); + // TODO //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); result.Add(''); @@ -4898,48 +4946,35 @@ begin else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omXXM: begin - if ParseBaseIndexReg(OItem3.Values[il_Op3], sBaseReg, sIndexReg) then - begin - end; + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - case Fx64 of - true: sReg := 'RAX'; - else sReg := 'EAX'; - end; - - result.Add(format('%20s%6s', [' push', sReg])); - result.Add(format('%20s%6s,%s', [' mov', sReg, str(iAsmCounter)])); - result.Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); - result.Add(format('%20s%6s', [' pop', sReg])); - - result.Add(format('%20s%6s,%6s', ['kortestb', 'K1', 'K2'])); - result.Add(format('%20s%6s', [' jnc', '@@CHECKRESULT'])); - result.Add(''); + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omXXB32, omXXB64: begin sMREF := OItem3.Values[il_Op3]; + if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omXMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omYB32I, @@ -5423,6 +5458,34 @@ begin end; end; +procedure TAsmTestGenerator.MemRegBaseIndexCombiCDISP8N(const aPrefix, + aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); +var + iBase: integer; + iIndex: integer; + iOffset: integer; +begin + + for iBase := 0 to aSLBaseReg.Count - 1 do + begin + for iOffset := 0 to 63 do + begin + aRList.Add(format(aPrefix + '[%s +%2d]', [aSLBaseReg[iBase], iOffset])); + + for iIndex := 0 to aSLIndexReg.Count - 1 do + begin + if aSLBaseReg[iBase] <> aSLIndexReg[iIndex] then + begin + aRList.Add(format(aPrefix + '[%s + %s + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 2 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 4 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 8 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + end; + end; + end; + end; +end; + procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); var @@ -5480,6 +5543,9 @@ var begin result := false; + aBaseReg := ''; + aIndexReg := ''; + iStartPos := Pos('[', aOp); iEndPos := Pos(']', aOp); @@ -5507,7 +5573,7 @@ begin if (FReg32Index.IndexOf(sIndexReg) >= 0) or (FReg64Index.IndexOf(sIndexReg) >= 0) or (FReg6432Index.IndexOf(sIndexReg) >= 0) then - aIndexReg := sIndex; + aIndexReg := sIndexReg; result := trim(aBasereg) <> ''; finally diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index da4b76801a..7bc1adf155 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3694,12 +3694,12 @@ begin slHeader.Add(' $E0, $E1, $E2, $E3, $E4, $E5, $E6, $E7, $E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF,'); slHeader.Add(' $F0, $F1, $F2, $F3, $F4, $F5, $F6, $F7, $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF);'); slHeader.Add('var'); - slHeader.Add(' DataBlock: Array[0..$FFFF) of byte;'); + slHeader.Add(' DataBlock: Array[0..$FFFF] of byte;'); slheader.Add(' i: integer;'); slHeader.Add('begin'); - slHeader.Add(' for i := 0 to high(DataBlock) do + slHeader.Add(' for i := 0 to high(DataBlock) do'); slHeader.Add(' DataBlock[i] := cDataBlockByte[i mod 256];'); slHeader.Add(' asm'); From e309c47ed619cf7161ef355b4d1fa3128efaaa38 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 4 Feb 2021 04:53:13 +0000 Subject: [PATCH 053/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48508 - --- tests/utils/avx/avxopcodes.pas | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 7bc1adf155..02273b9bcd 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3676,6 +3676,8 @@ begin slHeader.Add('Program $$$OPCODE$$$;'); slHeader.Add('{$asmmode intel}'); + slHeader.Add('uses sysutils;'); + slHeader.Add('const'); slHeader.Add(' cDataBlockByte: Array[0..255] of byte = ( $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0A, $0B, $0C, $0D, $0E, $0F,'); slHeader.Add(' $10, $11, $12, $13, $14, $15, $16, $17, $18, $19, $1A, $1B, $1C, $1D, $1E, $1F,'); @@ -3694,9 +3696,13 @@ begin slHeader.Add(' $E0, $E1, $E2, $E3, $E4, $E5, $E6, $E7, $E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF,'); slHeader.Add(' $F0, $F1, $F2, $F3, $F4, $F5, $F6, $F7, $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF);'); slHeader.Add('var'); - slHeader.Add(' DataBlock: Array[0..$FFFF] of byte;'); - slheader.Add(' i: integer;'); + slHeader.Add(' DataBlock: Array[0..$3FFF] of dword;'); + slHeader.Add(' i: integer;'); + slHeader.Add('procedure writelnK7(aVal: dword);'); + slHeader.Add('begin'); + slHeader.Add(' writeln(''K7: '' + ' + 'inttostr(aVal));'); + slHeader.Add('end;'); slHeader.Add('begin'); slHeader.Add(' for i := 0 to high(DataBlock) do'); @@ -3726,15 +3732,19 @@ begin for i := 1 to 10 do slHeader.Add('NOP'); - slFooter.Add(' xor eax, eax'); + + for i := 1 to 10 do + slFooter.Add('NOP'); + slFooter.Add(' @@CHECKRESULT: '); + slFooter.Add(' kmovd eax, k7'); + slFooter.Add(' call writelnK7'); + slFooter.Add(' @@END: '); if aX64 then slFooter.Add(' pop rax') else slFooter.Add(' pop eax'); - for i := 1 to 10 do - slFooter.Add('NOP'); slFooter.Add(' end;'); slFooter.Add('end.'); From 4e151d5a6d8b1b11617cc17f3fa3e08f612efe4a Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 8 Feb 2021 11:04:21 +0000 Subject: [PATCH 054/116] bugfix 0037785 cvtsi2sd,cvtsi2ss for platform i386 git-svn-id: branches/tg74/avx512-0037785@48526 - --- compiler/i386/i386atts.inc | 4 ++-- compiler/i8086/i8086atts.inc | 4 ++-- compiler/x86/aasmcpu.pas | 16 ++++++++++------ compiler/x86/rax86.pas | 3 ++- compiler/x86/x86ins.dat | 4 ++-- compiler/x86_64/x8664ats.inc | 4 ++-- 6 files changed, 20 insertions(+), 15 deletions(-) diff --git a/compiler/i386/i386atts.inc b/compiler/i386/i386atts.inc index 63fca4b4e3..ea6ae89703 100644 --- a/compiler/i386/i386atts.inc +++ b/compiler/i386/i386atts.inc @@ -424,7 +424,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, @@ -541,7 +541,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/i8086/i8086atts.inc b/compiler/i8086/i8086atts.inc index e7bef56dda..c016aa167a 100644 --- a/compiler/i8086/i8086atts.inc +++ b/compiler/i8086/i8086atts.inc @@ -424,7 +424,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, @@ -541,7 +541,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas index eeb6044d77..e1ddf50dff 100644 --- a/compiler/x86/aasmcpu.pas +++ b/compiler/x86/aasmcpu.pas @@ -5518,13 +5518,17 @@ implementation (gas_needsuffix[AsmOp] <> AttSufNONE) and (not(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples)) then begin - // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat'); + // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat - inc(iCntOpcodeValError); - Str(gas_needsuffix[AsmOp],hs1); - Str(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize,hs2); - Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type, - std_op2str[AsmOp],hs1,hs2); + if (AsmOp <> A_CVTSI2SD) and + (AsmOp <> A_CVTSI2SS) then + begin + inc(iCntOpcodeValError); + Str(gas_needsuffix[AsmOp],hs1); + Str(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize,hs2); + Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type, + std_op2str[AsmOp],hs1,hs2); + end; end; end; end; diff --git a/compiler/x86/rax86.pas b/compiler/x86/rax86.pas index a0cfa731a0..7fbc06704c 100644 --- a/compiler/x86/rax86.pas +++ b/compiler/x86/rax86.pas @@ -2075,7 +2075,8 @@ begin end; if asize<>0 then - ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; + //ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and not OT_SIZE_MASK) or asize; + ai.oper[i-1]^.ot:=(ai.oper[i-1]^.ot and OT_NON_SIZE) or asize; end; end; OPR_REFERENCE: diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index bfa4ed2299..e30a93c7ff 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -2339,7 +2339,7 @@ xmmreg,mmxrm \331\2\x0F\x2A\110 KATMAI,SSE,MMX mmxreg,mem64 \331\2\x0F\x2D\110 KATMAI,SSE,MMX mmxreg,xmmreg \331\2\x0F\x2D\110 KATMAI,SSE,MMX -[CVTSI2SS,cvtsi2ssX] +[CVTSI2SS,cvtsi2ssS] (Ch_Wop2, Ch_Rop1) xmmreg,rm32 \333\321\2\x0F\x2A\110 KATMAI,SSE xmmreg,rm64 \333\321\2\x0F\x2A\110 KATMAI,SSE,X86_64 @@ -2878,7 +2878,7 @@ reg64,mem64 \334\320\2\x0F\x2D\110 WILLAMETTE,SSE2,X86_64 xmmreg,xmmreg \334\2\x0F\x5A\110 WILLAMETTE,SSE2 ;,SQ xmmreg,mem64 \334\2\x0F\x5A\110 WILLAMETTE,SSE2 ;,SQ -[CVTSI2SD,cvtsi2sdX] +[CVTSI2SD,cvtsi2sdS] (Ch_Wop2, Ch_Rop1) xmmreg,rm32 \334\2\x0F\x2A\110 WILLAMETTE,SSE2 xmmreg,rm64 \326\334\321\2\x0F\x2A\110 WILLAMETTE,SSE2,X86_64 diff --git a/compiler/x86_64/x8664ats.inc b/compiler/x86_64/x8664ats.inc index d68e5930ce..ac2ce4819f 100644 --- a/compiler/x86_64/x8664ats.inc +++ b/compiler/x86_64/x8664ats.inc @@ -410,7 +410,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, @@ -527,7 +527,7 @@ attsufNONE, attsufNONE, attsufNONE, attsufNONE, -attsufINT, +attsufMMS, attsufNONE, attsufNONE, attsufNONE, From dfc65acfa8a117265260964da616d70a7f4d80bf Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 10 Feb 2021 14:13:30 +0000 Subject: [PATCH 055/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48606 - --- tests/utils/avx/avxopcodes.pas | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 02273b9bcd..4468cdbcdb 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3701,13 +3701,15 @@ begin slHeader.Add('procedure writelnK7(aVal: dword);'); slHeader.Add('begin'); - slHeader.Add(' writeln(''K7: '' + ' + 'inttostr(aVal));'); + slHeader.Add(' write(''K7: '' + ' + 'inttostr(aVal));'); slHeader.Add('end;'); slHeader.Add('begin'); slHeader.Add(' for i := 0 to high(DataBlock) do'); slHeader.Add(' DataBlock[i] := cDataBlockByte[i mod 256];'); + slHeader.Add(' write(Paramstr(0) + '': '');'); + slHeader.Add(' asm'); slHeader.Add(' vpxord zmm0, zmm0, zmm0'); @@ -3747,6 +3749,7 @@ begin slFooter.Add(' end;'); + slFooter.Add(' writeln(ParamStr(0));'); slFooter.Add('end.'); end; From 3d37b958bcc1c171c66cb654aafbb5546217e7ea Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 12 Feb 2021 08:22:01 +0000 Subject: [PATCH 056/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48656 - --- tests/utils/avx/asmtestgenerator.pas | 168 +++++++++++++++++---------- tests/utils/avx/avxopcodes.pas | 13 ++- 2 files changed, 115 insertions(+), 66 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 8ef3afc89e..323708e184 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4984,23 +4984,33 @@ begin else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); end; omYYM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omYYB32, omYYB64: begin @@ -5009,22 +5019,31 @@ begin else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); end; omYMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omZB32I, omZB64I: @@ -5033,32 +5052,43 @@ begin if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); end; omZZM: begin - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; omZZB32, omZZB64: begin @@ -5066,32 +5096,42 @@ begin if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); - result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter)); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); end; omZMI: begin - result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(AsmCodeBlockCompare(iAsmCounter)); end; end; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 4468cdbcdb..1c826a0f43 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3701,9 +3701,15 @@ begin slHeader.Add('procedure writelnK7(aVal: dword);'); slHeader.Add('begin'); - slHeader.Add(' write(''K7: '' + ' + 'inttostr(aVal));'); + slHeader.Add(' writeln(''K7: '' + ' + 'inttostr(aVal));'); slHeader.Add('end;'); + slHeader.Add('procedure writelnOK;'); + slHeader.Add('begin'); + slHeader.Add(' writeln('' OK '');'); + slHeader.Add('end;'); + + slHeader.Add('begin'); slHeader.Add(' for i := 0 to high(DataBlock) do'); slHeader.Add(' DataBlock[i] := cDataBlockByte[i mod 256];'); @@ -3738,6 +3744,10 @@ begin for i := 1 to 10 do slFooter.Add('NOP'); + slFooter.Add(' call writelnOK'); + slFooter.Add(' jmp @@END'); + + slFooter.Add(' @@CHECKRESULT: '); slFooter.Add(' kmovd eax, k7'); slFooter.Add(' call writelnK7'); @@ -3749,7 +3759,6 @@ begin slFooter.Add(' end;'); - slFooter.Add(' writeln(ParamStr(0));'); slFooter.Add('end.'); end; From 8d21ab9d67d41f06f26a890ab7e346517c1f4f2d Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 12 Feb 2021 16:23:55 +0000 Subject: [PATCH 057/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48658 - --- tests/utils/avx/asmtestgenerator.pas | 42 +++++++++++++++------------- tests/utils/avx/avxopcodes.pas | 15 +++++++++- 2 files changed, 36 insertions(+), 21 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 323708e184..c8f3825de7 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3741,7 +3741,7 @@ var end; end; - function AsmCodeBlockCompare(aAsmCounter: integer): String; + function AsmCodeBlockCompare(aAsmCounter: integer; aIsKortestQ: boolean = false): String; var sReg: string; begin @@ -3752,12 +3752,21 @@ var else sReg := 'EAX'; end; - result := result + format('%20s%6s ', [' push', sReg]) + #13#10 + - format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)]) + #13#10 + - format('%20s%6s,%s', [' kmovd', 'K7', 'EAX']) + #13#10 + - format('%20s%6s', [' pop', sReg]) + #13#10 + - format('%20s%6s, %s', ['kortestb', 'K1', 'K2']) + #13#10 + - format('%20s %6s', [' jnc', '@@CHECKRESULT']) + #13#10 + #13#10; + with TStringList.Create do + try + Add(format('%20s%6s ', [' push', sReg])); + Add(format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)])); + Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); + Add(format('%20s%6s', [' pop', sReg])); + if aIsKortestQ then Add(format('%20s%6s, %s', ['kortestq', 'K1', 'K2'])) + else Add(format('%20s%6s, %s', ['kortestb', 'K1', 'K2'])); + + Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); + + result := Text; + finally + Free; + end; end; begin @@ -4583,13 +4592,7 @@ begin Item.OpTyp := otKREG; Item.OpActive := true; - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if UsePrefix then sl_Prefix := ''; - - for i := 0 to FRegKREG.Count - 1 do - Item.Values.Add(FRegKREG[i] + sSuffix); + Item.Values.Add('K1'); end else if trim(sl_Operand) = '' then begin @@ -4931,13 +4934,12 @@ begin inc(iAsmCounter); case OpMode of - omKXM: begin - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, OItem1.Values[il_Op1], 'XMM1', OItem3.Values[il_Op3] ])); + omKXM, + omKYM, + omKZM: begin + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - // TODO - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - result.Add(''); + result.Add(AsmCodeBlockCompare(iAsmCounter, true)); end; omXB32I, omXB64I: begin diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 1c826a0f43..6444137b68 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3675,6 +3675,7 @@ begin slHeader.Add('Program $$$OPCODE$$$;'); slHeader.Add('{$asmmode intel}'); + slHeader.Add('{$mode objfpc}{$H+}'); slHeader.Add('uses sysutils;'); @@ -3716,7 +3717,8 @@ begin slHeader.Add(' write(Paramstr(0) + '': '');'); - slHeader.Add(' asm'); + slHeader.Add(' try'); + slHeader.Add(' asm'); slHeader.Add(' vpxord zmm0, zmm0, zmm0'); slHeader.Add(' vpxord xmm1, xmm1, xmm1'); @@ -3758,6 +3760,17 @@ begin else slFooter.Add(' pop eax'); + slFooter.Add(' end;'); + slFooter.Add(' except'); + slFooter.Add(' on E: EInvalidOp do'); + slFooter.Add(' begin'); + slFooter.Add(' writeln(''Error - Invalid Op: '' + E.Message);'); + slFooter.Add(' end;'); + + slFooter.Add(' on E: Exception do'); + slFooter.Add(' begin'); + slFooter.Add(' writeln(''Fehler: '' + E.Message);'); + slFooter.Add(' end;'); slFooter.Add(' end;'); slFooter.Add('end.'); From 1cd0364c50e44b6d2b7d859b4e4bc556bfd3593a Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 15 Feb 2021 05:33:27 +0000 Subject: [PATCH 058/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48682 - --- tests/utils/avx/asmtestgenerator.pas | 124 +++++++++++++++++++-------- tests/utils/avx/avxopcodes.pas | 9 +- 2 files changed, 93 insertions(+), 40 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index c8f3825de7..e50d962112 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -34,8 +34,11 @@ type TOpMemType = Set of TOpType; + TAsmCompareMode = (cmKORTESTNC, cmXORTestNZ); + TOpMode = (omUnknown, omKXM, omKYM, omKZM, + omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I); @@ -3741,7 +3744,7 @@ var end; end; - function AsmCodeBlockCompare(aAsmCounter: integer; aIsKortestQ: boolean = false): String; + function AsmCodeBlockCompare(aAsmCounter: integer; aCompareMode: TAsmCompareMode): String; var sReg: string; begin @@ -3758,10 +3761,17 @@ var Add(format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)])); Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); Add(format('%20s%6s', [' pop', sReg])); - if aIsKortestQ then Add(format('%20s%6s, %s', ['kortestq', 'K1', 'K2'])) - else Add(format('%20s%6s, %s', ['kortestb', 'K1', 'K2'])); - Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); + case aComparemode of + cmKORTESTNC: begin + Add(format('%20s%6s, %s', ['kortestb', 'K1', 'K2'])); + Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); + end; + cmXORTestNZ: begin + Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); + Add(format('%20s %6s', [' jnz', '@@CHECKRESULT'])); + end; + end; result := Text; finally @@ -3993,8 +4003,8 @@ begin else if (AnsiSameText(sl_Operand, 'ZMMRM')) or (AnsiSameText(sl_Operand, 'ZMMRM_M')) or (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) + (AnsiSameText(sl_Operand, 'ZMMRM_ER')) or + (AnsiSameText(sl_Operand, 'ZMMRM_SAE')) then begin Item.OpNumber := il_Op; @@ -4010,8 +4020,8 @@ begin //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - if x64 then MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); end else if AnsiSameText(sl_Operand, 'MEM8') then begin @@ -4781,6 +4791,26 @@ begin (OItem2.OpTyp = otZMMReg) and (OItem3.OpTyp in MEMTYPES) then OpMode := omKZM + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKXB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKXB64 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKYB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKYB64 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKZB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKZB64 + + else if (OItem1.OpTyp = otXMMReg) and (OItem2.OpTyp = otXMMReg) and (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM @@ -4866,7 +4896,7 @@ begin (sLogMsg <> 'XXR') then - writeln('offen: ' + sLogMsg); + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); end; end; else; @@ -4938,53 +4968,71 @@ begin omKYM, omKZM: begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - result.Add(AsmCodeBlockCompare(iAsmCounter, true)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; + omKXB32, + omKXB64, + omKYB32, + omKYB64, + omKZB32, + omKZB64: begin + sMREF := OItem3.Values[il_Op3]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omXB32I, omXB64I: begin sMREF := OItem2.Values[il_Op2]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omXXM: begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omXXB32, omXXB64: begin sMREF := OItem3.Values[il_Op3]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omXMI: begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omYB32I, omYB64I: begin sMREF := OItem2.Values[il_Op2]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); @@ -4996,7 +5044,7 @@ begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5012,14 +5060,14 @@ begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omYYB32, omYYB64: begin sMREF := OItem3.Values[il_Op3]; - if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); @@ -5031,7 +5079,7 @@ begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omYMI: begin @@ -5045,14 +5093,14 @@ begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omZB32I, omZB64I: begin sMREF := OItem2.Values[il_Op2]; - if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); @@ -5069,7 +5117,7 @@ begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5090,13 +5138,13 @@ begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omZZB32, omZZB64: begin sMREF := OItem3.Values[il_Op3]; - if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) - else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); @@ -5114,7 +5162,7 @@ begin result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omZMI: begin @@ -5133,7 +5181,7 @@ begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; end; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 6444137b68..4644562c23 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3700,9 +3700,14 @@ begin slHeader.Add(' DataBlock: Array[0..$3FFF] of dword;'); slHeader.Add(' i: integer;'); - slHeader.Add('procedure writelnK7(aVal: dword);'); + slHeader.Add('procedure writelnK7;'); + slHeader.Add('var'); + slHeader.Add(' iK7: dword;'); slHeader.Add('begin'); - slHeader.Add(' writeln(''K7: '' + ' + 'inttostr(aVal));'); + slHeader.Add(' asm'); + slHeader.Add(' kmovd iK7, k7'); + slHeader.Add(' end;'); + slHeader.Add(' writeln(''K7: '' + ' + 'inttostr(iK7));'); slHeader.Add('end;'); slHeader.Add('procedure writelnOK;'); From 1f12cdefb98091c855b0e61d2f899204f943f0ca Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 15 Feb 2021 16:03:49 +0000 Subject: [PATCH 059/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48683 - --- tests/utils/avx/asmtestgenerator.pas | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index e50d962112..cd06f4acef 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -39,6 +39,7 @@ type TOpMode = (omUnknown, omKXM, omKYM, omKZM, omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, + omKMI, omKB32I, omKB64I, omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I); @@ -4810,6 +4811,15 @@ begin (OItem2.OpTyp = otZMMReg) and (OItem3.OpTyp = otB64) then OpMode := omKZB64 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omKMI + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omKB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omKB64I else if (OItem1.OpTyp = otXMMReg) and (OItem2.OpTyp = otXMMReg) and @@ -4950,7 +4960,7 @@ begin else sMRef := ''; end; - if ParseBaseIndexReg(OItem3.Values[il_Op3], sBaseReg, sIndexReg) then + if ParseBaseIndexReg(sMRef, sBaseReg, sIndexReg) then begin result.Add(format('%20s %s', [' pop', sBaseReg])); result.Add(format('%20s %s', [' push', sBaseReg])); @@ -4988,7 +4998,20 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; + omKMI: begin + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKB32I, + omKB64I: + begin + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; omXB32I, omXB64I: begin sMREF := OItem2.Values[il_Op2]; From e430c92fcbb5b00680ac84579d6f969a4aa1c1c4 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 22 Feb 2021 15:59:58 +0000 Subject: [PATCH 060/116] bugfix 0037785 cvtsi2ss and cvtsi2sd in x86_64 { att} git-svn-id: branches/tg74/avx512-0037785@48790 - --- compiler/ppcx64.lpi | 23 +++++++++++++---------- compiler/x86/itcpugas.pas | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/compiler/ppcx64.lpi b/compiler/ppcx64.lpi index a28f04cf21..b0969ab928 100644 --- a/compiler/ppcx64.lpi +++ b/compiler/ppcx64.lpi @@ -1,7 +1,7 @@ - + - + @@ -19,26 +19,30 @@ - - - - - + + + + + + + + + + + - - @@ -71,7 +75,6 @@ - diff --git a/compiler/x86/itcpugas.pas b/compiler/x86/itcpugas.pas index 14972b4f69..7ba8f9326c 100644 --- a/compiler/x86/itcpugas.pas +++ b/compiler/x86/itcpugas.pas @@ -73,7 +73,7 @@ interface S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,{S_NO,}S_NO,S_NO,S_IL,S_IS,S_IQ,S_NO,S_NO,S_NO,S_NO ); att_sizemmsuffix : array[0..14] of topsize = ( - S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,{S_NO,}S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_XMM,S_YMM,S_ZMM + S_NO,S_NO,S_NO,S_NO,S_NO, S_NO,{S_NO,}S_NO,S_NO,S_IL,S_NO,S_IQ,S_NO,S_XMM,S_YMM,S_ZMM ); att_sizemmxsuffix : array[0..14] of topsize = ( S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,{S_NO,}S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_XMM,S_NO,S_NO From ca0d11e308a6c64fa6494d7c904032280ec83111 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 24 Feb 2021 16:29:26 +0000 Subject: [PATCH 061/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48804 - --- tests/utils/avx/asmtestgenerator.pas | 40 +++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index cd06f4acef..9658f6defe 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -40,6 +40,7 @@ type omKXM, omKYM, omKZM, omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, omKMI, omKB32I, omKB64I, + omMXI, omMYI, omMZI, omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I); @@ -4811,16 +4812,26 @@ begin (OItem2.OpTyp = otZMMReg) and (OItem3.OpTyp = otB64) then OpMode := omKZB64 - else if (OItem1.OpTyp = otKReg) and + else if (OItem1.OpTyp = otKReg) and (OItem2.OpTyp in MEMTYPES) and (OItem3.OpTyp = otIMM8) then OpMode := omKMI - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otB32) and + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB32) and (OItem3.OpTyp = otIMM8) then OpMode := omKB32I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otB64) and + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB64) and (OItem3.OpTyp = otIMM8) then OpMode := omKB64I + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMXI + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMYI + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMZI + else if (OItem1.OpTyp = otXMMReg) and (OItem2.OpTyp = otXMMReg) and (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM @@ -4842,7 +4853,7 @@ begin else if (OItem1.OpTyp = otYMMReg) and (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM + (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM else if (OItem1.OpTyp = otYMMReg) and (OItem2.OpTyp = otYMMReg) and (OItem3.OpTyp = otB32) then OpMode := omYYB32 @@ -4969,6 +4980,13 @@ begin result.Add(format('%20s%6s, %s', [' xor', sIndexReg, sIndexReg])); end; + if OpMode in [omMXI, omMYI, omMZI] then + begin + result.Add(format('%-20s %6s', ['push', ''])); + result.Add(format('%-20s %6s', ['pop', ''])); + + end; + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); @@ -5012,6 +5030,16 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; + + omMXI: begin + result.Add(format('%20s%6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s%6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s%6s, $s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s%6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omXB32I, omXB64I: begin sMREF := OItem2.Values[il_Op2]; From 41399354ce3fdfa9683f310e168427480c01f9d1 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 25 Feb 2021 05:30:42 +0000 Subject: [PATCH 062/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48807 - --- tests/utils/avx/asmtestgenerator.pas | 105 +++++++++++++++++---------- 1 file changed, 67 insertions(+), 38 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 9658f6defe..4e223be760 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3766,7 +3766,7 @@ var case aComparemode of cmKORTESTNC: begin - Add(format('%20s%6s, %s', ['kortestb', 'K1', 'K2'])); + Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); end; cmXORTestNZ: begin @@ -4978,15 +4978,44 @@ begin if trim(sIndexReg) <> '' then result.Add(format('%20s%6s, %s', [' xor', sIndexReg, sIndexReg])); - end; - if OpMode in [omMXI, omMYI, omMZI] then - begin - result.Add(format('%-20s %6s', ['push', ''])); - result.Add(format('%-20s %6s', ['pop', ''])); + if OpMode in [omMXI, omMYI, omMZI] then + begin + case Fx64 of + true: begin + result.Add(format('%20s %6s', ['push', 'RDI'])); + result.Add(format('%20s %6s', ['push', 'RCX'])); + result.Add(format('%20s %6s', ['push', 'RAX'])); + + result.Add(format('%20s %6s', ['push', sBaseReg])); + result.Add(format('%20s %6s', ['pop', 'RDI'])); + result.Add(format('%20s %6s', ['mov', 'RCX, sizeof(DataBlock)'])); + result.Add(format('%20s %6s, %s', ['xor', 'RAX', 'RAX'])); + result.Add(format('%20s ', ['rep stosb'])); + result.Add(format('%20s %6s', ['pop', 'RAX'])); + result.Add(format('%20s %6s', ['pop', 'RCX'])); + result.Add(format('%20s %6s', ['pop', 'RDI'])); + end; + else begin + result.Add(format('%20s %6s', ['push', 'EDI'])); + result.Add(format('%20s %6s', ['push', 'ECX'])); + result.Add(format('%20s %6s', ['push', 'EAX'])); + + result.Add(format('%20s %6s', ['push', sBaseReg])); + result.Add(format('%20s %6s', ['pop', 'EDI'])); + result.Add(format('%20s %6s', ['mov', 'ECX, sizeof(DataBlock)'])); + result.Add(format('%20s %6s, %s', ['xor', 'EAX', 'EAX'])); + result.Add(format('%20s ', ['rep stosb'])); + result.Add(format('%20s %6s', ['pop', 'EAX'])); + result.Add(format('%20s %6s', ['pop', 'ECX'])); + result.Add(format('%20s %6s', ['pop', 'EDI'])); + end; + end; + end; end; + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); @@ -4995,8 +5024,8 @@ begin omKXM, omKYM, omKZM: begin - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; @@ -5011,32 +5040,32 @@ begin // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; omKMI: begin - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; omKB32I, omKB64I: begin - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; omMXI: begin - result.Add(format('%20s%6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s%6s, $s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); - result.Add(format('%20s%6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5054,8 +5083,8 @@ begin end; omXXM: begin - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5066,14 +5095,14 @@ begin // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omXMI: begin - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5108,8 +5137,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5127,8 +5156,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); @@ -5141,8 +5170,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5165,8 +5194,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); @@ -5186,8 +5215,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5210,8 +5239,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); @@ -5229,8 +5258,8 @@ begin //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); //result.Add(''); - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; From 493879d28cc1c2f76193c44458344f838ac17160 Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 1 Mar 2021 05:54:29 +0000 Subject: [PATCH 063/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48845 - --- tests/utils/avx/asmtestgenerator.pas | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 4e223be760..1e96de98f1 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4783,6 +4783,35 @@ begin (OItem4.OpTyp in BMEMTYPES) then iOpNumMRef := 4; case il_Operands of + 2: begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + if sLogMsg <> '' then + begin + //if (sLogMsg <> 'RMI') and + // (sLogMsg <> 'RRM') and + // (sLogMsg <> 'RMR') and + // (sLogMsg <> 'KKK') and + // (sLogMsg <> 'KKI') and + // (sLogMsg <> 'XXX') and + // (sLogMsg <> 'YYY') and + // (sLogMsg <> 'ZZZ') and + // (sLogMsg <> 'XXI') and + // (sLogMsg <> 'YYI') and + // (sLogMsg <> 'ZZI') and + // (sLogMsg <> 'XYI') and + // (sLogMsg <> 'YZI') and + // (sLogMsg <> 'XZI') and + // (sLogMsg <> 'RXI') and + // (sLogMsg <> 'RYI') and + // (sLogMsg <> 'RZI') and + // + // + // (sLogMsg <> 'XXR') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; 3: if (OItem1.OpTyp = otKReg) and (OItem2.OpTyp = otXMMReg) and (OItem3.OpTyp in MEMTYPES) then OpMode := omKXM @@ -5069,6 +5098,28 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + omMYI: begin + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omMZI: begin + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + + + omXB32I, omXB64I: begin sMREF := OItem2.Values[il_Op2]; From 3b408e6a6a986e8c1f0493e00e1645db3ee502ef Mon Sep 17 00:00:00 2001 From: tg74 Date: Mon, 1 Mar 2021 16:28:11 +0000 Subject: [PATCH 064/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48853 - --- tests/utils/avx/asmtestgenerator.pas | 169 ++++++++++++++++++++------- 1 file changed, 128 insertions(+), 41 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 1e96de98f1..5b05f41d1d 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -37,6 +37,11 @@ type TAsmCompareMode = (cmKORTESTNC, cmXORTestNZ); TOpMode = (omUnknown, + omMX, omMY, omMZ, + omXB32, omXB64, omYB32, omYB64, omZB32, omZB64, + omXM, omYM, omZM, + + omKXM, omKYM, omKZM, omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, omKMI, omKB32I, omKB64I, @@ -4782,34 +4787,60 @@ begin else if (OItem4.OpTyp in MEMTYPES) or (OItem4.OpTyp in BMEMTYPES) then iOpNumMRef := 4; + + // TODO delete + if il_Operands = 2 then + case il_Operands of 2: begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - if sLogMsg <> '' then - begin - //if (sLogMsg <> 'RMI') and - // (sLogMsg <> 'RRM') and - // (sLogMsg <> 'RMR') and - // (sLogMsg <> 'KKK') and - // (sLogMsg <> 'KKI') and - // (sLogMsg <> 'XXX') and - // (sLogMsg <> 'YYY') and - // (sLogMsg <> 'ZZZ') and - // (sLogMsg <> 'XXI') and - // (sLogMsg <> 'YYI') and - // (sLogMsg <> 'ZZI') and - // (sLogMsg <> 'XYI') and - // (sLogMsg <> 'YZI') and - // (sLogMsg <> 'XZI') and - // (sLogMsg <> 'RXI') and - // (sLogMsg <> 'RYI') and - // (sLogMsg <> 'RZI') and - // - // - // (sLogMsg <> 'XXR') then + if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otXMMReg) then OpMode := omMX + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otYMMReg) then OpMode := omMY + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otZMMReg) then OpMode := omMZ - writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omXB32 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omXB64 + + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omYB32 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omYB64 + + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omZB32 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omZB64 + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omXM + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omYM + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omZM + + + + + else + begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + if sLogMsg <> '' then + begin + if (sLogMsg <> 'XX') and + (sLogMsg <> 'XY') and + (sLogMsg <> 'YX') and + (sLogMsg <> 'YY') and + (sLogMsg <> 'YZ') and + (sLogMsg <> 'ZX') and + (sLogMsg <> 'ZZ') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; end; end; 3: if (OItem1.OpTyp = otKReg) and @@ -5089,6 +5120,16 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; + omMX: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omMXI: begin result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); @@ -5096,6 +5137,16 @@ begin result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omMY: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omMYI: begin @@ -5107,6 +5158,17 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + + omMZ: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omMZI: begin result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); @@ -5117,7 +5179,14 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + omXB32, + omXB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omXB32I, @@ -5130,6 +5199,13 @@ begin result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omXM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; omXXM: begin @@ -5159,25 +5235,31 @@ begin end; omYB32I, - omYB64I: begin - sMREF := OItem2.Values[il_Op2]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + omYB64I: + begin + sMREF := OItem2.Values[il_Op2]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - end; + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omYYM: begin //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); @@ -5251,7 +5333,12 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + omZM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omZZM: begin //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); From 0569ab4a2859d1e5ff60e996deaa0bcf2fff737c Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 2 Mar 2021 16:30:31 +0000 Subject: [PATCH 065/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48870 - --- tests/utils/avx/asmtestgenerator.pas | 39 ++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 5b05f41d1d..f000467c29 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4831,12 +4831,26 @@ begin sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); if sLogMsg <> '' then begin - if (sLogMsg <> 'XX') and + + if (sLogMsg <> 'KX') and + (sLogMsg <> 'KY') and + (sLogMsg <> 'KZ') and + (sLogMsg <> 'RM') and + (sLogMsg <> 'RX') and + (sLogMsg <> 'XK') and + (sLogMsg <> 'XR') and + (sLogMsg <> 'XX') and (sLogMsg <> 'XY') and + (sLogMsg <> 'XZ') and + (sLogMsg <> 'YK') and + (sLogMsg <> 'YR') and (sLogMsg <> 'YX') and (sLogMsg <> 'YY') and (sLogMsg <> 'YZ') and + (sLogMsg <> 'ZK') and + (sLogMsg <> 'ZR') and (sLogMsg <> 'ZX') and + (sLogMsg <> 'ZY') and (sLogMsg <> 'ZZ') then writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); @@ -5234,6 +5248,14 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + omYB32, + omYB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'YMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omYB32I, omYB64I: begin @@ -5308,6 +5330,15 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + + omZB32, + omZB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'ZMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; omZB32I, omZB64I: begin @@ -5401,7 +5432,11 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; - + else begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); + end; end; sRegCombi := ''; From fa8bbc43960c51ef1fa09ef630ab53c08e76ea29 Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 3 Mar 2021 05:26:29 +0000 Subject: [PATCH 066/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48872 - --- tests/utils/avx/asmtestgenerator.pas | 115 ++++++++++++++++++++++++++- 1 file changed, 112 insertions(+), 3 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index f000467c29..5b03a6908d 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -44,11 +44,17 @@ type omKXM, omKYM, omKZM, omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, + omKXB32I, omKXB64I, omKXMI, omKYB32I, omKYB64I, omKYMI, omKZB32I, omKZB64I, omKZMI, + omKMI, omKB32I, omKB64I, omMXI, omMYI, omMZI, omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, + omXXMI, omXXB32I, omXXB64I, + omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, - omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I); + omYYMI, omYYB32I, omYYB64I, + omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I, + omZZMI, omZZB32I, omZZB64I); TOperandListItem = class(TObject) private @@ -4789,7 +4795,7 @@ begin // TODO delete - if il_Operands = 2 then + if il_Operands = 4 then case il_Operands of 2: begin @@ -4994,6 +5000,102 @@ begin writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); end; end; + 4: if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXMI + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYMI + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZMI + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXB32I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXB64I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYB32I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYB64I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZB32I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZB64I + + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXMI + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYMI + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZMI + else + begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp) + MapOperand(OItem4.Optyp); + if sLogMsg <> '' then + begin + + if (sLogMsg <> 'KXXI') and + (sLogMsg <> 'KYYI') and + (sLogMsg <> 'KZZI') and + (sLogMsg <> 'XXRI') and + (sLogMsg <> 'XXXI') and + (sLogMsg <> 'YYYI') and + (sLogMsg <> 'ZZZI') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; + else; end; @@ -5432,10 +5534,17 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; + + omKXB32I, omKXB64I, omKXMI, omKYB32I, omKYB64I, omKYMI, omKZB32I, omKZB64I, omKZMI:; + omXXMI, omXXB32I, omXXB64I:; + omYYMI, omYYB32I, omYYB64I:; + omZZMI, omZZB32I, omZZB64I:; + + else begin sLogMsg := ''; sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); + //writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); end; end; From bc42999a09d3acb45eb1b3daf3a2223e828f93ff Mon Sep 17 00:00:00 2001 From: tg74 Date: Wed, 3 Mar 2021 16:27:21 +0000 Subject: [PATCH 067/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48873 - --- tests/utils/avx/asmtestgenerator.pas | 103 ++++++++++++++++++++++++--- 1 file changed, 94 insertions(+), 9 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 5b03a6908d..254cf49e24 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -5535,17 +5535,102 @@ begin result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; - omKXB32I, omKXB64I, omKXMI, omKYB32I, omKYB64I, omKYMI, omKZB32I, omKZB64I, omKZMI:; - omXXMI, omXXB32I, omXXB64I:; - omYYMI, omYYB32I, omYYB64I:; - omZZMI, omZZB32I, omZZB64I:; + omKXB32I, + omKXB64I: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - else begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - //writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); end; + omKXMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKYB32I, + omKYB64I: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKYMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + + omXXB32I, + omXXB64I: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omXXMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYYB32I, + omYYB64I, + omYYMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omKZB32I, + omKZB64I, + omKZMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + //omKZMI: + // begin + // sMREF := OItem3.Values[il_Op3]; + // + // result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + // result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + // + // result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + // end; + + omZZB32I, + omZZB64I, + omZZMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + else begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); + end; end; sRegCombi := ''; From 798eb0e768dee97be6c729e35445765dbedb7d36 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 4 Mar 2021 05:47:14 +0000 Subject: [PATCH 068/116] avxtestgenerator: working on new tests for compressed disp8*N git-svn-id: branches/tg74/avx512-0037785@48875 - --- tests/utils/avx/asmtestgenerator.pas | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 254cf49e24..ae725419fa 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -4795,7 +4795,7 @@ begin // TODO delete - if il_Operands = 4 then + //if il_Operands = 4 then case il_Operands of 2: begin @@ -5571,8 +5571,8 @@ begin begin sMREF := OItem3.Values[il_Op3]; - result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5580,8 +5580,8 @@ begin begin sMREF := OItem3.Values[il_Op3]; - result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5591,8 +5591,8 @@ begin begin sMREF := OItem3.Values[il_Op3]; - result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5609,8 +5609,8 @@ begin // begin // sMREF := OItem3.Values[il_Op3]; // - // result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - // result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + // result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + // result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); // // result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); // end; @@ -5621,8 +5621,8 @@ begin begin sMREF := OItem3.Values[il_Op3]; - result.Add(format('%20s %6s, %6, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; From 5d3faa5ebd1f1d4acbf58d563b5b38c9a4ae6cf1 Mon Sep 17 00:00:00 2001 From: tg74 Date: Thu, 4 Mar 2021 15:54:43 +0000 Subject: [PATCH 069/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48877 - --- tests/utils/avx/asmtestgenerator.pas | 6407 -------------------------- 1 file changed, 6407 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index ae725419fa..e69de29bb2 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -1,6407 +0,0 @@ -{ - - Copyright (C) - - This source is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License as published by the Free - Software Foundation; either version 2 of the License, or (at your option) - any later version. - - This code is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - details. - - A copy of the GNU General Public License is available on the World Wide Web - at . You can also obtain it by writing - to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - MA 02110-1301, USA. -} - -{$mode objfpc} - -unit asmtestgenerator; - -interface - -uses BaseList, Classes; - -type - TOpType = (otUnknown, otXMMReg, otXMMRM, otXMMRM16, otXMMRM8, otYMMReg, otYMMRM, otZMMReg, otZMMRM, otEAX, otRAX, otMem32, - otMem8, otMem16, otMem64, otMem128, otMem256, otMem512, otREG64, otREG32, otREG16, otREG8, otRM32, otRM64, otIMM8, - otXMEM32, otXMEM64, otYMEM32, otYMEM64, otZMEM32, otZMEM64, - otB32, otB64, otKREG); - - TOpMemType = Set of TOpType; - - TAsmCompareMode = (cmKORTESTNC, cmXORTestNZ); - - TOpMode = (omUnknown, - omMX, omMY, omMZ, - omXB32, omXB64, omYB32, omYB64, omZB32, omZB64, - omXM, omYM, omZM, - - - omKXM, omKYM, omKZM, - omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, - omKXB32I, omKXB64I, omKXMI, omKYB32I, omKYB64I, omKYMI, omKZB32I, omKZB64I, omKZMI, - - omKMI, omKB32I, omKB64I, - omMXI, omMYI, omMZI, - omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, - omXXMI, omXXB32I, omXXB64I, - - omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, - omYYMI, omYYB32I, omYYB64I, - omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I, - omZZMI, omZZB32I, omZZB64I); - - TOperandListItem = class(TObject) - private - FOpActive: boolean; - FOpNumber: integer; - FOpTyp: TOpType; - FValues: TStringList; - public - constructor Create; - destructor Destroy; override; - - property OpNumber: integer read FOpNumber write FOpNumber; - property OpTyp: TOpType read FOpTyp write FOpTyp; - property OpActive: boolean read FOpActive write FOpActive; - - property Values: TStringList read FValues; - end; - - TOperandList = class(TBaseList) - private - function GetItems(aIndex: integer): TOperandListItem; - - public - function Add(aItem: TOperandListItem): integer; - - property Items[aIndex: integer]: TOperandListItem read GetItems; - end; - - - { TAsmTestGenerator } - - TAsmTestGenerator = class(TObject) - private - FReg8 : TStringList; - FReg16 : TStringList; - FReg32Base : TStringList; - FReg32Index : TStringList; - FReg64Base : TStringList; - FReg64Index : TStringList; - FReg6432Base : TStringList; - FReg6432Index : TStringList; - FReg32XMMIndex : TStringList; - FReg32YMMIndex : TStringList; - FReg32ZMMIndex : TStringList; - FReg64XMMIndex : TStringList; - FReg64YMMIndex : TStringList; - FReg64ZMMIndex : TStringList; - FRegKREG : TStringList; - - Fx64: boolean; - FAVX512: boolean; - FSAE: boolean; - - procedure MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); - procedure MemRegBaseIndexCombiCDISP8N(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); - procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); - function ParseBaseIndexReg(const aOp: string; var aBaseReg, aIndexReg: string): boolean; - - function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; - function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; - function InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; - public - constructor Create; - destructor Destroy; override; - - class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); - class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); - class procedure CalcTestDataCDisp8(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); - - - class procedure CalcTestInstFile; - class procedure ListMemRefState; - - property x64: boolean read Fx64; - end; - -implementation - -uses SysUtils, Dialogs, typinfo; - -type - TAsmOp={$i ../../../compiler/x86_64/x8664op.inc} - TAttSuffix = (AttSufNONE,AttSufINT,AttSufFPU,AttSufFPUint,AttSufINTdual,AttSufMM,AttSufMMX,AttSufMMS); - - TMemRefSizeInfo = (msiUnknown, msiUnsupported, msiNoSize, msiNoMemRef, - msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, - msiMultipleMinSize64, msiMultipleMinSize128, msiMultipleminSize256, msiMultipleMinSize512, - msiMemRegSize, msiMemRegx16y32, msiMemRegx16y32z64, msiMemRegx32y64, msiMemRegx32y64z128, msiMemRegx64y128, msiMemRegx64y128z256, - msiMemRegx64y256, msiMemRegx64y256z512, - msiMem8, msiMem16, msiMem32, msiBMem32, msiMem64, msiBMem64, msiMem128, msiMem256, msiMem512, - msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64, - msiVMemMultiple, msiVMemRegSize, - msiMemRegConst128,msiMemRegConst256,msiMemRegConst512); - - TMemRefSizeInfoBCST = (msbUnknown, msbBCST32, msbBCST64, msbMultiple); - TMemRefSizeInfoBCSTType = (btUnknown, bt1to2, bt1to4, bt1to8, bt1to16); - - TEVEXTupleState = (etsUnknown, etsIsTuple, etsNotTuple); - TConstSizeInfo = (csiUnknown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64); - - - TInsTabMemRefSizeInfoRec = record - MemRefSize : TMemRefSizeInfo; - MemRefSizeBCST : TMemRefSizeInfoBCST; - BCSTXMMMultiplicator : byte; - ExistsSSEAVX : boolean; - ConstSize : TConstSizeInfo; - BCSTTypes : Set of TMemRefSizeInfoBCSTType; - RegXMMSizeMask : int64; - RegYMMSizeMask : int64; - RegZMMSizeMask : int64; - end; - - - TInsTabMemRefSizeInfoCache=array[TasmOp] of TInsTabMemRefSizeInfoRec; - PInsTabMemRefSizeInfoCache=^TInsTabMemRefSizeInfoCache; - - TInsTabCache=array[TasmOp] of longint; - PInsTabCache=^TInsTabCache; - - -const - instabentries = {$i ../../../compiler/x86_64/x8664nop.inc} - gas_needsuffix:array[tasmop] of TAttSuffix={$i ../../../compiler/x86_64/x8664ats.inc} - - MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultipleMinSize8, - msiMultipleMinSize16, msiMultipleMinSize32, - msiMultipleMinSize64, msiMultipleMinSize128, - msiMultipleMinSize256, msiMultipleMinSize512, - msiVMemMultiple]; - - MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64, - msiZMem32, msiZMem64, - msiVMemMultiple, msiVMemRegSize]; - - MEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, - otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, - otRM32, otRM64]; - BMEMTYPES: TOpMemType = [otB32, otB64]; - -var - InsTabCache : PInsTabCache; - InsTabMemRefSizeInfoCache: PInsTabMemRefSizeInfoCache; - -type - - - op2strtable=array[tasmop] of string[16]; - - {Instruction flags } - tinsflag = ( - { please keep these in order and in sync with IF_SMASK } - IF_SM, { size match first two operands } - IF_SM2, - IF_SB, { unsized operands can't be non-byte } - IF_SW, { unsized operands can't be non-word } - IF_SD, { unsized operands can't be nondword } - - { unsized argument spec } - { please keep these in order and in sync with IF_ARMASK } - IF_AR0, { SB, SW, SD applies to argument 0 } - IF_AR1, { SB, SW, SD applies to argument 1 } - IF_AR2, { SB, SW, SD applies to argument 2 } - - IF_PRIV, { it's a privileged instruction } - IF_SMM, { it's only valid in SMM } - IF_PROT, { it's protected mode only } - IF_NOX86_64, { removed instruction in x86_64 } - IF_UNDOC, { it's an undocumented instruction } - IF_FPU, { it's an FPU instruction } - IF_MMX, { it's an MMX instruction } - { it's a 3DNow! instruction } - IF_3DNOW, - { it's a SSE (KNI, MMX2) instruction } - IF_SSE, - { SSE2 instructions } - IF_SSE2, - { SSE3 instructions } - IF_SSE3, - { SSE64 instructions } - IF_SSE64, - { SVM instructions } - IF_SVM, - { SSE4 instructions } - IF_SSE4, - IF_SSSE3, - IF_SSE41, - IF_SSE42, - IF_MOVBE, - IF_CLMUL, - IF_AVX, - IF_AVX2, - IF_AVX512, - IF_BMI1, - IF_BMI2, - { Intel ADX (Multi-Precision Add-Carry Instruction Extensions) } - IF_ADX, - IF_16BITONLY, - IF_FMA, - IF_FMA4, - IF_TSX, - IF_RAND, - IF_XSAVE, - IF_PREFETCHWT1, - - { mask for processor level } - { please keep these in order and in sync with IF_PLEVEL } - IF_8086, { 8086 instruction } - IF_186, { 186+ instruction } - IF_286, { 286+ instruction } - IF_386, { 386+ instruction } - IF_486, { 486+ instruction } - IF_PENT, { Pentium instruction } - IF_P6, { P6 instruction } - IF_KATMAI, { Katmai instructions } - IF_WILLAMETTE, { Willamette instructions } - IF_PRESCOTT, { Prescott instructions } - IF_X86_64, - IF_SANDYBRIDGE, { Sandybridge-specific instruction } - IF_NEC, { NEC V20/V30 instruction } - - { the following are not strictly part of the processor level, because - they are never used standalone, but always in combination with a - separate processor level flag. Therefore, they use bits outside of - IF_PLEVEL, otherwise they would mess up the processor level they're - used in combination with. - The following combinations are currently used: - [IF_AMD, IF_P6], - [IF_CYRIX, IF_486], - [IF_CYRIX, IF_PENT], - [IF_CYRIX, IF_P6] } - IF_CYRIX, { Cyrix, Centaur or VIA-specific instruction } - IF_AMD, { AMD-specific instruction } - - { added flags } - IF_PRE, { it's a prefix instruction } - IF_PASS2, { if the instruction can change in a second pass } - IF_IMM4, { immediate operand is a nibble (must be in range [0..15]) } - IF_IMM3, { immediate operand is a triad (must be in range [0..7]) } - - IF_BCST2, - IF_BCST4, - IF_BCST8, - IF_BCST16, - IF_T2, { disp8 - tuple - 2 } - IF_T4, { disp8 - tuple - 4 } - IF_T8, { disp8 - tuple - 8 } - IF_T1S, { disp8 - tuple - 1 scalar } - IF_T1S8, - IF_T1S16, - IF_T1F32, - IF_T1F64, - IF_TMDDUP, - IF_TFV, { disp8 - tuple - full vector } - IF_TFVM, { disp8 - tuple - full vector memory } - IF_TQVM, - IF_TMEM128, - IF_THV, - IF_THVM, - IF_TOVM, - - IF_SCL32, - IF_SCL64 - - - ); - tinsflags=set of tinsflag; - - - tinsentry=packed record - opcode : tasmop; - ops : byte; - //optypes : array[0..max_operands-1] of longint; - optypes : array[0..3] of int64; //TG - code : array[0..11] of char; - flags : tinsflags; - end; - pinsentry=^tinsentry; - -const - OT_NONE = $00000000; - - { Bits 0..7: sizes } - OT_BITS8 = $00000001; - OT_BITS16 = $00000002; - OT_BITS32 = $00000004; - OT_BITS64 = $00000008; { x86_64 and FPU } - //OT_BITS128 = $10000000; { 16 byte SSE } - //OT_BITS256 = $20000000; { 32 byte AVX } - //OT_BITS512 = $40000000; { 64 byte AVX512 } - OT_BITS128 = $20000000; { 16 byte SSE } - OT_BITS256 = $40000000; { 32 byte AVX } - OT_BITS512 = $80000000; { 64 byte AVX512 } - - OT_VECTORMASK = $1000000000; { OPTIONAL VECTORMASK AVX512} - OT_VECTORZERO = $2000000000; { OPTIONAL ZERO-FLAG AVX512} - OT_VECTORBCST = $4000000000; { BROADCAST-MEM-FLAG AVX512} - OT_VECTORSAE = $8000000000; { OPTIONAL SAE-FLAG AVX512} - OT_VECTORER = $10000000000; { OPTIONAL ER-FLAG-FLAG AVX512} - - - OT_BITSB32 = OT_BITS32 or OT_VECTORBCST; - OT_BITSB64 = OT_BITS64 or OT_VECTORBCST; - - - OT_VECTOR_EXT_MASK = OT_VECTORMASK or OT_VECTORZERO or OT_VECTORBCST; - - OT_BITS80 = $00000010; { FPU only } - OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP } - OT_NEAR = $00000040; - OT_SHORT = $00000080; - - { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask, - but this requires adjusting the opcode table } - //OT_SIZE_MASK = $3000001F; { all the size attributes } - OT_SIZE_MASK = $E000001F; { all the size attributes } - OT_NON_SIZE = int64(not int64(OT_SIZE_MASK)); - - { Bits 8..11: modifiers } - OT_SIGNED = $00000100; { the operand need to be signed -128-127 } - OT_TO = $00000200; { reverse effect in FADD, FSUB &c } - OT_COLON = $00000400; { operand is followed by a colon } - OT_MODIFIER_MASK = $00000F00; - - { Bits 12..15: type of operand } - OT_REGISTER = $00001000; - OT_IMMEDIATE = $00002000; - OT_MEMORY = $0000C000; { always includes 'OT_REGMEM' bit as well } - OT_REGMEM = $00008000; { for r/m, ie EA, operands } - OT_TYPE_MASK = OT_REGISTER or OT_IMMEDIATE or OT_MEMORY or OT_REGMEM; - - OT_REGNORM = OT_REGISTER or OT_REGMEM; { 'normal' reg, qualifies as EA } - - { Bits 20..22, 24..26: register classes - otf_* consts are not used alone, only to build other constants. } - otf_reg_cdt = $00100000; - otf_reg_gpr = $00200000; - otf_reg_sreg = $00400000; - otf_reg_k = $00800000; - otf_reg_fpu = $01000000; - otf_reg_mmx = $02000000; - otf_reg_xmm = $04000000; - otf_reg_ymm = $08000000; - otf_reg_zmm = $10000000; - - - otf_reg_extra_mask = $0F000000; - { Bits 16..19: subclasses, meaning depends on classes field } - otf_sub0 = $00010000; - otf_sub1 = $00020000; - otf_sub2 = $00040000; - otf_sub3 = $00080000; - OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3; - - //OT_REG_EXTRA_MASK = $0F000000; - OT_REG_EXTRA_MASK = $1F000000; - - OT_REG_TYPMASK = otf_reg_cdt or otf_reg_gpr or otf_reg_sreg or otf_reg_k or otf_reg_extra_mask; - { register class 0: CRx, DRx and TRx } - OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS64; - OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn } - OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn } - OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn } - OT_REG_CR4 = OT_REG_CDT or otf_sub3; { CR4 (Pentium only) } - - { register class 1: general-purpose registers } - OT_REG_GPR = OT_REGNORM or otf_reg_gpr; - OT_RM_GPR = OT_REGMEM or otf_reg_gpr; - OT_REG8 = OT_REG_GPR or OT_BITS8; { 8-bit GPR } - OT_REG16 = OT_REG_GPR or OT_BITS16; - OT_REG32 = OT_REG_GPR or OT_BITS32; - OT_REG64 = OT_REG_GPR or OT_BITS64; - - { GPR subclass 0: accumulator: AL, AX, EAX or RAX } - OT_REG_ACCUM = OT_REG_GPR or otf_sub0; - OT_REG_AL = OT_REG_ACCUM or OT_BITS8; - OT_REG_AX = OT_REG_ACCUM or OT_BITS16; - OT_REG_EAX = OT_REG_ACCUM or OT_BITS32; - OT_REG_RAX = OT_REG_ACCUM or OT_BITS64; - { GPR subclass 1: counter: CL, CX, ECX or RCX } - OT_REG_COUNT = OT_REG_GPR or otf_sub1; - OT_REG_CL = OT_REG_COUNT or OT_BITS8; - OT_REG_CX = OT_REG_COUNT or OT_BITS16; - OT_REG_ECX = OT_REG_COUNT or OT_BITS32; - OT_REG_RCX = OT_REG_COUNT or OT_BITS64; - { GPR subclass 2: data register: DL, DX, EDX or RDX } - OT_REG_DX = OT_REG_GPR or otf_sub2 or OT_BITS16; - OT_REG_EDX = OT_REG_GPR or otf_sub2 or OT_BITS32; - - { register class 2: Segment registers } - OT_REG_SREG = OT_REGISTER or otf_reg_sreg or OT_BITS16; - OT_REG_CS = OT_REG_SREG or otf_sub0; { CS } - OT_REG_DESS = OT_REG_SREG or otf_sub1; { DS, ES, SS (non-CS 86 registers) } - OT_REG_FSGS = OT_REG_SREG or otf_sub2; { FS, GS (386 extended registers) } - - { register class 3: FPU registers } - OT_FPUREG = OT_REGISTER or otf_reg_fpu; - OT_FPU0 = OT_FPUREG or otf_sub0; { FPU stack register zero } - - { register class 4: MMX (both reg and r/m) } - OT_MMXREG = OT_REGNORM or otf_reg_mmx; - OT_MMXRM = OT_REGMEM or otf_reg_mmx; - - { register class 5: XMM (both reg and r/m) } - OT_XMMREG = OT_REGNORM or otf_reg_xmm; - OT_XMMRM = OT_REGMEM or otf_reg_xmm; - OT_XMEM32 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS32; - OT_XMEM32_M = OT_XMEM32 or OT_VECTORMASK; - OT_XMEM64 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS64; - OT_XMEM64_M = OT_XMEM64 or OT_VECTORMASK; - - OT_XMMREG_M = OT_XMMREG or OT_VECTORMASK; - OT_XMMREG_MZ = OT_XMMREG or OT_VECTORMASK or OT_VECTORZERO; - OT_XMMRM_MZ = OT_XMMRM or OT_VECTORMASK or OT_VECTORZERO; - OT_XMMREG_SAE = OT_XMMREG or OT_VECTORSAE; - OT_XMMRM_SAE = OT_XMMRM or OT_VECTORSAE; - OT_XMMREG_ER = OT_XMMREG or OT_VECTORER; - OT_XMMRM_ER = OT_XMMRM or OT_VECTORER; - - - - { register class 5: YMM (both reg and r/m) } - OT_YMMREG = OT_REGNORM or otf_reg_ymm; - OT_YMMRM = OT_REGMEM or otf_reg_ymm; - OT_YMEM32 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS32; - OT_YMEM32_M = OT_YMEM32 or OT_VECTORMASK; - OT_YMEM64 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS64; - OT_YMEM64_M = OT_YMEM64 or OT_VECTORMASK; - - OT_YMMREG_M = OT_YMMREG or OT_VECTORMASK; - OT_YMMREG_MZ = OT_YMMREG or OT_VECTORMASK or OT_VECTORZERO; - OT_YMMRM_MZ = OT_YMMRM or OT_VECTORMASK or OT_VECTORZERO; - OT_YMMREG_SAE = OT_YMMREG or OT_VECTORSAE; - OT_YMMRM_SAE = OT_YMMRM or OT_VECTORSAE; - OT_YMMREG_ER = OT_YMMREG or OT_VECTORER; - OT_YMMRM_ER = OT_YMMRM or OT_VECTORER; - - - { register class 5: ZMM (both reg and r/m) } - OT_ZMMREG = OT_REGNORM or otf_reg_zmm; - OT_ZMMRM = OT_REGMEM or otf_reg_zmm; - OT_ZMEM32 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS32; - OT_ZMEM32_M = OT_ZMEM32 or OT_VECTORMASK; - OT_ZMEM64 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS64; - OT_ZMEM64_M = OT_ZMEM64 or OT_VECTORMASK; - - OT_ZMMREG_M = OT_ZMMREG or OT_VECTORMASK; - OT_ZMMREG_MZ = OT_ZMMREG or OT_VECTORMASK or OT_VECTORZERO; - OT_ZMMRM_MZ = OT_ZMMRM or OT_VECTORMASK or OT_VECTORZERO; - OT_ZMMREG_SAE = OT_ZMMREG or OT_VECTORSAE; - OT_ZMMRM_SAE = OT_ZMMRM or OT_VECTORSAE; - OT_ZMMREG_ER = OT_ZMMREG or OT_VECTORER; - OT_ZMMRM_ER = OT_ZMMRM or OT_VECTORER; - - - OT_KREG = OT_REGNORM or otf_reg_k; - OT_KREG_M = OT_KREG or OT_VECTORMASK; - - { Vector-Memory operands } - OT_VMEM_ANY = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64 or OT_ZMEM32 or OT_ZMEM64; - - { Memory operands } - OT_MEM8 = OT_MEMORY or OT_BITS8; - OT_MEM16 = OT_MEMORY or OT_BITS16; - OT_MEM16_M = OT_MEM16 or OT_VECTORMASK; - OT_MEM32 = OT_MEMORY or OT_BITS32; - OT_MEM32_M = OT_MEMORY or OT_BITS32 or OT_VECTORMASK; - OT_BMEM32 = OT_MEMORY or OT_BITS32 or OT_VECTORBCST; - OT_BMEM32_SAE= OT_MEMORY or OT_BITS32 or OT_VECTORBCST or OT_VECTORSAE; - OT_MEM64 = OT_MEMORY or OT_BITS64; - OT_MEM64_M = OT_MEMORY or OT_BITS64 or OT_VECTORMASK; - OT_BMEM64 = OT_MEMORY or OT_BITS64 or OT_VECTORBCST; - OT_BMEM64_SAE= OT_MEMORY or OT_BITS64 or OT_VECTORBCST or OT_VECTORSAE; - OT_MEM128 = OT_MEMORY or OT_BITS128; - OT_MEM128_M = OT_MEMORY or OT_BITS128 or OT_VECTORMASK; - OT_MEM256 = OT_MEMORY or OT_BITS256; - OT_MEM256_M = OT_MEMORY or OT_BITS256 or OT_VECTORMASK; - OT_MEM512 = OT_MEMORY or OT_BITS512; - OT_MEM512_M = OT_MEMORY or OT_BITS512 or OT_VECTORMASK; - OT_MEM80 = OT_MEMORY or OT_BITS80; - - - - - OT_MEM_OFFS = OT_MEMORY or otf_sub0; { special type of EA } - { simple [address] offset } - - { Matches any type of r/m operand } - OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK; - - { Immediate operands } - OT_IMM8 = OT_IMMEDIATE or OT_BITS8; - OT_IMM16 = OT_IMMEDIATE or OT_BITS16; - OT_IMM32 = OT_IMMEDIATE or OT_BITS32; - OT_IMM64 = OT_IMMEDIATE or OT_BITS64; - - OT_ONENESS = otf_sub0; { special type of immediate operand } - OT_UNITY = OT_IMMEDIATE or OT_ONENESS; { for shift/rotate instructions } - - std_op2str:op2strtable={$i ../../../compiler/x86_64/x8664int.inc} - - InsTab:array[0..instabentries-1] of TInsEntry={$i ../../../compiler/x86_64/x8664tab.inc} - - procedure BuildInsTabCache; - var - i : longint; - begin - new(instabcache); - FillChar(instabcache^,sizeof(tinstabcache),$ff); - i:=0; - while (i= 0 then - begin - - - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbUnknown; - InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 0; - InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; - InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := false; - InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := []; - - insentry:=@instab[i]; - - RegMMXSizeMask := 0; - RegXMMSizeMask := 0; - RegYMMSizeMask := 0; - RegZMMSizeMask := 0; - - RegMMXConstSizeMask := 0; - RegXMMConstSizeMask := 0; - RegYMMConstSizeMask := 0; - RegZMMConstSizeMask := 0; - - RegBCSTSizeMask:= 0; - RegBCSTXMMSizeMask := 0; - RegBCSTYMMSizeMask := 0; - RegBCSTZMMSizeMask := 0; - ExistsMemRef := false; - - while (insentry^.opcode=AsmOp) do - begin - MRefInfo := msiUnknown; - - actRegSize := 0; - actRegCount := 0; - actRegTypes := 0; - NewRegSize := 0; - - actMemSize := 0; - actMemCount := 0; - actRegMemTypes := 0; - - actVMemCount := 0; - actVMemTypes := 0; - - actConstSize := 0; - actConstCount := 0; - - ExistsCode336 := false; // indicate fixed operand size 32 bit - ExistsCode337 := false; // indicate fixed operand size 64 bit - ExistsSSEAVXReg := false; - - // parse insentry^.code for &336 and &337 - // &336 (octal) = 222 (decimal) == fixed operand size 32 bit - // &337 (octal) = 223 (decimal) == fixed operand size 64 bit - for i := low(insentry^.code) to high(insentry^.code) do - begin - case insentry^.code[i] of - #222: ExistsCode336 := true; - #223: ExistsCode337 := true; - #0,#1,#2,#3: break; - end; - end; - - for i := 0 to insentry^.ops -1 do - begin - if (insentry^.optypes[i] and OT_REGISTER) = OT_REGISTER then - case insentry^.optypes[i] and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of - OT_XMMREG, - OT_YMMREG, - OT_ZMMREG: ExistsSSEAVXReg := true; - else; - end; - end; - - - for j := 0 to insentry^.ops -1 do - begin - if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR - ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR - ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR - ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) OR - ((insentry^.optypes[j] and OT_ZMEM32) = OT_ZMEM32) OR - ((insentry^.optypes[j] and OT_ZMEM64) = OT_ZMEM64) then - begin - inc(actVMemCount); - - case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64 OR OT_ZMEM32 OR OT_ZMEM64) of - OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32; - OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64; - OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32; - OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64; - OT_ZMEM32: actVMemTypes := actVMemTypes or OT_ZMEM32; - OT_ZMEM64: actVMemTypes := actVMemTypes or OT_ZMEM64; - else; - end; - end - else if (insentry^.optypes[j] and OT_REGISTER) = OT_REGISTER then - begin - inc(actRegCount); - - NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK); - if NewRegSize = 0 then - begin - case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of - OT_MMXREG: begin - NewRegSize := OT_BITS64; - end; - OT_XMMREG: begin - NewRegSize := OT_BITS128; - InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; - end; - OT_YMMREG: begin - NewRegSize := OT_BITS256; - InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; - end; - OT_ZMMREG: begin - NewRegSize := OT_BITS512; - InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; - end; - OT_KREG: begin - InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; - end; - - else NewRegSize := not(0); - end; - end; - - actRegSize := actRegSize or NewRegSize; - actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK)); - end - else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then - begin - inc(actMemCount); - - - if ExistsSSEAVXReg and ExistsCode336 then - actMemSize := actMemSize or OT_BITS32 - else if ExistsSSEAVXReg and ExistsCode337 then - actMemSize := actMemSize or OT_BITS64 - else - actMemSize:=actMemSize or (insentry^.optypes[j] and (OT_SIZE_MASK OR OT_VECTORBCST)); - - if (insentry^.optypes[j] and OT_REGMEM) = OT_REGMEM then - begin - actRegMemTypes := actRegMemTypes or insentry^.optypes[j]; - end; - end - else if ((insentry^.optypes[j] and OT_IMMEDIATE) = OT_IMMEDIATE) then - begin - inc(actConstCount); - - actConstSize := actConstSize or (insentry^.optypes[j] and OT_SIZE_MASK); - end - end; - - if actConstCount > 0 then - begin - case actConstSize of - 0: SConstInfo := csiNoSize; - OT_BITS8: SConstInfo := csiMem8; - OT_BITS16: SConstInfo := csiMem16; - OT_BITS32: SConstInfo := csiMem32; - OT_BITS64: SConstInfo := csiMem64; - else SConstInfo := csiMultiple; - end; - - if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize = csiUnknown then - begin - InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := SConstInfo; - end - else if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize <> SConstInfo then - begin - InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiMultiple; - end; - end; - - if actVMemCount > 0 then - begin - if actVMemCount = 1 then - begin - if actVMemTypes > 0 then - begin - case actVMemTypes of - OT_XMEM32: MRefInfo := msiXMem32; - OT_XMEM64: MRefInfo := msiXMem64; - OT_YMEM32: MRefInfo := msiYMem32; - OT_YMEM64: MRefInfo := msiYMem64; - OT_ZMEM32: MRefInfo := msiZMem32; - OT_ZMEM64: MRefInfo := msiZMem64; - else; - end; - - case actRegTypes of - OT_XMMREG: case MRefInfo of - msiXMem32, - msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128; - msiYMem32, - msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256; - msiZMem32, - msiZMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS512; - else; - end; - OT_YMMREG: case MRefInfo of - msiXMem32, - msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128; - msiYMem32, - msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256; - msiZMem32, - msiZMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS512; - else; - end; - OT_ZMMREG: case MRefInfo of - msiXMem32, - msiXMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS128; - msiYMem32, - msiYMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS256; - msiZMem32, - msiZMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS512; - else; - end; - - //else InternalError(777209); - end; - - - if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; - end - else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then - begin - if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64] then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple; - end - else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> msiVMemMultiple then; - end; - - end; - end - else; - end - else - begin - if (actMemCount=2) and ((AsmOp=A_MOVS) or (AsmOp=A_CMPS)) then actMemCount:=1; - - ExistsMemRef := ExistsMemRef or (actMemCount > 0); - - case actMemCount of - 0: ; // nothing todo - 1: begin - MRefInfo := msiUnknown; - - if not(ExistsCode336 or ExistsCode337) then - case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of - OT_MMXRM: actMemSize := actMemSize or OT_BITS64; - OT_XMMRM: actMemSize := actMemSize or OT_BITS128; - OT_YMMRM: actMemSize := actMemSize or OT_BITS256; - OT_ZMMRM: actMemSize := actMemSize or OT_BITS512; - end; - - case actMemSize of - 0: MRefInfo := msiNoSize; - OT_BITS8: MRefInfo := msiMem8; - OT_BITS16: MRefInfo := msiMem16; - OT_BITS32: MRefInfo := msiMem32; - OT_BITSB32: MRefInfo := msiBMem32; - OT_BITS64: MRefInfo := msiMem64; - OT_BITSB64: MRefInfo := msiBMem64; - OT_BITS128: MRefInfo := msiMem128; - OT_BITS256: MRefInfo := msiMem256; - OT_BITS512: MRefInfo := msiMem512; - OT_BITS80, - OT_FAR, - OT_NEAR, - OT_SHORT: ; // ignore - else - begin - bitcount := bitcnt(actMemSize); - - if bitcount > 1 then MRefInfo := msiMultiple - else; - end; - end; - - if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; - end - else - begin - // ignore broadcast-memory - if not(MRefInfo in [msiBMem32, msiBMem64]) then - begin - if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then - begin - with InsTabMemRefSizeInfoCache^[AsmOp] do - begin - if ((MemRefSize in [msiMem8, msiMULTIPLEMinSize8]) OR (MRefInfo = msiMem8)) then MemRefSize := msiMultipleMinSize8 - else if ((MemRefSize in [ msiMem16, msiMULTIPLEMinSize16]) OR (MRefInfo = msiMem16)) then MemRefSize := msiMultipleMinSize16 - else if ((MemRefSize in [ msiMem32, msiMULTIPLEMinSize32]) OR (MRefInfo = msiMem32)) then MemRefSize := msiMultipleMinSize32 - else if ((MemRefSize in [ msiMem64, msiMULTIPLEMinSize64]) OR (MRefInfo = msiMem64)) then MemRefSize := msiMultipleMinSize64 - else if ((MemRefSize in [msiMem128, msiMULTIPLEMinSize128]) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultipleMinSize128 - else if ((MemRefSize in [msiMem256, msiMULTIPLEMinSize256]) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultipleMinSize256 - else if ((MemRefSize in [msiMem512, msiMULTIPLEMinSize512]) OR (MRefInfo = msiMem512)) then MemRefSize := msiMultipleMinSize512 - else MemRefSize := msiMultiple; - end; - end; - end; - end; - - //if not(MRefInfo in [msiBMem32, msiBMem64]) and (actRegCount > 0) then - if actRegCount > 0 then - begin - if MRefInfo in [msiBMem32, msiBMem64] then - begin - if IF_BCST2 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to2]; - if IF_BCST4 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to4]; - if IF_BCST8 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to8]; - if IF_BCST16 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to16]; - - //InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes - - // BROADCAST - OPERAND - RegBCSTSizeMask := RegBCSTSizeMask or actMemSize; - - case actRegTypes and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of - OT_XMMREG: RegBCSTXMMSizeMask := RegBCSTXMMSizeMask or actMemSize; - OT_YMMREG: RegBCSTYMMSizeMask := RegBCSTYMMSizeMask or actMemSize; - OT_ZMMREG: RegBCSTZMMSizeMask := RegBCSTZMMSizeMask or actMemSize; - else begin - - RegBCSTXMMSizeMask := not(0); - RegBCSTYMMSizeMask := not(0); - RegBCSTZMMSizeMask := not(0); - end; - end; - end - else - case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of - OT_MMXREG: if actConstCount > 0 then RegMMXConstSizeMask := RegMMXConstSizeMask or actMemSize - else RegMMXSizeMask := RegMMXSizeMask or actMemSize; - OT_XMMREG: if actConstCount > 0 then RegXMMConstSizeMask := RegXMMConstSizeMask or actMemSize - else RegXMMSizeMask := RegXMMSizeMask or actMemSize; - OT_YMMREG: if actConstCount > 0 then RegYMMConstSizeMask := RegYMMConstSizeMask or actMemSize - else RegYMMSizeMask := RegYMMSizeMask or actMemSize; - OT_ZMMREG: if actConstCount > 0 then RegZMMConstSizeMask := RegZMMConstSizeMask or actMemSize - else RegZMMSizeMask := RegZMMSizeMask or actMemSize; - else begin - RegMMXSizeMask := not(0); - RegXMMSizeMask := not(0); - RegYMMSizeMask := not(0); - RegZMMSizeMask := not(0); - - RegMMXConstSizeMask := not(0); - RegXMMConstSizeMask := not(0); - RegYMMConstSizeMask := not(0); - RegZMMConstSizeMask := not(0); - end; - end; - end - else - - - end - else; - end; - end; - - inc(insentry); - end; - - if InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX then - begin - case RegBCSTSizeMask of - 0: ; // ignore; - OT_BITSB32: begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST32; - InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 4; - end; - OT_BITSB64: begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST64; - InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 2; - end; - else begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbMultiple; - end; - end; - end; - - - if (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples) and - (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX)then - begin - if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiVMemMultiple then - begin - if ((RegXMMSizeMask = OT_BITS128) or (RegXMMSizeMask = 0)) and - ((RegYMMSizeMask = OT_BITS256) or (RegYMMSizeMask = 0)) and - ((RegZMMSizeMask = OT_BITS512) or (RegZMMSizeMask = 0)) and - ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) <> 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemRegSize; - end; - end - else if (RegMMXSizeMask or RegMMXConstSizeMask) <> 0 then - begin - if ((RegMMXSizeMask or RegMMXConstSizeMask) = OT_BITS64) and - ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = 0) and - ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; - end; - end - else if (((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) or ((RegXMMSizeMask or RegXMMConstSizeMask) = 0)) and - (((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) or ((RegYMMSizeMask or RegYMMConstSizeMask) = 0)) and - (((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) or ((RegZMMSizeMask or RegZMMConstSizeMask) = 0)) and - (((RegXMMSizeMask or RegXMMConstSizeMask or - RegYMMSizeMask or RegYMMConstSizeMask or - RegZMMSizeMask or RegZMMConstSizeMask)) <> 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; - end - else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and - (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and - (RegZMMSizeMask or RegZMMConstSizeMask = 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32; - end - else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and - (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and - (RegZMMSizeMask or RegZMMConstSizeMask = OT_BITS64) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32z64; - end - else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS32) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS64) then - begin - if ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64; - end - else if ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS128) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64z128; - end; - end - else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and - ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128; - end - else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and - ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS256) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128z256; - end - else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and - ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256; - end - else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and - ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and - ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256z512; - end - else if ((RegXMMConstSizeMask = 0) or (RegXMMConstSizeMask = OT_BITS128)) and - ((RegYMMConstSizeMask = 0) or (RegYMMConstSizeMask = OT_BITS256)) and - ((RegZMMConstSizeMask = 0) or (RegZMMConstSizeMask = OT_BITS512)) and - ((RegXMMConstSizeMask or RegYMMConstSizeMask or RegZMMConstSizeMask) <> 0) and - ( - ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS128) or - ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS256) or - ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS512) - ) then - begin - case RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask of - OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst128; - OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst256; - OT_BITS512: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst512; - else InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMultiple; - end; - end - else - begin - if not( - (AsmOp = A_CVTSI2SS) or - (AsmOp = A_CVTSI2SD) or - (AsmOp = A_CVTPD2DQ) or - (AsmOp = A_VCVTPD2DQ) or - (AsmOp = A_VCVTPD2PS) or - (AsmOp = A_VCVTSI2SD) or - (AsmOp = A_VCVTSI2SS) or - (AsmOp = A_VCVTTPD2DQ) or - (AsmOp = A_VCVTPD2UDQ) or - (AsmOp = A_VCVTQQ2PS) or - (AsmOp = A_VCVTTPD2UDQ) or - (AsmOp = A_VCVTUQQ2PS) or - (AsmOp = A_VCVTUSI2SD) or - (AsmOp = A_VCVTUSI2SS) or - - - // TODO check - (AsmOp = A_VCMPSS) - - - ) then; - - end; - - end - else if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and - (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown) and - (not(ExistsMemRef)) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiNoMemRef; - end; - - InsTabMemRefSizeInfoCache^[AsmOp].RegXMMSizeMask:=RegXMMSizeMask; - InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask; - InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask; - - end; - end; - - for AsmOp := low(TAsmOp) to high(TAsmOp) do - begin - - - // only supported intructiones with SSE- or AVX-operands - if not(InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) then - begin - InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; - InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; - end; - end; - end; - -{ TOperandListItem } - -constructor TOperandListItem.Create; -begin - inherited; - - FOpActive := false; - FOpNumber := -1; - FOpTyp := otUnknown; - FValues := TStringList.Create; -end; - -destructor TOperandListItem.Destroy; -begin - FreeAndNil(FValues); - inherited; -end; - -{ TOperandList } - -function TOperandList.Add(aItem: TOperandListItem): integer; -begin - result := FList.Add(aItem); -end; - -function TOperandList.GetItems(aIndex: integer): TOperandListItem; -begin - result := TOperandListItem(FList[aIndex]); -end; - -{ TAsmTestGenerator } - -function TAsmTestGenerator.InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, - aOp4: String): TStringList; -var - i: integer; - Item: TOperandListItem; - OItem1: TOperandListItem; - OItem2: TOperandListItem; - OItem3: TOperandListItem; - OItem4: TOperandListItem; - - il_Op: integer; - il_Op1: integer; - il_Op2: integer; - il_Op3: integer; - il_Op4: integer; - - sSuffix: string; - sl_Operand: String; - sl_Inst : String; - sl_RegCombi: String; - sl_Prefix: String; - UsePrefix: boolean; - il_Operands: integer; - UsedParams: cardinal; - UseDefault: boolean; - sl_RegCombi1: string; - sl_RegCombi2: string; - sl_RegCombi3: string; - MaskRegNeeded:boolean; - - - function PrepareOperandTyp(const aTyp: String): String; - begin - result := aTyp; - if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); - if result = 'XMMRM128' then result := 'XMMRM'; - if result = 'YMMRM256' then result := 'YMMRM'; - end; - - -begin - result := TStringList.Create; - - OItem1 := TOperandListItem.Create; - try - OItem2 := TOperandListItem.Create; - try - OItem3 := TOperandListItem.Create; - try - OItem4 := TOperandListItem.Create; - try - - UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR - (UpperCase(aInst) = 'VCVTPD2PS') OR - (UpperCase(aInst) = 'VCVTSI2SD') OR - (UpperCase(aInst) = 'VCVTSI2SS') OR - (UpperCase(aInst) = 'VCVTTPD2DQ') or - (UpperCase(aInst) = 'VPMOVZXWQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTTPD2UDQ') or - (UpperCase(aInst) = 'VCVTUQQ2PS') or - (UpperCase(aInst) = 'VCVTQQ2PS') or - (UpperCase(aInst) = 'VCVTUSI2SD') or - (UpperCase(aInst) = 'VCVTUSI2SS') or - (UpperCase(aInst) = 'VFPCLASSPD') or - (UpperCase(aInst) = 'VFPCLASSPS') or - (UpperCase(aInst) = 'VCMPSS') - - ; - - - MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or - (Pos('VPGATHER', Uppercase(aInst)) = 1) or - (Pos('VPSCATTER', Uppercase(aInst)) = 1) or - (Pos('VSCATTER', Uppercase(aInst)) = 1); - - for il_Op := 1 to 4 do - begin - sl_Prefix := ''; - - case il_Op of - 1: begin - Item := OItem1; - sl_Operand := aOp1; - end; - 2: begin - Item := OItem2; - sl_Operand := aOp2; - end; - 3: begin - Item := OItem3; - sl_Operand := aOp3; - end; - 4: begin - Item := OItem4; - sl_Operand := aOp4; - end; - end; - - sl_Operand := PrepareOperandTyp(sl_Operand); - - if (AnsiSameText(sl_Operand, 'XMMREG')) or - (AnsiSameText(sl_Operand, 'XMMREG_M')) or - (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'XMMREG_ER')) or - (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMReg; - Item.OpActive := true; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM1' + sSuffix); - Item.Values.Add('XMM2' + sSuffix); - Item.Values.Add('XMM3' + sSuffix); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM5' + sSuffix); - Item.Values.Add('XMM6' + sSuffix); - Item.Values.Add('XMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM9' + sSuffix); - Item.Values.Add('XMM18' + sSuffix); - Item.Values.Add('XMM27' + sSuffix); - Item.Values.Add('XMM31' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('XMM0'); - Item.Values.Add('XMM9'); - Item.Values.Add('XMM18'); - Item.Values.Add('XMM27'); - Item.Values.Add('XMM31'); - end; - end - else - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM8' + sSuffix); - Item.Values.Add('XMM12' + sSuffix); - Item.Values.Add('XMM15' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('XMM0'); - Item.Values.Add('XMM4'); - Item.Values.Add('XMM8'); - Item.Values.Add('XMM12'); - Item.Values.Add('XMM15'); - end; - end; - end; - end - else if (AnsiSameText(sl_Operand, 'XMMRM')) or - (AnsiSameText(sl_Operand, 'XMMRM_M')) or - (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM1' + sSuffix); - Item.Values.Add('XMM2' + sSuffix); - Item.Values.Add('XMM3' + sSuffix); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM5' + sSuffix); - Item.Values.Add('XMM6' + sSuffix); - Item.Values.Add('XMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM9' + sSuffix); - Item.Values.Add('XMM9'); - Item.Values.Add('XMM18' + sSuffix); - Item.Values.Add('XMM18'); - Item.Values.Add('XMM27' + sSuffix); - Item.Values.Add('XMM27'); - Item.Values.Add('XMM31' + sSuffix); - Item.Values.Add('XMM31'); - end - else - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM4'); - Item.Values.Add('XMM8' + sSuffix); - Item.Values.Add('XMM8'); - Item.Values.Add('XMM12' + sSuffix); - Item.Values.Add('XMM15'); - Item.Values.Add('XMM15' + sSuffix); - end; - - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end; - end - else if (AnsiSameText(sl_Operand, 'XMMRM8')) or - (AnsiSameText(sl_Operand, 'XMMRM8_M')) or - (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM8; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'byte '; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM1' + sSuffix); - Item.Values.Add('XMM2' + sSuffix); - Item.Values.Add('XMM3' + sSuffix); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM5' + sSuffix); - Item.Values.Add('XMM6' + sSuffix); - Item.Values.Add('XMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM9' + sSuffix); - Item.Values.Add('XMM9'); - Item.Values.Add('XMM18' + sSuffix); - Item.Values.Add('XMM18'); - Item.Values.Add('XMM27' + sSuffix); - Item.Values.Add('XMM27'); - Item.Values.Add('XMM31' + sSuffix); - Item.Values.Add('XMM31'); - end - else - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM4'); - Item.Values.Add('XMM8' + sSuffix); - Item.Values.Add('XMM8'); - Item.Values.Add('XMM12' + sSuffix); - Item.Values.Add('XMM12'); - Item.Values.Add('XMM15' + sSuffix); - Item.Values.Add('XMM15'); - end; - - //Item.Values.Add('[RIP]'); - //Item.Values.Add('[RIP + 16]'); - - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end; - end - else if (AnsiSameText(sl_Operand, 'XMMRM16')) or - (AnsiSameText(sl_Operand, 'XMMRM16_M')) or - (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM16; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'word '; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM1' + sSuffix); - Item.Values.Add('XMM2' + sSuffix); - Item.Values.Add('XMM3' + sSuffix); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM5' + sSuffix); - Item.Values.Add('XMM6' + sSuffix); - Item.Values.Add('XMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM9' + sSuffix); - Item.Values.Add('XMM9'); - Item.Values.Add('XMM18' + sSuffix); - Item.Values.Add('XMM18'); - Item.Values.Add('XMM27' + sSuffix); - Item.Values.Add('XMM27'); - Item.Values.Add('XMM31' + sSuffix); - Item.Values.Add('XMM31'); - end - else - begin - Item.Values.Add('XMM0' + sSuffix); - Item.Values.Add('XMM0'); - Item.Values.Add('XMM4' + sSuffix); - Item.Values.Add('XMM4'); - Item.Values.Add('XMM8' + sSuffix); - Item.Values.Add('XMM8'); - Item.Values.Add('XMM12' + sSuffix); - Item.Values.Add('XMM12'); - Item.Values.Add('XMM15' + sSuffix); - Item.Values.Add('XMM15'); - end; - - //Item.Values.Add('[RIP]'); - //Item.Values.Add('[RIP + 16]'); - - MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else - begin - MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end; - end - else if (AnsiSameText(sl_Operand, 'YMMREG')) or - (AnsiSameText(sl_Operand, 'YMMREG_M')) or - (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'YMMREG_ER')) or - (AnsiSameText(sl_Operand, 'YMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMReg; - Item.OpActive := true; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM1' + sSuffix); - Item.Values.Add('YMM2' + sSuffix); - Item.Values.Add('YMM3' + sSuffix); - Item.Values.Add('YMM4' + sSuffix); - Item.Values.Add('YMM5' + sSuffix); - Item.Values.Add('YMM6' + sSuffix); - Item.Values.Add('YMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM9' + sSuffix); - Item.Values.Add('YMM18' + sSuffix); - Item.Values.Add('YMM27' + sSuffix); - Item.Values.Add('YMM31' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('YMM0'); - Item.Values.Add('YMM9'); - Item.Values.Add('YMM18'); - Item.Values.Add('YMM27'); - Item.Values.Add('YMM31'); - end; - end - else - begin - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM4' + sSuffix); - Item.Values.Add('YMM8' + sSuffix); - Item.Values.Add('YMM12' + sSuffix); - Item.Values.Add('YMM15' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('YMM0'); - Item.Values.Add('YMM4'); - Item.Values.Add('YMM8'); - Item.Values.Add('YMM12'); - Item.Values.Add('YMM15'); - end; - end; - end; - end - else if (AnsiSameText(sl_Operand, 'YMMRM')) or - (AnsiSameText(sl_Operand, 'YMMRM_M')) or - (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'YMMRM_ER')) or - (AnsiSameText(sl_Operand, 'YMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM1' + sSuffix); - Item.Values.Add('YMM2' + sSuffix); - Item.Values.Add('YMM3' + sSuffix); - Item.Values.Add('YMM4' + sSuffix); - Item.Values.Add('YMM5' + sSuffix); - Item.Values.Add('YMM6' + sSuffix); - Item.Values.Add('YMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM9' + sSuffix); - Item.Values.Add('YMM18' + sSuffix); - Item.Values.Add('YMM27' + sSuffix); - Item.Values.Add('YMM31' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('YMM0'); - Item.Values.Add('YMM9'); - Item.Values.Add('YMM18'); - Item.Values.Add('YMM27'); - Item.Values.Add('YMM31'); - end; - end - else - begin - Item.Values.Add('YMM0' + sSuffix); - Item.Values.Add('YMM4' + sSuffix); - Item.Values.Add('YMM8' + sSuffix); - Item.Values.Add('YMM12' + sSuffix); - Item.Values.Add('YMM15' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('YMM0'); - Item.Values.Add('YMM4'); - Item.Values.Add('YMM8'); - Item.Values.Add('YMM12'); - Item.Values.Add('YMM15'); - end; - end; - - MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end; - end - else if (AnsiSameText(sl_Operand, 'ZMMREG')) or - (AnsiSameText(sl_Operand, 'ZMMREG_M')) or - (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or - (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMReg; - Item.OpActive := true; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM1' + sSuffix); - Item.Values.Add('ZMM2' + sSuffix); - Item.Values.Add('ZMM3' + sSuffix); - Item.Values.Add('ZMM4' + sSuffix); - Item.Values.Add('ZMM5' + sSuffix); - Item.Values.Add('ZMM6' + sSuffix); - Item.Values.Add('ZMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM9' + sSuffix); - Item.Values.Add('ZMM18' + sSuffix); - Item.Values.Add('ZMM27' + sSuffix); - Item.Values.Add('ZMM31' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('ZMM0'); - Item.Values.Add('ZMM9'); - Item.Values.Add('ZMM18'); - Item.Values.Add('ZMM27'); - Item.Values.Add('ZMM31'); - end; - end - else - begin - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM4' + sSuffix); - Item.Values.Add('ZMM8' + sSuffix); - Item.Values.Add('ZMM12' + sSuffix); - Item.Values.Add('ZMM15' + sSuffix); - end; - end; - end - else if (AnsiSameText(sl_Operand, 'ZMMRM')) or - (AnsiSameText(sl_Operand, 'ZMMRM_M')) or - (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - sSuffix := ''; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM1' + sSuffix); - Item.Values.Add('ZMM2' + sSuffix); - Item.Values.Add('ZMM3' + sSuffix); - Item.Values.Add('ZMM4' + sSuffix); - Item.Values.Add('ZMM5' + sSuffix); - Item.Values.Add('ZMM6' + sSuffix); - Item.Values.Add('ZMM7' + sSuffix); - - if x64 then - begin - Item.Values.Clear; - if FAVX512 then - begin - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM9' + sSuffix); - Item.Values.Add('ZMM18' + sSuffix); - Item.Values.Add('ZMM27' + sSuffix); - Item.Values.Add('ZMM31' + sSuffix); - - if (sSuffix <> '') and - (MaskRegNeeded = false) then - begin - Item.Values.Add('ZMM0'); - Item.Values.Add('ZMM9'); - Item.Values.Add('ZMM18'); - Item.Values.Add('ZMM27'); - Item.Values.Add('ZMM31'); - end; - end - else - begin - Item.Values.Add('ZMM0' + sSuffix); - Item.Values.Add('ZMM4' + sSuffix); - Item.Values.Add('ZMM8' + sSuffix); - Item.Values.Add('ZMM12' + sSuffix); - Item.Values.Add('ZMM15' + sSuffix); - end; - - MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end; - end - else if AnsiSameText(sl_Operand, 'MEM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM8; - Item.OpActive := true; - - - - if UsePrefix then sl_Prefix := 'byte '; - - - sSuffix := ''; - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'MEM16') or - AnsiSameText(sl_Operand, 'MEM16_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM16; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'word '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'MEM32') or - AnsiSameText(sl_Operand, 'MEM32_M') or - AnsiSameText(sl_Operand, 'MEM32_MZ') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'dword '; - - sSuffix := ''; - - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM64')) or - (AnsiSameText(sl_Operand, 'MEM64_M')) or - (AnsiSameText(sl_Operand, 'MEM64_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'qword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM128')) or - (AnsiSameText(sl_Operand, 'MEM128_M')) or - (AnsiSameText(sl_Operand, 'MEM128_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM128; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - if x64 then - begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM256')) or - (AnsiSameText(sl_Operand, 'MEM256_M')) or - (AnsiSameText(sl_Operand, 'MEM256_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM256; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM512')) or - (AnsiSameText(sl_Operand, 'MEM512_M')) or - (AnsiSameText(sl_Operand, 'MEM512_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM512; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'REG8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG8; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg8); - end - else Item.Values.AddStrings(FReg8); - end - else if AnsiSameText(sl_Operand, 'REG16') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG16; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg16); - end - else Item.Values.AddStrings(FReg16); - end - else if AnsiSameText(sl_Operand, 'REG32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG32; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg32Base); - end - else Item.Values.AddStrings(FReg32Base); - end - else if AnsiSameText(sl_Operand, 'REG64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG64; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg64Base); - end; - end - else if AnsiSameText(sl_Operand, 'RM32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM32; - Item.OpActive := true; - - Item.Values.AddStrings(FReg32Base); - - if UsePrefix then sl_Prefix := 'dword '; - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'RM64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM32; - Item.OpActive := true; - - - - if UsePrefix then sl_Prefix := 'qword '; - - if x64 then - begin - Item.Values.AddStrings(FReg64Base); - MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'IMM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otIMM8; - Item.OpActive := true; - - Item.Values.Add('0'); - end - else if AnsiSameText(sl_Operand, 'XMEM32') or - AnsiSameText(sl_Operand, 'XMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); - end; - end - else if AnsiSameText(sl_Operand, 'XMEM64') or - AnsiSameText(sl_Operand, 'XMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM64; - Item.OpActive := true; - - //if UsePrefix then sl_Prefix := 'oword '; - // - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'YMEM32') or - AnsiSameText(sl_Operand, 'YMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'YMEM64') or - AnsiSameText(sl_Operand, 'YMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'ZMEM32') or - AnsiSameText(sl_Operand, 'ZMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'ZMEM64') or - AnsiSameText(sl_Operand, 'ZMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, '2B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '4B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '8B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '16B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '2B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '4B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '8B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '16B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'KREG') or - AnsiSameText(sl_Operand, 'KREG_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otKREG; - Item.OpActive := true; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if UsePrefix then sl_Prefix := ''; - - for i := 0 to FRegKREG.Count - 1 do - Item.Values.Add(FRegKREG[i] + sSuffix); - end - else if trim(sl_Operand) = '' then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add(''); - end - else - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add('?' + sl_Operand); - end - - end; - - sl_RegCombi := ''; - - - il_Operands := 0; - UsedParams := 0; - - if OItem1.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 1; - end; - - if OItem2.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 2; - end; - - if OItem3.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 4; - end; - - if OItem4.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 8; - end; - - case il_Operands of - 1: UseDefault := UsedParams <> 1; - 2: UseDefault := UsedParams <> 3; - 3: UseDefault := UsedParams <> 7; - 4: UseDefault := UsedParams <> 15; - else UseDefault := true; - end; - - //UseDefault := true; - - if UseDefault then - begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - sl_RegCombi := ''; - - if OItem1.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; - end; - - if OItem2.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; - end; - - if OItem3.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; - end; - - if OItem4.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; - end; - - if sl_RegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - sl_RegCombi := ''; - end; - end; - end; - end; - end; - end - else - begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - if OItem1.OpActive then - begin - sl_RegCombi1 := OItem1.Values[il_Op1]; - end - else sl_RegCombi1 := ''; - - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - if OItem2.OpActive then - begin - sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; - end - else sl_RegCombi2 := sl_RegCombi1; - - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - if OItem3.OpActive then - begin - sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; - end - else sl_RegCombi3 := sl_RegCombi2; - - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - if OItem4.OpActive then - begin - sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; - end - else sl_RegCombi := sl_RegCombi3; - - if sl_RegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - sl_RegCombi := ''; - end; - end; - end; - end; - end; - end; - finally - FreeAndNil(OItem4); - end; - finally - FreeAndNil(OItem3); - end; - finally - FreeAndNil(OItem2); - end; - finally - FreeAndNil(OItem1); - end; -end; - - -function TAsmTestGenerator.InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, - aOp4: String): TStringList; -var - i: integer; - Item: TOperandListItem; - OItem1: TOperandListItem; - OItem2: TOperandListItem; - OItem3: TOperandListItem; - OItem4: TOperandListItem; - - il_Op: integer; - il_Op1: integer; - il_Op2: integer; - il_Op3: integer; - il_Op4: integer; - - sSuffix: string; - sl_Operand: String; - sl_Inst : String; - sl_RegCombi: String; - sl_Prefix: String; - UsePrefix: boolean; - il_Operands: integer; - UsedParams: cardinal; - UseDefault: boolean; - sl_RegCombi1: string; - sl_RegCombi2: string; - sl_RegCombi3: string; - - function PrepareOperandTyp(const aTyp: String): String; - begin - result := aTyp; - if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); - if result = 'XMMRM128' then result := 'XMMRM'; - if result = 'YMMRM256' then result := 'YMMRM'; - end; - - -begin - result := TStringList.Create; - - OItem1 := TOperandListItem.Create; - try - OItem2 := TOperandListItem.Create; - try - OItem3 := TOperandListItem.Create; - try - OItem4 := TOperandListItem.Create; - try - - UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR - (UpperCase(aInst) = 'VCVTPD2PS') OR - (UpperCase(aInst) = 'VCVTSI2SD') OR - (UpperCase(aInst) = 'VCVTSI2SS') OR - (UpperCase(aInst) = 'VCVTTPD2DQ') or - (UpperCase(aInst) = 'VPMOVZXWQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTTPD2UDQ') or - (UpperCase(aInst) = 'VCVTUQQ2PS') or - (UpperCase(aInst) = 'VCVTQQ2PS') or - (UpperCase(aInst) = 'VCVTUSI2SD') or - (UpperCase(aInst) = 'VCVTUSI2SS') or - (UpperCase(aInst) = 'VFPCLASSPD') or - (UpperCase(aInst) = 'VFPCLASSPS') or - (UpperCase(aInst) = 'VCMPSS') - - ; - - - - for il_Op := 1 to 4 do - begin - sl_Prefix := ''; - - case il_Op of - 1: begin - Item := OItem1; - sl_Operand := aOp1; - end; - 2: begin - Item := OItem2; - sl_Operand := aOp2; - end; - 3: begin - Item := OItem3; - sl_Operand := aOp3; - end; - 4: begin - Item := OItem4; - sl_Operand := aOp4; - end; - end; - - sl_Operand := PrepareOperandTyp(sl_Operand); - - if (AnsiSameText(sl_Operand, 'XMMREG')) or - (AnsiSameText(sl_Operand, 'XMMREG_M')) or - (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'XMMREG_ER')) or - (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMReg; - Item.OpActive := true; - - Item.Values.Add('XMM0'); - end - else if (AnsiSameText(sl_Operand, 'XMMRM')) or - (AnsiSameText(sl_Operand, 'XMMRM_M')) or - (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - Item.Values.Add(' lOWord'); - Item.Values.Add(' gOWord'); - Item.Values.Add(' clOWord'); - Item.Values.Add(' cgOWord'); - - Item.Values.Add(' oword lOWord'); - Item.Values.Add(' oword gOWord'); - Item.Values.Add(' oword clOWord'); - Item.Values.Add(' oword cgOWord'); - - Item.Values.Add(' byte lOWord'); - Item.Values.Add(' byte gOWord'); - Item.Values.Add(' byte clOWord'); - Item.Values.Add(' byte cgOWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' oword lRec'); - Item.Values.Add(' oword gRec'); - - Item.Values.Add(' oword lRec.rOWord'); - Item.Values.Add(' oword gRec.rOWord'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'XMMRM8')) or - (AnsiSameText(sl_Operand, 'XMMRM8_M')) or - (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM8; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'byte '; - - Item.Values.Add('lbyte'); - Item.Values.Add('gbyte'); - Item.Values.Add('clbyte'); - Item.Values.Add('cgbyte'); - - Item.Values.Add('byte lbyte'); - Item.Values.Add('byte gbyte'); - Item.Values.Add('byte clbyte'); - Item.Values.Add('byte cgbyte'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' byte lRec'); - Item.Values.Add(' byte gRec'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'XMMRM16')) or - (AnsiSameText(sl_Operand, 'XMMRM16_M')) or - (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM16; - Item.OpActive := true; - - Item.Values.Add('lword'); - Item.Values.Add('gword'); - Item.Values.Add('clword'); - Item.Values.Add('cgword'); - - Item.Values.Add('word lword'); - Item.Values.Add('word gword'); - Item.Values.Add('word clword'); - Item.Values.Add('word cgword'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' word lRec'); - Item.Values.Add(' word gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'YMMREG')) or - (AnsiSameText(sl_Operand, 'YMMREG_M')) or - (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'YMMREG_ER')) or - (AnsiSameText(sl_Operand, 'YMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMReg; - Item.OpActive := true; - - Item.Values.Add('YMM0'); - end - else if (AnsiSameText(sl_Operand, 'YMMRM')) or - (AnsiSameText(sl_Operand, 'YMMRM_M')) or - (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'YMMRM_ER')) or - (AnsiSameText(sl_Operand, 'YMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMRM; - Item.OpActive := true; - - Item.Values.Add('lYWord'); - Item.Values.Add('gYWord'); - Item.Values.Add('clYWord'); - Item.Values.Add('cgYWord'); - - Item.Values.Add('yword lYWord'); - Item.Values.Add('yword gYWord'); - Item.Values.Add('yword clYWord'); - Item.Values.Add('yword cgYWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' yword lRec'); - Item.Values.Add(' yword gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'ZMMREG')) or - (AnsiSameText(sl_Operand, 'ZMMREG_M')) or - (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or - (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMReg; - Item.OpActive := true; - - Item.Values.Add('ZMM0'); - end - else if (AnsiSameText(sl_Operand, 'ZMMRM')) or - (AnsiSameText(sl_Operand, 'ZMMRM_M')) or - (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMRM; - Item.OpActive := true; - - Item.Values.Add('lZWord'); - Item.Values.Add('gZWord'); - Item.Values.Add('clZWord'); - Item.Values.Add('cgZWord'); - - Item.Values.Add('zword lZWord'); - Item.Values.Add('zword gZWord'); - Item.Values.Add('zword clZWord'); - Item.Values.Add('zword cgZWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' zword lRec'); - Item.Values.Add(' zword gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if AnsiSameText(sl_Operand, 'MEM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM8; - Item.OpActive := true; - - Item.Values.Add('lByte'); - Item.Values.Add('gByte'); - Item.Values.Add('clByte'); - Item.Values.Add('cgByte'); - - Item.Values.Add('byte lByte'); - Item.Values.Add('byte gByte'); - Item.Values.Add('byte clByte'); - Item.Values.Add('byte cgByte'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' byte lRec'); - Item.Values.Add(' byte gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - end - else if AnsiSameText(sl_Operand, 'MEM16') or - AnsiSameText(sl_Operand, 'MEM16_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM16; - Item.OpActive := true; - - Item.Values.Add('lWord'); - Item.Values.Add('gWord'); - Item.Values.Add('clWord'); - Item.Values.Add('cgWord'); - - Item.Values.Add('word lWord'); - Item.Values.Add('word gWord'); - Item.Values.Add('word clWord'); - Item.Values.Add('word cgWord'); - - Item.Values.Add(' word lRec'); - Item.Values.Add(' word gRec'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - end - else if AnsiSameText(sl_Operand, 'MEM32') or - AnsiSameText(sl_Operand, 'MEM32_M') or - AnsiSameText(sl_Operand, 'MEM32_MZ') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM32; - Item.OpActive := true; - - Item.Values.Add('lDWord'); - Item.Values.Add('gDWord'); - Item.Values.Add('clDWord'); - Item.Values.Add('cgDWord'); - - Item.Values.Add('dword lDWord'); - Item.Values.Add('dword gDWord'); - Item.Values.Add('dword clDWord'); - Item.Values.Add('dword cgDWord'); - - Item.Values.Add(' dword lRec'); - Item.Values.Add(' dword gRec'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - end - else if (AnsiSameText(sl_Operand, 'MEM64')) or - (AnsiSameText(sl_Operand, 'MEM64_M')) or - (AnsiSameText(sl_Operand, 'MEM64_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM64; - Item.OpActive := true; - - Item.Values.Add('lQWord'); - Item.Values.Add('gQWord'); - Item.Values.Add('clQWord'); - Item.Values.Add('cgQWord'); - - Item.Values.Add('qword lQWord'); - Item.Values.Add('qword gQWord'); - Item.Values.Add('qword clQWord'); - Item.Values.Add('qword cgQWord'); - - Item.Values.Add(' qword lRec'); - Item.Values.Add(' qword gRec'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - end - else if (AnsiSameText(sl_Operand, 'MEM128')) or - (AnsiSameText(sl_Operand, 'MEM128_M')) or - (AnsiSameText(sl_Operand, 'MEM128_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM128; - Item.OpActive := true; - - Item.Values.Add('lOWord'); - Item.Values.Add('gOWord'); - Item.Values.Add('clOWord'); - Item.Values.Add('cgOWord'); - - Item.Values.Add('oword lOWord'); - Item.Values.Add('oword gOWord'); - Item.Values.Add('oword clOWord'); - Item.Values.Add('oword cgOWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' oword lRec'); - Item.Values.Add(' oword gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'MEM256')) or - (AnsiSameText(sl_Operand, 'MEM256_M')) or - (AnsiSameText(sl_Operand, 'MEM256_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM256; - Item.OpActive := true; - - Item.Values.Add('lYWord'); - Item.Values.Add('gYWord'); - Item.Values.Add('clYWord'); - Item.Values.Add('cgYWord'); - - Item.Values.Add('yword lYWord'); - Item.Values.Add('yword gYWord'); - Item.Values.Add('yword clYWord'); - Item.Values.Add('yword cgYWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' yword lRec'); - Item.Values.Add(' yword gRec'); - - Item.Values.Add(' lRec.rByte'); - Item.Values.Add(' gRec.rByte'); - - Item.Values.Add(' lRec.rWord'); - Item.Values.Add(' gRec.rWord'); - - Item.Values.Add(' lRec.rDWord'); - Item.Values.Add(' gRec.rDWord'); - - Item.Values.Add(' lRec.rQWord'); - Item.Values.Add(' gRec.rQWord'); - - Item.Values.Add(' lRec.rOWord'); - Item.Values.Add(' gRec.rOWord'); - - Item.Values.Add(' lRec.rYWord'); - Item.Values.Add(' gRec.rYWord'); - - Item.Values.Add(' lRec.rZWord'); - Item.Values.Add(' gRec.rZWord'); - - end - else if (AnsiSameText(sl_Operand, 'MEM512')) or - (AnsiSameText(sl_Operand, 'MEM512_M')) or - (AnsiSameText(sl_Operand, 'MEM512_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM512; - Item.OpActive := true; - - Item.Values.Add('lZWord'); - Item.Values.Add('gZWord'); - Item.Values.Add('clZWord'); - Item.Values.Add('cgZWord'); - - Item.Values.Add('zword lZWord'); - Item.Values.Add('zword gZWord'); - Item.Values.Add('zword clZWord'); - Item.Values.Add('zword cgZWord'); - - Item.Values.Add(' lRec'); - Item.Values.Add(' gRec'); - - Item.Values.Add(' zword lRec'); - Item.Values.Add(' zword gRec'); - - - end - else if AnsiSameText(sl_Operand, 'REG8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG8; - Item.OpActive := true; - - Item.Values.Add('al'); - end - else if AnsiSameText(sl_Operand, 'REG16') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG16; - Item.OpActive := true; - - Item.Values.Add('ax'); - end - else if AnsiSameText(sl_Operand, 'REG32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG32; - Item.OpActive := true; - - Item.Values.Add('eax'); - end - else if AnsiSameText(sl_Operand, 'REG64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG64; - Item.OpActive := true; - - Item.Values.Add('rax'); - end - else if AnsiSameText(sl_Operand, 'RM32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM32; - Item.OpActive := true; - - Item.Values.Add('lDWord'); - Item.Values.Add('gDWord'); - end - else if AnsiSameText(sl_Operand, 'RM64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM64; - Item.OpActive := true; - - Item.Values.Add('lQWord'); - Item.Values.Add('gQWord'); - end - else if AnsiSameText(sl_Operand, 'IMM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otIMM8; - Item.OpActive := true; - - Item.Values.Add('0'); - end - else if AnsiSameText(sl_Operand, 'XMEM32') or - AnsiSameText(sl_Operand, 'XMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM32; - Item.OpActive := true; - end - else if AnsiSameText(sl_Operand, 'XMEM64') or - AnsiSameText(sl_Operand, 'XMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM64; - Item.OpActive := true; - end - else if AnsiSameText(sl_Operand, 'YMEM32') or - AnsiSameText(sl_Operand, 'YMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM32; - Item.OpActive := true; - end - else if AnsiSameText(sl_Operand, 'YMEM64') or - AnsiSameText(sl_Operand, 'YMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - end - else if AnsiSameText(sl_Operand, 'ZMEM32') or - AnsiSameText(sl_Operand, 'ZMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - end - else if AnsiSameText(sl_Operand, 'ZMEM64') or - AnsiSameText(sl_Operand, 'ZMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - end - else if AnsiSameText(sl_Operand, '2B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - Item.Values.Add('lDWord {1to2}'); - Item.Values.Add('gDWord {1to2}'); - end - else if AnsiSameText(sl_Operand, '4B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - Item.Values.Add('lDWord {1to4}'); - Item.Values.Add('gDWord {1to4}'); - end - else if AnsiSameText(sl_Operand, '8B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - Item.Values.Add('lDWord {1to8}'); - Item.Values.Add('gDWord {1to8}'); - end - else if AnsiSameText(sl_Operand, '16B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - Item.Values.Add('lDWord {1to16}'); - Item.Values.Add('gDWord {1to16}'); - end - else if AnsiSameText(sl_Operand, '2B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - Item.Values.Add('lQWord {1to2}'); - Item.Values.Add('gQWord {1to2}'); - end - else if AnsiSameText(sl_Operand, '4B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - Item.Values.Add('lQWord {1to4}'); - Item.Values.Add('gQWord {1to4}'); - end - else if AnsiSameText(sl_Operand, '8B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - Item.Values.Add('lQWord {1to8}'); - Item.Values.Add('gQWord {1to8}'); - end - else if AnsiSameText(sl_Operand, '16B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - Item.Values.Add('lQWord {1to16}'); - Item.Values.Add('gQWord {1to16}'); - end - else if AnsiSameText(sl_Operand, 'KREG') or - AnsiSameText(sl_Operand, 'KREG_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otKREG; - Item.OpActive := true; - - Item.Values.Add('k1'); - end - else if trim(sl_Operand) = '' then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add(''); - end - else - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add('?' + sl_Operand); - end - - end; - - sl_RegCombi := ''; - - - il_Operands := 0; - UsedParams := 0; - - if OItem1.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 1; - end; - - if OItem2.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 2; - end; - - if OItem3.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 4; - end; - - if OItem4.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 8; - end; - - case il_Operands of - 1: UseDefault := UsedParams <> 1; - 2: UseDefault := UsedParams <> 3; - 3: UseDefault := UsedParams <> 7; - 4: UseDefault := UsedParams <> 15; - else UseDefault := true; - end; - - //UseDefault := true; - - if UseDefault then - begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - sl_RegCombi := ''; - - if OItem1.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; - end; - - if OItem2.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; - end; - - if OItem3.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; - end; - - if OItem4.OpActive then - begin - if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; - end; - - if sl_RegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - sl_RegCombi := ''; - end; - end; - end; - end; - end; - end - else - begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - if OItem1.OpActive then - begin - sl_RegCombi1 := OItem1.Values[il_Op1]; - end - else sl_RegCombi1 := ''; - - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - if OItem2.OpActive then - begin - sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; - end - else sl_RegCombi2 := sl_RegCombi1; - - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - if OItem3.OpActive then - begin - sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; - end - else sl_RegCombi3 := sl_RegCombi2; - - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - if OItem4.OpActive then - begin - sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; - end - else sl_RegCombi := sl_RegCombi3; - - if sl_RegCombi <> '' then - begin - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(sl_Inst + sl_RegCombi); - sl_RegCombi := ''; - end; - end; - end; - end; - end; - end; - finally - FreeAndNil(OItem4); - end; - finally - FreeAndNil(OItem3); - end; - finally - FreeAndNil(OItem2); - end; - finally - FreeAndNil(OItem1); - end; -end; - -function TAsmTestGenerator.InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, - aOp3, aOp4: String): TStringList; -var - i: integer; - Item: TOperandListItem; - OItem1: TOperandListItem; - OItem2: TOperandListItem; - OItem3: TOperandListItem; - OItem4: TOperandListItem; - - il_Op: integer; - il_Op1: integer; - il_Op2: integer; - il_Op3: integer; - il_Op4: integer; - iAsmCounter: integer; - - sSuffix: string; - sReg: string; - sl_Operand: String; - sl_Inst : String; - sRegCombi: String; - sRegCombi1: String; - sRegCombi2: String; - sRegCombi3: String; - sRegCombi4: String; - sBaseReg : String; - sIndexReg : String; - - sl_Prefix: String; - UsePrefix: boolean; - il_Operands: integer; - UsedParams: cardinal; - UseDefault: boolean; - sl_RegCombi1: string; - sl_RegCombi2: string; - sl_RegCombi3: string; - sInstruction: string; - sMREF: string; - sLogMsg: string; - MaskRegNeeded:boolean; - slRegCombi: TStringList; - OpMode: TOpMode; - iOpNumMRef: integer; - - function PrepareOperandTyp(const aTyp: String): String; - begin - result := aTyp; - if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); - if result = 'XMMRM128' then result := 'XMMRM'; - if result = 'YMMRM256' then result := 'YMMRM'; - end; - - procedure SplitOperands(const aOperand1, aOperand2, aOperand3, aOperand4: string; var aRegCombi0, aRegCombi1, aRegCombi2, aRegCombi3, aRegCombi4: string); - var - i: integer; - s1: string; - s2: string; - s3: string; - s4: string; - iCnt1: integer; - iCnt2: integer; - iCnt3: integer; - iCnt4: integer; - iMaxCnt: integer; - - begin - with TStringList.Create do - try - Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); - iCnt1 := Count; - - Text := StringReplace(trim(aOperand2), '|', #13#10, [rfReplaceAll]); - iCnt2 := Count; - - Text := StringReplace(trim(aOperand3), '|', #13#10, [rfReplaceAll]); - iCnt3 := Count; - - Text := StringReplace(trim(aOperand4), '|', #13#10, [rfReplaceAll]); - iCnt4 := Count; - - iMaxCnt := iCnt1; - if iCnt2 > iMaxCnt then iMaxCnt := iCnt2; - if iCnt3 > iMaxCnt then iMaxCnt := iCnt3; - if iCnt4 > iMaxCnt then iMaxCnt := iCnt4; - - - if (aOperand1 <> '') and (aRegCombi0 <> '') then - begin - aRegCombi0 := aRegCombi0 + ','; - aRegCombi1 := aRegCombi1 + ','; - aRegCombi2 := aRegCombi2 + ','; - aRegCombi3 := aRegCombi3 + ','; - aRegCombi4 := aRegCombi4 + ','; - end; - - - Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); - if Count = iMaxCnt then - begin - for i := 0 to iMaxCnt - 1 do - begin - case i of - 0: aRegCombi0 := aRegCombi0 + ',' + Strings[i]; - 1: aRegCombi1 := aRegCombi1 + ',' + Strings[i]; - 2: aRegCombi2 := aRegCombi2 + ',' + Strings[i]; - 3: aRegCombi3 := aRegCombi3 + ',' + Strings[i]; - 4: aRegCombi4 := aRegCombi4 + ',' + Strings[i]; - end; - end; - end - else - begin - if Count = 1 then - begin - for i := 0 to iMaxCnt - 1 do - begin - case i of - 0: aRegCombi0 := aRegCombi0 + ',' + Strings[0]; - 1: aRegCombi1 := aRegCombi1 + ',' + Strings[0]; - 2: aRegCombi2 := aRegCombi2 + ',' + Strings[0]; - 3: aRegCombi3 := aRegCombi3 + ',' + Strings[0]; - 4: aRegCombi4 := aRegCombi4 + ',' + Strings[0]; - end; - end; - end - else - begin - // TODO log - end; - end; - finally - Free; - end; - end; - - function MapOperand(aOpTyp: TOpType): String; - begin - case aOpTyp of - otXMMReg: result := 'X'; - otYMMReg: result := 'Y'; - otZMMReg: result := 'Z'; - otEAX, - otRAX, - otREG64, - otREG32, - otREG16, - otREG8: result := 'R'; - otRM32, - otRM64, - otXMMRM, - otXMMRM8, - otXMMRM16, - otYMMRM, - otZMMRM, - otMem32, - otMem8, - otMem16, - otMem64, - otMem128, - otMem256, - otMem512: result := 'M'; - otIMM8: result := 'I'; - otXMEM32: result := 'X32'; - otXMEM64: result := 'X64'; - otYMEM32: result := 'Y32'; - otYMEM64: result := 'Y64'; - otZMEM32: result := 'Z32'; - otZMEM64: result := 'Z64'; - otB32: result := 'B32'; - otB64: result := 'B64'; - otKREG: result := 'K'; - else result := ''; - end; - end; - - function AsmCodeBlockCompare(aAsmCounter: integer; aCompareMode: TAsmCompareMode): String; - var - sReg: string; - begin - result := ''; - - case Fx64 of - true: sReg := 'RAX'; - else sReg := 'EAX'; - end; - - with TStringList.Create do - try - Add(format('%20s%6s ', [' push', sReg])); - Add(format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)])); - Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); - Add(format('%20s%6s', [' pop', sReg])); - - case aComparemode of - cmKORTESTNC: begin - Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); - Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); - end; - cmXORTestNZ: begin - Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); - Add(format('%20s %6s', [' jnz', '@@CHECKRESULT'])); - end; - end; - - result := Text; - finally - Free; - end; - end; - -begin - result := TStringList.Create; - - iAsmCounter := 0; - - OItem1 := TOperandListItem.Create; - try - OItem2 := TOperandListItem.Create; - try - OItem3 := TOperandListItem.Create; - try - OItem4 := TOperandListItem.Create; - try - - UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR - (UpperCase(aInst) = 'VCVTPD2PS') OR - (UpperCase(aInst) = 'VCVTSI2SD') OR - (UpperCase(aInst) = 'VCVTSI2SS') OR - (UpperCase(aInst) = 'VCVTTPD2DQ') or - (UpperCase(aInst) = 'VPMOVZXWQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTPD2UDQ') or - (UpperCase(aInst) = 'VCVTTPD2UDQ') or - (UpperCase(aInst) = 'VCVTUQQ2PS') or - (UpperCase(aInst) = 'VCVTQQ2PS') or - (UpperCase(aInst) = 'VCVTUSI2SD') or - (UpperCase(aInst) = 'VCVTUSI2SS') or - (UpperCase(aInst) = 'VFPCLASSPD') or - (UpperCase(aInst) = 'VFPCLASSPS') or - (UpperCase(aInst) = 'VCMPSS') - - ; - - - MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or - (Pos('VPGATHER', Uppercase(aInst)) = 1) or - (Pos('VPSCATTER', Uppercase(aInst)) = 1) or - (Pos('VSCATTER', Uppercase(aInst)) = 1); - - for il_Op := 1 to 4 do - begin - sl_Prefix := ''; - - case il_Op of - 1: begin - Item := OItem1; - sl_Operand := aOp1; - end; - 2: begin - Item := OItem2; - sl_Operand := aOp2; - end; - 3: begin - Item := OItem3; - sl_Operand := aOp3; - end; - 4: begin - Item := OItem4; - sl_Operand := aOp4; - end; - end; - - sl_Operand := PrepareOperandTyp(sl_Operand); - - if (AnsiSameText(sl_Operand, 'XMMREG')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMReg; - Item.OpActive := true; - - Item.Values.Add('XMM16'); - end - else if (AnsiSameText(sl_Operand, 'XMMREG_M')) or - (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'XMMREG_ER')) or - (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMReg; - Item.OpActive := true; - - //sSuffix := ''; - //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - // - //if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' - // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - // - //Item.Values.Add('XMM0' + sSuffix); - //if (sSuffix <> '') and - // (MaskRegNeeded = false) then Item.Values.Add('XMM0'); - - Item.Values.Add('XMM16'); - end - else if (AnsiSameText(sl_Operand, 'XMMRM')) or - (AnsiSameText(sl_Operand, 'XMMRM_M')) or - (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'XMMRM8')) or - (AnsiSameText(sl_Operand, 'XMMRM8_M')) or - (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM8; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'byte '; - - if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'XMMRM16')) or - (AnsiSameText(sl_Operand, 'XMMRM16_M')) or - (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or - (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or - (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMMRM16; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'word '; - - if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'YMMREG')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMReg; - Item.OpActive := true; - - Item.Values.Add('YMM16'); - end - else if (AnsiSameText(sl_Operand, 'YMMREG_M')) or - (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'YMMREG_ER')) or - (AnsiSameText(sl_Operand, 'YMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMReg; - Item.OpActive := true; - - //sSuffix := ''; - //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - // - //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - // - //Item.Values.Add('YMM0' + sSuffix); - //if (sSuffix <> '') and - // (MaskRegNeeded = false) then Item.Values.Add('YMM0'); - - Item.Values.Add('YMM16'); - end - else if (AnsiSameText(sl_Operand, 'YMMRM')) or - (AnsiSameText(sl_Operand, 'YMMRM_M')) or - (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'YMMRM_ER')) or - (AnsiSameText(sl_Operand, 'YMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - //sSuffix := ''; - //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - // - //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'ZMMREG')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMReg; - Item.OpActive := true; - - Item.Values.Add('ZMM16'); - end - else if (AnsiSameText(sl_Operand, 'ZMMREG_M')) or - (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or - (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or - (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMReg; - Item.OpActive := true; - - //sSuffix := ''; - //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - // - //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - Item.Values.Add('ZMM16'); - end - else if (AnsiSameText(sl_Operand, 'ZMMRM')) or - (AnsiSameText(sl_Operand, 'ZMMRM_M')) or - (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or - (AnsiSameText(sl_Operand, 'ZMMRM_ER')) or - (AnsiSameText(sl_Operand, 'ZMMRM_SAE')) - then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMMRM; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - //sSuffix := ''; - //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' - // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - // - //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' - // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; - - if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'MEM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM8; - Item.OpActive := true; - - - - if UsePrefix then sl_Prefix := 'byte '; - - - sSuffix := ''; - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'MEM16') or - AnsiSameText(sl_Operand, 'MEM16_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM16; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'word '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'MEM32') or - AnsiSameText(sl_Operand, 'MEM32_M') or - AnsiSameText(sl_Operand, 'MEM32_MZ') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'dword '; - - sSuffix := ''; - - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM64')) or - (AnsiSameText(sl_Operand, 'MEM64_M')) or - (AnsiSameText(sl_Operand, 'MEM64_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'qword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM128')) or - (AnsiSameText(sl_Operand, 'MEM128_M')) or - (AnsiSameText(sl_Operand, 'MEM128_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM128; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM256')) or - (AnsiSameText(sl_Operand, 'MEM256_M')) or - (AnsiSameText(sl_Operand, 'MEM256_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM256; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if (AnsiSameText(sl_Operand, 'MEM512')) or - (AnsiSameText(sl_Operand, 'MEM512_M')) or - (AnsiSameText(sl_Operand, 'MEM512_MZ')) then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otMEM512; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'REG8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG8; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg8); - end - else Item.Values.AddStrings(FReg8); - end - else if AnsiSameText(sl_Operand, 'REG16') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG16; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg16); - end - else Item.Values.AddStrings(FReg16); - end - else if AnsiSameText(sl_Operand, 'REG32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG32; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg32Base); - end - else Item.Values.AddStrings(FReg32Base); - end - else if AnsiSameText(sl_Operand, 'REG64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otREG64; - Item.OpActive := true; - - if x64 then - begin - Item.Values.AddStrings(FReg64Base); - end; - end - else if AnsiSameText(sl_Operand, 'RM32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM32; - Item.OpActive := true; - - Item.Values.AddStrings(FReg32Base); - - if UsePrefix then sl_Prefix := 'dword '; - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'RM64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otRM32; - Item.OpActive := true; - - - - if UsePrefix then sl_Prefix := 'qword '; - - if x64 then - begin - Item.Values.AddStrings(FReg64Base); - MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'IMM8') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otIMM8; - Item.OpActive := true; - - Item.Values.Add('0'); - end - else if AnsiSameText(sl_Operand, 'XMEM32') or - AnsiSameText(sl_Operand, 'XMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'oword '; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); - end; - end - else if AnsiSameText(sl_Operand, 'XMEM64') or - AnsiSameText(sl_Operand, 'XMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otXMEM64; - Item.OpActive := true; - - //if UsePrefix then sl_Prefix := 'oword '; - // - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'YMEM32') or - AnsiSameText(sl_Operand, 'YMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'YMEM64') or - AnsiSameText(sl_Operand, 'YMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otYMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'yword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'ZMEM32') or - AnsiSameText(sl_Operand, 'ZMEM32_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM32; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, 'ZMEM64') or - AnsiSameText(sl_Operand, 'ZMEM64_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otZMEM64; - Item.OpActive := true; - - if UsePrefix then sl_Prefix := 'zword '; - - //if x64 then - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); - //end - //else - //begin - // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); - //end; - - sSuffix := ''; - if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; - - if x64 then - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); - end - else - begin - VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); - if (sSuffix <> '') and - (MaskRegNeeded = false) - then - VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); - end; - - end - else if AnsiSameText(sl_Operand, '2B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '4B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '8B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '16B32') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB32; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '2B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '4B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '8B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, '16B64') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otB64; - Item.OpActive := true; - - - if x64 then - begin - MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); - //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); - end - else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); - end - else if AnsiSameText(sl_Operand, 'KREG') or - AnsiSameText(sl_Operand, 'KREG_M') then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otKREG; - Item.OpActive := true; - - Item.Values.Add('K1'); - end - else if trim(sl_Operand) = '' then - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add(''); - end - else - begin - Item.OpNumber := il_Op; - Item.OpTyp := otUnknown; - Item.OpActive := false; - - Item.Values.Add('?' + sl_Operand); - end - - end; - - //sl_RegCombi := ''; - - - il_Operands := 0; - UsedParams := 0; - - if OItem1.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 1; - end; - - if OItem2.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 2; - end; - - if OItem3.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 4; - end; - - if OItem4.OpActive then - begin - inc(il_Operands); - UsedParams := UsedParams or 8; - end; - - case il_Operands of - 1: UseDefault := UsedParams <> 1; - 2: UseDefault := UsedParams <> 3; - 3: UseDefault := UsedParams <> 7; - 4: UseDefault := UsedParams <> 15; - else UseDefault := true; - end; - - // TODO deaktivieren - //UseDefault := true; - - if UseDefault then - begin - sl_Inst := format('%-20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - slRegCombi := TStringList.Create; - try - while slRegCombi.Count < 5 do - slRegCombi.Add(''); - - - //SplitOperands(OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4] - if OItem1.OpActive then - begin - // SplitOperand(OItem1.Values[il_Op1], sRegCombi0,sRegCombi1,sRegCombi2,sRegCombi3,sRegCombi4); - // - end; - finally - FreeAndNil(slRegCombi); - end; - - //sRegCombi0 := ''; - //sRegCombi1 := ''; - //sRegCombi2 := ''; - //sRegCombi3 := ''; - //sRegCombi4 := ''; - // - //if OItem1.OpActive then - //begin - // if sRegCombi0 <> '' then - // begin - // sRegCombi0 := sRegCombi0 + ', '; - // sRegCombi1 := sRegCombi1 + ', '; - // sRegCombi2 := sRegCombi2 + ', '; - // sRegCombi3 := sRegCombi3 + ', '; - // sRegCombi4 := sRegCombi4 + ', '; - // end; - // - // if Pos('|', OItem1.Values[il_Op1]) > 0 then - // begin - // with TStringList.Create do - // try - // Text := Stringreplace(OItem1.Values[il_Op1], '|', #13#10,[rfReplaceAll]); - // iCnt := Count; - // while Count < 5 do Add(''); - // - // sRegCombi0 := sRegCombi0 + Strings[0]; - // sRegCombi1 := sRegCombi1 + Strings[1]; - // sRegCombi2 := sRegCombi2 + Strings[2]; - // sRegCombi3 := sRegCombi3 + Strings[3]; - // sRegCombi4 := sRegCombi4 + Strings[4]; - // - // finally - // Free; - // end; - // end - // else - // begin - // sRegCombi0 := sRegCombi0 + OItem1.Values[il_Op1]; - // sRegCombi1 := sRegCombi1 + OItem1.Values[il_Op1]; - // sRegCombi2 := sRegCombi2 + OItem1.Values[il_Op1]; - // sRegCombi3 := sRegCombi3 + OItem1.Values[il_Op1]; - // sRegCombi4 := sRegCombi4 + OItem1.Values[il_Op1]; - // end; - //end; - // - //if OItem2.OpActive then - //begin - // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - // sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; - //end; - // - //if OItem3.OpActive then - //begin - // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - // sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; - //end; - // - //if OItem4.OpActive then - //begin - // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; - // sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; - //end; - // - //if sl_RegCombi <> '' then - //begin - // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - // result.Add(sl_Inst + sl_RegCombi); - // sl_RegCombi := ''; - //end; - end; - end; - end; - end; - end - else - begin - OpMode := omUnknown; - - iOpNumMRef := -1; - if (OItem1.OpTyp in MEMTYPES) or - (OItem1.OpTyp in BMEMTYPES) then iOpNumMRef := 1 - else if (OItem2.OpTyp in MEMTYPES) or - (OItem2.OpTyp in BMEMTYPES) then iOpNumMRef := 2 - else if (OItem3.OpTyp in MEMTYPES) or - (OItem3.OpTyp in BMEMTYPES) then iOpNumMRef := 3 - else if (OItem4.OpTyp in MEMTYPES) or - (OItem4.OpTyp in BMEMTYPES) then iOpNumMRef := 4; - - - // TODO delete - //if il_Operands = 4 then - - case il_Operands of - 2: begin - if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otXMMReg) then OpMode := omMX - else if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otYMMReg) then OpMode := omMY - else if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otZMMReg) then OpMode := omMZ - - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otB32) then OpMode := omXB32 - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otB64) then OpMode := omXB64 - - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otB32) then OpMode := omYB32 - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otB64) then OpMode := omYB64 - - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otB32) then OpMode := omZB32 - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otB64) then OpMode := omZB64 - - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp in MEMTYPES) then OpMode := omXM - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp in MEMTYPES) then OpMode := omYM - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp in MEMTYPES) then OpMode := omZM - - - - - else - begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - if sLogMsg <> '' then - begin - - if (sLogMsg <> 'KX') and - (sLogMsg <> 'KY') and - (sLogMsg <> 'KZ') and - (sLogMsg <> 'RM') and - (sLogMsg <> 'RX') and - (sLogMsg <> 'XK') and - (sLogMsg <> 'XR') and - (sLogMsg <> 'XX') and - (sLogMsg <> 'XY') and - (sLogMsg <> 'XZ') and - (sLogMsg <> 'YK') and - (sLogMsg <> 'YR') and - (sLogMsg <> 'YX') and - (sLogMsg <> 'YY') and - (sLogMsg <> 'YZ') and - (sLogMsg <> 'ZK') and - (sLogMsg <> 'ZR') and - (sLogMsg <> 'ZX') and - (sLogMsg <> 'ZY') and - (sLogMsg <> 'ZZ') then - - writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); - end; - end; - end; - 3: if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omKXM - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omKYM - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omKZM - - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omKXB32 - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omKXB64 - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omKYB32 - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omKYB64 - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omKZB32 - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omKZB64 - - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp in MEMTYPES) and - (OItem3.OpTyp = otIMM8) then OpMode := omKMI - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otB32) and - (OItem3.OpTyp = otIMM8) then OpMode := omKB32I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otB64) and - (OItem3.OpTyp = otIMM8) then OpMode := omKB64I - - else if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otIMM8) then OpMode := omMXI - else if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otIMM8) then OpMode := omMYI - else if (OItem1.OpTyp in MEMTYPES) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otIMM8) then OpMode := omMZI - - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omXXB32 - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omXXB64 - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otB32) and - (OItem3.OpTyp = otIMM8) then OpMode := omXB32I - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otB64) and - (OItem3.OpTyp = otIMM8) then OpMode := omXB64I - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp in MEMTYPES) and - (OItem3.OpTyp = otIMM8) then OpMode := omXMI - - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omYYB32 - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omYYB64 - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otB32) and - (OItem3.OpTyp = otIMM8) then OpMode := omYB32I - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otB64) and - (OItem3.OpTyp = otIMM8) then OpMode := omYB64I - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp in MEMTYPES) and - (OItem3.OpTyp = otIMM8) then OpMode := omYMI - - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp in MEMTYPES) then OpMode := omZZM - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB32) then OpMode := omZZB32 - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB64) then OpMode := omZZB64 - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otB32) and - (OItem3.OpTyp = otIMM8) then OpMode := omZB32I - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otB64) and - (OItem3.OpTyp = otIMM8) then OpMode := omZB64I - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp in MEMTYPES) and - (OItem3.OpTyp = otIMM8) then OpMode := omZMI - - - else - begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - if sLogMsg <> '' then - begin - if (sLogMsg <> 'RMI') and - (sLogMsg <> 'RRM') and - (sLogMsg <> 'RMR') and - (sLogMsg <> 'KKK') and - (sLogMsg <> 'KKI') and - (sLogMsg <> 'XXX') and - (sLogMsg <> 'YYY') and - (sLogMsg <> 'ZZZ') and - (sLogMsg <> 'XXI') and - (sLogMsg <> 'YYI') and - (sLogMsg <> 'ZZI') and - (sLogMsg <> 'XYI') and - (sLogMsg <> 'YZI') and - (sLogMsg <> 'XZI') and - (sLogMsg <> 'RXI') and - (sLogMsg <> 'RYI') and - (sLogMsg <> 'RZI') and - - - (sLogMsg <> 'XXR') then - - writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); - end; - end; - 4: if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omKXB32I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omKXB64I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omKXMI - - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omKYB32I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omKYB64I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omKYMI - - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omKZB32I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omKZB64I - else if (OItem1.OpTyp = otKReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omKZMI - - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omXXB32I - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omXXB64I - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omYYB32I - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omYYB64I - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB32) and - (OItem4.OpTyp = otIMM8) then OpMode := omZZB32I - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp = otB64) and - (OItem4.OpTyp = otIMM8) then OpMode := omZZB64I - - - else if (OItem1.OpTyp = otXMMReg) and - (OItem2.OpTyp = otXMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omXXMI - else if (OItem1.OpTyp = otYMMReg) and - (OItem2.OpTyp = otYMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omYYMI - else if (OItem1.OpTyp = otZMMReg) and - (OItem2.OpTyp = otZMMReg) and - (OItem3.OpTyp in MEMTYPES) and - (OItem4.OpTyp = otIMM8) then OpMode := omZZMI - else - begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp) + MapOperand(OItem4.Optyp); - if sLogMsg <> '' then - begin - - if (sLogMsg <> 'KXXI') and - (sLogMsg <> 'KYYI') and - (sLogMsg <> 'KZZI') and - (sLogMsg <> 'XXRI') and - (sLogMsg <> 'XXXI') and - (sLogMsg <> 'YYYI') and - (sLogMsg <> 'ZZZI') then - - writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); - end; - end; - - else; - end; - - if OpMode <> omUnknown then - begin - sInstruction := format('%20s', [aInst]); - - for il_Op1 := 0 to OItem1.Values.Count - 1 do - begin - for il_Op2 := 0 to OItem2.Values.Count - 1 do - begin - for il_Op3 := 0 to OItem3.Values.Count - 1 do - begin - for il_Op4 := 0 to OItem4.Values.Count - 1 do - begin - sRegCombi := ''; - - if OItem1.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem1.Values[il_Op1]; - end; - - if OItem2.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem2.Values[il_Op2]; - end; - - if OItem3.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem3.Values[il_Op3]; - end; - - if OItem4.OpActive then - begin - if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; - sRegCombi := sRegCombi + OItem4.Values[il_Op4]; - end; - - if sRegCombi <> '' then - begin - case iOpNumMRef of - 1: sMRef := OItem1.Values[il_Op1]; - 2: sMRef := OItem2.Values[il_Op2]; - 3: sMRef := OItem3.Values[il_Op3]; - 4: sMRef := OItem1.Values[il_Op4]; - else sMRef := ''; - end; - - if ParseBaseIndexReg(sMRef, sBaseReg, sIndexReg) then - begin - result.Add(format('%20s %s', [' pop', sBaseReg])); - result.Add(format('%20s %s', [' push', sBaseReg])); - - if trim(sIndexReg) <> '' then - result.Add(format('%20s%6s, %s', [' xor', sIndexReg, sIndexReg])); - - if OpMode in [omMXI, omMYI, omMZI] then - begin - case Fx64 of - true: begin - result.Add(format('%20s %6s', ['push', 'RDI'])); - result.Add(format('%20s %6s', ['push', 'RCX'])); - result.Add(format('%20s %6s', ['push', 'RAX'])); - - result.Add(format('%20s %6s', ['push', sBaseReg])); - result.Add(format('%20s %6s', ['pop', 'RDI'])); - result.Add(format('%20s %6s', ['mov', 'RCX, sizeof(DataBlock)'])); - result.Add(format('%20s %6s, %s', ['xor', 'RAX', 'RAX'])); - result.Add(format('%20s ', ['rep stosb'])); - result.Add(format('%20s %6s', ['pop', 'RAX'])); - result.Add(format('%20s %6s', ['pop', 'RCX'])); - result.Add(format('%20s %6s', ['pop', 'RDI'])); - end; - else begin - result.Add(format('%20s %6s', ['push', 'EDI'])); - result.Add(format('%20s %6s', ['push', 'ECX'])); - result.Add(format('%20s %6s', ['push', 'EAX'])); - - result.Add(format('%20s %6s', ['push', sBaseReg])); - result.Add(format('%20s %6s', ['pop', 'EDI'])); - result.Add(format('%20s %6s', ['mov', 'ECX, sizeof(DataBlock)'])); - result.Add(format('%20s %6s, %s', ['xor', 'EAX', 'EAX'])); - result.Add(format('%20s ', ['rep stosb'])); - result.Add(format('%20s %6s', ['pop', 'EAX'])); - result.Add(format('%20s %6s', ['pop', 'ECX'])); - result.Add(format('%20s %6s', ['pop', 'EDI'])); - end; - end; - end; - - end; - - - //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); - - inc(iAsmCounter); - case OpMode of - omKXM, - omKYM, - omKZM: begin - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKXB32, - omKXB64, - omKYB32, - omKYB64, - omKZB32, - omKZB64: begin - sMREF := OItem3.Values[il_Op3]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], sMREF])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKMI: begin - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKB32I, - omKB64I: - begin - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - - omMX: begin - result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omMXI: begin - result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omMY: begin - result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omMYI: begin - result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omMZ: begin - result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omMZI: begin - result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); - - result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omXB32, - omXB64: begin - sMREF := OItem2.Values[il_Op2]; - result.Add(format('%20s%6s,%6s + $2000', [aInst, 'XMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - - omXB32I, - omXB64I: begin - sMREF := OItem2.Values[il_Op2]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omXM: begin - result.Add(format('%20s %6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omXXM: begin - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omXXB32, - omXXB64: begin - sMREF := OItem3.Values[il_Op3]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omXMI: begin - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omYB32, - omYB64: begin - sMREF := OItem2.Values[il_Op2]; - result.Add(format('%20s%6s,%6s + $2000', [aInst, 'YMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omYB32I, - omYB64I: - begin - sMREF := OItem2.Values[il_Op2]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - - //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omYM: begin - result.Add(format('%20s %6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omYYM: begin - //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omYYB32, - omYYB64: begin - sMREF := OItem3.Values[il_Op3]; - //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) - // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); - - //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - - end; - omYMI: begin - //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omZB32, - omZB64: begin - sMREF := OItem2.Values[il_Op2]; - result.Add(format('%20s%6s,%6s + $2000', [aInst, 'ZMM1', sMREF])); - result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omZB32I, - omZB64I: - begin - sMREF := OItem2.Values[il_Op2]; - //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - - //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - // - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - - end; - omZM: begin - result.Add(format('%20s %6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omZZM: begin - //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - // - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omZZB32, - omZZB64: begin - sMREF := OItem3.Values[il_Op3]; - //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) - // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); - - //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); - //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); - //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); - //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - // - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - - result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - - end; - omZMI: begin - //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - //result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - // - //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); - //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); - //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); - // - //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); - //result.Add(''); - result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); - result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - - omKXB32I, - omKXB64I: - begin - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKXMI: - begin - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKYB32I, - omKYB64I: - begin - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - omKYMI: - begin - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - - omXXB32I, - omXXB64I: - begin - sMREF := OItem3.Values[il_Op3]; - - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omXXMI: - begin - sMREF := OItem3.Values[il_Op3]; - - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omYYB32I, - omYYB64I, - omYYMI: - begin - sMREF := OItem3.Values[il_Op3]; - - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - omKZB32I, - omKZB64I, - omKZMI: - begin - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); - end; - //omKZMI: - // begin - // sMREF := OItem3.Values[il_Op3]; - // - // result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - // result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - // - // result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - // end; - - omZZB32I, - omZZB64I, - omZZMI: - begin - sMREF := OItem3.Values[il_Op3]; - - result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); - result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); - - result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); - end; - else begin - sLogMsg := ''; - sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); - writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); - end; - end; - - sRegCombi := ''; - end; - end; - end; - end; - end; - end; - - - - //sl_Inst := format('%-20s', [aInst]); - // - //for il_Op1 := 0 to OItem1.Values.Count - 1 do - //begin - // if OItem1.OpActive then - // begin - // sl_RegCombi1 := OItem1.Values[il_Op1]; - // end - // else sl_RegCombi1 := ''; - // - // for il_Op2 := 0 to OItem2.Values.Count - 1 do - // begin - // if OItem2.OpActive then - // begin - // sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; - // end - // else sl_RegCombi2 := sl_RegCombi1; - // - // for il_Op3 := 0 to OItem3.Values.Count - 1 do - // begin - // if OItem3.OpActive then - // begin - // sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; - // end - // else sl_RegCombi3 := sl_RegCombi2; - // - // for il_Op4 := 0 to OItem4.Values.Count - 1 do - // begin - // if OItem4.OpActive then - // begin - // sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; - // end - // else sl_RegCombi := sl_RegCombi3; - // - // if (sl_RegCombi <> '') and - // ( - // (OItem1.OpActive and (OItem1.OpTyp in OTMEMTYPES)) or - // (OItem2.OpActive and (OItem2.OpTyp in OTMEMTYPES)) or - // (OItem3.OpActive and (OItem3.OpTyp in OTMEMTYPES)) or - // (OItem4.OpActive and (OItem4.OpTyp in OTMEMTYPES)) - // ) then - // begin - // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); - // result.Add(sl_Inst + sl_RegCombi); - // - // - // - // sl_RegCombi := ''; - // end; - // end; - // end; - // end; - //end; - end; - finally - FreeAndNil(OItem4); - end; - finally - FreeAndNil(OItem3); - end; - finally - FreeAndNil(OItem2); - end; - finally - FreeAndNil(OItem1); - end; -end; - - -constructor TAsmTestGenerator.Create; -begin - inherited; - - FX64 := true; - FAVX512 := false; - - FReg8 := TStringList.Create; - FReg16 := TStringList.Create; - - FReg32Base := TStringList.Create; - FReg32Index := TStringList.Create; - FReg64Base := TStringList.Create; - FReg64Index := TStringList.Create; - FReg6432Base := TStringList.Create; - FReg6432Index := TStringList.Create; - FReg32XMMIndex := TStringList.Create; - FReg32YMMIndex := TStringList.Create; - FReg32ZMMIndex := TStringList.Create; - FReg64XMMIndex := TStringList.Create; - FReg64YMMIndex := TStringList.Create; - FReg64ZMMIndex := TStringList.Create; - FRegKREG := TStringList.Create; - - FReg8.Add('AL'); - FReg8.Add('BL'); - FReg8.Add('CL'); - FReg8.Add('DL'); - - - FReg16.Add('AX'); - FReg16.Add('BX'); - FReg16.Add('CX'); - FReg16.Add('DX'); - - - FReg32Base.Add('EAX'); - FReg32Base.Add('EBX'); - FReg32Base.Add('ECX'); - FReg32Base.Add('EDX'); - //FReg32Base.Add('ESP'); - //FReg32Base.Add('EBP'); - FReg32Base.Add('EDI'); - FReg32Base.Add('ESI'); - - - FReg32Index.Add('EAX'); - FReg32Index.Add('EBX'); - FReg32Index.Add('ECX'); - FReg32Index.Add('EDX'); - //FReg32Index.Add('EBP'); - FReg32Index.Add('EDI'); - FReg32Index.Add('ESI'); - - - FReg64Base.Add('RAX'); - FReg64Base.Add('RBX'); - FReg64Base.Add('RCX'); - FReg64Base.Add('RDX'); - //FReg64Base.Add('RSP'); - //FReg64Base.Add('RBP'); - FReg64Base.Add('RDI'); - FReg64Base.Add('RSI'); - FReg64Base.Add('R8'); - FReg64Base.Add('R9'); - FReg64Base.Add('R10'); - FReg64Base.Add('R11'); - FReg64Base.Add('R12'); - FReg64Base.Add('R13'); - FReg64Base.Add('R14'); - FReg64Base.Add('R15'); - - FReg64Index.Add('RAX'); - FReg64Index.Add('RBX'); - FReg64Index.Add('RCX'); - FReg64Index.Add('RDX'); - //FReg64Index.Add('RBP'); - FReg64Index.Add('RDI'); - FReg64Index.Add('RSI'); - FReg64Index.Add('R8'); - FReg64Index.Add('R9'); - FReg64Index.Add('R10'); - FReg64Index.Add('R11'); - FReg64Index.Add('R12'); - FReg64Index.Add('R13'); - FReg64Index.Add('R14'); - FReg64Index.Add('R15'); - - FReg6432Base.Add('EAX'); - FReg6432Base.Add('EBX'); - FReg6432Base.Add('ECX'); - FReg6432Base.Add('EDX'); - FReg6432Base.Add('ESP'); - //FReg6432Base.Add('EBP'); - FReg6432Base.Add('EDI'); - FReg6432Base.Add('ESI'); - FReg6432Base.Add('R8D'); - FReg6432Base.Add('R9D'); - FReg6432Base.Add('R10D'); - FReg6432Base.Add('R11D'); - FReg6432Base.Add('R12D'); - FReg6432Base.Add('R13D'); - FReg6432Base.Add('R14D'); - FReg6432Base.Add('R15D'); - - FReg6432Index.Add('EAX'); - FReg6432Index.Add('EBX'); - FReg6432Index.Add('ECX'); - FReg6432Index.Add('EDX'); - //FReg6432Index.Add('EBP'); - FReg6432Index.Add('EDI'); - FReg6432Index.Add('ESI'); - FReg6432Index.Add('R8D'); - FReg6432Index.Add('R9D'); - FReg6432Index.Add('R10D'); - FReg6432Index.Add('R11D'); - FReg6432Index.Add('R12D'); - FReg6432Index.Add('R13D'); - FReg6432Index.Add('R14D'); - FReg6432Index.Add('R15D'); - - FReg32XMMIndex.ADD('XMM0'); - FReg32XMMIndex.ADD('XMM1'); - FReg32XMMIndex.ADD('XMM2'); - FReg32XMMIndex.ADD('XMM3'); - FReg32XMMIndex.ADD('XMM4'); - FReg32XMMIndex.ADD('XMM5'); - FReg32XMMIndex.ADD('XMM6'); - FReg32XMMIndex.ADD('XMM7'); - - FReg32YMMIndex.ADD('YMM0'); - FReg32YMMIndex.ADD('YMM1'); - FReg32YMMIndex.ADD('YMM2'); - FReg32YMMIndex.ADD('YMM3'); - FReg32YMMIndex.ADD('YMM4'); - FReg32YMMIndex.ADD('YMM5'); - FReg32YMMIndex.ADD('YMM6'); - FReg32YMMIndex.ADD('YMM7'); - - FReg32ZMMIndex.ADD('ZMM0'); - FReg32ZMMIndex.ADD('ZMM1'); - FReg32ZMMIndex.ADD('ZMM2'); - FReg32ZMMIndex.ADD('ZMM3'); - FReg32ZMMIndex.ADD('ZMM4'); - FReg32ZMMIndex.ADD('ZMM5'); - FReg32ZMMIndex.ADD('ZMM6'); - FReg32ZMMIndex.ADD('ZMM7'); - - - FReg64XMMIndex.ADD('XMM0'); - FReg64XMMIndex.ADD('XMM1'); - FReg64XMMIndex.ADD('XMM2'); - FReg64XMMIndex.ADD('XMM3'); - FReg64XMMIndex.ADD('XMM4'); - FReg64XMMIndex.ADD('XMM5'); - FReg64XMMIndex.ADD('XMM6'); - FReg64XMMIndex.ADD('XMM7'); - FReg64XMMIndex.ADD('XMM8'); - FReg64XMMIndex.ADD('XMM9'); - FReg64XMMIndex.ADD('XMM10'); - FReg64XMMIndex.ADD('XMM11'); - FReg64XMMIndex.ADD('XMM12'); - FReg64XMMIndex.ADD('XMM13'); - FReg64XMMIndex.ADD('XMM14'); - FReg64XMMIndex.ADD('XMM15'); - - - FReg64YMMIndex.ADD('YMM0'); - FReg64YMMIndex.ADD('YMM1'); - FReg64YMMIndex.ADD('YMM2'); - FReg64YMMIndex.ADD('YMM3'); - FReg64YMMIndex.ADD('YMM4'); - FReg64YMMIndex.ADD('YMM5'); - FReg64YMMIndex.ADD('YMM6'); - FReg64YMMIndex.ADD('YMM7'); - FReg64YMMIndex.ADD('YMM8'); - FReg64YMMIndex.ADD('YMM9'); - FReg64YMMIndex.ADD('YMM10'); - FReg64YMMIndex.ADD('YMM11'); - FReg64YMMIndex.ADD('YMM12'); - FReg64YMMIndex.ADD('YMM13'); - FReg64YMMIndex.ADD('YMM14'); - FReg64YMMIndex.ADD('YMM15'); - - FReg64ZMMIndex.ADD('ZMM0'); - FReg64ZMMIndex.ADD('ZMM1'); - FReg64ZMMIndex.ADD('ZMM2'); - FReg64ZMMIndex.ADD('ZMM3'); - FReg64ZMMIndex.ADD('ZMM4'); - FReg64ZMMIndex.ADD('ZMM5'); - FReg64ZMMIndex.ADD('ZMM6'); - FReg64ZMMIndex.ADD('ZMM7'); - FReg64ZMMIndex.ADD('ZMM8'); - FReg64ZMMIndex.ADD('ZMM9'); - FReg64ZMMIndex.ADD('ZMM10'); - FReg64ZMMIndex.ADD('ZMM11'); - FReg64ZMMIndex.ADD('ZMM12'); - FReg64ZMMIndex.ADD('ZMM13'); - FReg64ZMMIndex.ADD('ZMM14'); - FReg64ZMMIndex.ADD('ZMM15'); - FReg64ZMMIndex.ADD('ZMM16'); - FReg64ZMMIndex.ADD('ZMM17'); - FReg64ZMMIndex.ADD('ZMM18'); - FReg64ZMMIndex.ADD('ZMM19'); - FReg64ZMMIndex.ADD('ZMM20'); - FReg64ZMMIndex.ADD('ZMM21'); - FReg64ZMMIndex.ADD('ZMM22'); - FReg64ZMMIndex.ADD('ZMM23'); - FReg64ZMMIndex.ADD('ZMM24'); - FReg64ZMMIndex.ADD('ZMM25'); - FReg64ZMMIndex.ADD('ZMM26'); - FReg64ZMMIndex.ADD('ZMM27'); - FReg64ZMMIndex.ADD('ZMM28'); - FReg64ZMMIndex.ADD('ZMM29'); - FReg64ZMMIndex.ADD('ZMM30'); - FReg64ZMMIndex.ADD('ZMM31'); - - FRegKREG.ADD('K0'); - FRegKREG.ADD('K1'); - FRegKREG.ADD('K2'); - FRegKREG.ADD('K3'); - FRegKREG.ADD('K4'); - FRegKREG.ADD('K5'); - FRegKREG.ADD('K6'); - FRegKREG.ADD('K7'); - -end; - -destructor TAsmTestGenerator.Destroy; -begin - FreeAndNil(FReg8); - FreeAndNil(FReg16); - - FreeAndNil(FReg32Base); - FreeAndNil(FReg32Index); - FreeAndNil(FReg64Base); - FreeAndNil(FReg64Index); - FreeAndNil(FReg6432Base); - FreeAndNil(FReg6432Index); - - FreeAndNil(FReg32XMMIndex); - FreeAndNil(FReg32YMMIndex); - FreeAndNil(FReg32ZMMIndex); - FreeAndNil(FReg64XMMIndex); - FreeAndNil(FReg64YMMIndex); - FreeAndNil(FReg64ZMMIndex); - - FreeAndnil(FRegKREG); - - inherited; -end; - -procedure TAsmTestGenerator.MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, - aSLIndexReg, aRList: TStringList); -var - il_Base: integer; - il_Index: integer; -begin - - for il_Base := 0 to aSLBaseReg.Count - 1 do - begin - aRList.Add(format(aPrefix + '[%s]%s', [aSLBaseReg[il_Base], aSuffix])); - - for il_Index := 0 to aSLIndexReg.Count - 1 do - begin - aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s + $10]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s + $40]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s - $10]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s - $40]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - - - aRList.Add(format(aPrefix + '[%s + %s * 2]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 4]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 8]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - - aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 8 + 64]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - end; - end; -end; - -procedure TAsmTestGenerator.MemRegBaseIndexCombiCDISP8N(const aPrefix, - aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); -var - iBase: integer; - iIndex: integer; - iOffset: integer; -begin - - for iBase := 0 to aSLBaseReg.Count - 1 do - begin - for iOffset := 0 to 63 do - begin - aRList.Add(format(aPrefix + '[%s +%2d]', [aSLBaseReg[iBase], iOffset])); - - for iIndex := 0 to aSLIndexReg.Count - 1 do - begin - if aSLBaseReg[iBase] <> aSLIndexReg[iIndex] then - begin - aRList.Add(format(aPrefix + '[%s + %s + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); - aRList.Add(format(aPrefix + '[%s + %s * 2 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); - aRList.Add(format(aPrefix + '[%s + %s * 4 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); - aRList.Add(format(aPrefix + '[%s + %s * 8 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); - end; - end; - end; - end; -end; - -procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; - aSLBaseReg, aSLIndexReg, aRList: TStringList); -var - il_Base: integer; - il_Index: integer; -begin - - //for il_Index := 0 to aSLIndexReg.Count - 1 do - //begin - // aRList.Add(format(aPrefix + '[%s]', [aSLIndexReg[il_Index]])); - // - // aRList.Add(format(aPrefix + '[%s * 2]', [aSLIndexReg[il_Index]])); - // aRList.Add(format(aPrefix + '[%s * 4]', [aSLIndexReg[il_Index]])); - // aRList.Add(format(aPrefix + '[%s * 8]', [aSLIndexReg[il_Index]])); - // - // aRList.Add(format(aPrefix + '[%s * 2 + 16]', [aSLIndexReg[il_Index]])); - // aRList.Add(format(aPrefix + '[%s * 4 + 32]', [aSLIndexReg[il_Index]])); - // aRList.Add(format(aPrefix + '[%s * 8 + 48]', [aSLIndexReg[il_Index]])); - //end; - - - for il_Base := 0 to aSLBaseReg.Count - 1 do - begin - //aRList.Add(format(aPrefix + '[%s]', [aSLBaseReg[il_Base]])); - - for il_Index := 0 to aSLIndexReg.Count - 1 do - begin - aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - - aRList.Add(format(aPrefix + '[%s + %s * 2]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 4]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - aRList.Add(format(aPrefix + '[%s + %s * 8]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); - - //aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); - //aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); - //aRList.Add(format(aPrefix + '[%s + %s * 8 + 48]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); - - - aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLIndexReg[il_Index], aSLBaseReg[il_Base], aSuffix])); - - //aRList.Add(format(aPrefix + '[%s + %s + 16]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]])); - end; - end; -end; - -function TAsmTestGenerator.ParseBaseIndexReg(const aOp: string; var aBaseReg, - aIndexReg: string): boolean; -var - iStartPos: integer; - iEndPos: integer; - iPos: integer; - sOp: string; - sBaseReg: string; - sIndexReg: string; -begin - result := false; - - aBaseReg := ''; - aIndexReg := ''; - - iStartPos := Pos('[', aOp); - iEndPos := Pos(']', aOp); - - if (iStartPos > 0) and - (iEndPos > 0) and - (iStartPos < iEndPos) then - begin - sOp := trim(copy(aOp, iStartPos + 1, iEndPos - iStartPos - 1)); - - with TStringList.Create do - try - CommaText := StringReplace(sOp, '+', ',', [rfReplaceAll]); - - while Count < 2 do Add(''); - - sBaseReg := trim(Strings[0]); - - if (FReg32Base.IndexOf(sBasereg) >= 0) or - (FReg64Base.IndexOf(sBasereg) >= 0) or - (FReg6432Base.IndexOf(sBasereg) >= 0) then - aBaseReg := sBaseReg; - - sIndexReg := trim(Strings[1]); - - if (FReg32Index.IndexOf(sIndexReg) >= 0) or - (FReg64Index.IndexOf(sIndexReg) >= 0) or - (FReg6432Index.IndexOf(sIndexReg) >= 0) then - aIndexReg := sIndexReg; - - result := trim(aBasereg) <> ''; - finally - Free; - end; - end; -end; - -class procedure TAsmTestGenerator.CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, - aOp4: String; aSL: TStringList); -var - sl: TStringList; -begin - with TAsmTestGenerator.Create do - try - Fx64 := aX64; - FAVX512 := aAVX512; - FSAE := aSAE; - - sl := InternalCalcTestData(aInst, aOp1, aOp2, aOp3, aOp4); - try - aSL.AddStrings(sl); - finally - FreeAndNil(sl); - end; - finally - Free; - end; -end; - -class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, - aOp4: String; aSL: TStringList); -var - sl: TStringList; -begin - with TAsmTestGenerator.Create do - try - Fx64 := aX64; - FAVX512 := aAVX512; - FSAE := aSAE; - - sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4); - try - aSL.AddStrings(sl); - finally - FreeAndNil(sl); - end; - finally - Free; - end; -end; - -class procedure TAsmTestGenerator.CalcTestDataCDisp8(aX64, aAVX512, - aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); -var - sl: TStringList; -begin - with TAsmTestGenerator.Create do - try - Fx64 := aX64; - FAVX512 := aAVX512; - FSAE := aSAE; - - sl := InternalCalcTestDataCDisp8(aInst, aOp1, aOp2, aOp3, aOp4); - try - aSL.AddStrings(sl); - finally - FreeAndNil(sl); - end; - finally - Free; - end; -end; - - - -class procedure TAsmTestGenerator.CalcTestInstFile; -var - i,j: integer; - sInst: string; - sI386: string; - sX8664: string; - sAVX512: string; - sOperands: string; - - sLine: string; - - - sl: TStringList; - bVEX: boolean; - bEVEX: boolean; - b256 : boolean; - b512 : boolean; -begin - sl := TStringList.Create; - try - - //tinsentry=packed record - // opcode : tasmop; - // ops : byte; - // //optypes : array[0..max_operands-1] of longint; - // optypes : array[0..3] of int64; //TG - // code : array[0..11] of char; - // flags : tinsflags; - //end; - - for i := 0 to length(InsTab) - 1 do - begin - bVEX := false; - bEVEX := false; - b256 := false; - b512 := false; - - //TG TODO delete - if instab[i].opcode = a_vtestps then - begin - b512 := b512; - end; - - for j := 0 to length(InsTab[i].code) - 1 do - begin - case ord(InsTab[i].code[j]) of - 0: break; - 1,2,3: break; - 232: bEVEX := true; - 233: b512 := true; - 242: bVEX := true; - 244: b256 := true; - end; - end; - - if bVEX or bEVEX then - begin - sInst := std_op2str[InsTab[i].opcode]; - sI386 := '1'; - sX8664 := '1'; - if IF_X86_64 in InsTab[i].flags then - begin - sI386 := '0'; - end; - - if bEVEX then sAVX512 := '1' - else sAVX512 := '0'; - - sOperands := ''; - for j := 0 to 3 do - begin - case InsTab[i].optypes[j] of - OT_XMMREG: sOperands := sOperands + 'XMMREG,'; - OT_XMMREG_M: sOperands := sOperands + 'XMMREG_M,'; - OT_XMMREG_MZ: sOperands := sOperands + 'XMMREG_MZ,'; - OT_XMMREG_ER: sOperands := sOperands + 'XMMREG_ER,'; - OT_XMMREG_SAE: sOperands := sOperands + 'XMMREG_SAE,'; - OT_XMMRM: sOperands := sOperands + 'XMMRM,'; - OT_XMMRM_MZ: sOperands := sOperands + 'XMMRM_MZ,'; - - OT_YMMREG: sOperands := sOperands + 'YMMREG,'; - OT_YMMREG_M: sOperands := sOperands + 'YMMREG_M,'; - OT_YMMREG_MZ: sOperands := sOperands + 'YMMREG_MZ,'; - OT_YMMREG_ER: sOperands := sOperands + 'YMMREG_ER,'; - OT_YMMREG_SAE: sOperands := sOperands + 'YMMREG_SAE,'; - OT_YMMRM: sOperands := sOperands + 'YMMRM,'; - OT_YMMRM_MZ: sOperands := sOperands + 'YMMRM_MZ,'; - - OT_ZMMREG: sOperands := sOperands + 'ZMMREG,'; - OT_ZMMREG_M: sOperands := sOperands + 'ZMMREG_M,'; - OT_ZMMREG_MZ: sOperands := sOperands + 'ZMMREG_MZ,'; - OT_ZMMREG_ER: sOperands := sOperands + 'ZMMREG_ER,'; - OT_ZMMREG_SAE: sOperands := sOperands + 'ZMMREG_SAE,'; - OT_ZMMRM: sOperands := sOperands + 'ZMMRM,'; - OT_ZMMRM_MZ: sOperands := sOperands + 'ZMMRM_MZ,'; - - OT_MEM32: sOperands := sOperands + 'MEM32,'; - OT_MEM64: sOperands := sOperands + 'MEM64,'; - OT_MEM128: sOperands := sOperands + 'MEM128,'; - OT_MEM256: sOperands := sOperands + 'MEM256,'; - OT_MEM512: sOperands := sOperands + 'MEM512,'; - - OT_REG32: sOperands := sOperands + 'REG32,'; - OT_REG64: sOperands := sOperands + 'REG64,'; - ot_rm_gpr or ot_bits32: - sOperands := sOperands + 'RM32,'; - ot_rm_gpr or ot_bits64: - sOperands := sOperands + 'RM64,'; - - OT_XMEM32: sOperands := sOperands + 'XMEM32,'; - OT_XMEM64: sOperands := sOperands + 'XMEM64,'; - - OT_YMEM32: sOperands := sOperands + 'YMEM32,'; - OT_YMEM64: sOperands := sOperands + 'YMEM64,'; - - OT_IMM8: sOperands := sOperands + 'IMM8,'; - OT_NONE: sOperands := sOperands + ','; - - OT_BMEM32: if b512 then sOperands := sOperands + '16B32,' - else if b256 then sOperands := sOperands + '8B32,' - else sOperands := sOperands + '4B32,'; - OT_BMEM64: if b512 then sOperands := sOperands + '8B32,' - else if b256 then sOperands := sOperands + '4B32,' - else sOperands := sOperands + '2B64,'; - - OT_KREG: sOperands := sOperands + 'KREG,'; - OT_KREG_M: sOperands := sOperands + 'KREG_M,'; - - else sOperands := sOperands; - end; - end; - - sOperands := copy(sOperands, 1, length(sOperands) - 1); - - sl.Add(format('FOpCodeList.Add(''%s,%s,%s,%s,%s'');', [sInst, sI386, sX8664, sAVX512, sOperands])); - end; - - end; - - sl.Savetofile('/tmp/fpcavx512.txt'); - - // std_op2str - - finally - FreeAndnil(sl); - end; -end; - -class procedure TAsmTestGenerator.ListMemRefState; -var - i: integer; - sGasSufffix: string; - mrsize: TMemRefSizeInfo; - opcode: tasmop; - sl: TStringList; - slEmpty: TStringList; -begin - BuildInsTabCache; - BuildInsTabMemRefSizeInfoCache; - - slEmpty := TStringList.Create; - try - for mrsize := low(TMemRefSizeInfo) to high(TMemRefSizeInfo) do - begin - - sl := TStringList.Create; - try - for opcode:=low(tasmop) to high(tasmop) do - begin - if InsTabMemRefSizeInfoCache^[opcode].MemRefSize = mrsize then - begin - sGasSufffix:=''; - if gas_needsuffix[opcode] <> AttSufNone then - sGasSufffix:=GetEnumName(Typeinfo(TAttSuffix), ord(gas_needsuffix[opcode])); - - sl.add(format('%-25s: %s: %s', [GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize)), std_op2str[opcode], sGasSufffix])); - end; - end; - - sl.Sort; - - if sl.Count > 0 then - begin - writeln; - - writeln(sl.text); - end - else slEmpty.Add(GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize))); - - - finally - FreeAndNil(sl); - end; - end; - - slEmpty.Sort; - writeln(''); - writeln(slEmpty.Text); - finally - FreeAndNil(slEmpty); - end; - - if assigned(instabcache) then - begin - dispose(instabcache); - instabcache:=nil; - end; - - if assigned(InsTabMemRefSizeInfoCache) then - begin - dispose(InsTabMemRefSizeInfoCache); - InsTabMemRefSizeInfoCache:=nil; - end; - - -end; - -end. From d6235174ac37b3aa7ba6ee1e03a5abe450d2a4d5 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 5 Mar 2021 09:02:53 +0000 Subject: [PATCH 070/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48879 - --- tests/utils/avx/asmtestgenerator.pas | 6407 ++++++++++++++++++++++++++ 1 file changed, 6407 insertions(+) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index e69de29bb2..6ad2dbc817 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -0,0 +1,6407 @@ +{ + + Copyright (C) + + This source is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This code is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. + + A copy of the GNU General Public License is available on the World Wide Web + at . You can also obtain it by writing + to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. +} + +{$mode objfpc} + +unit asmtestgenerator; + +interface + +uses BaseList, Classes; + +type + TOpType = (otUnknown, otXMMReg, otXMMRM, otXMMRM16, otXMMRM8, otYMMReg, otYMMRM, otZMMReg, otZMMRM, otEAX, otRAX, otMem32, + otMem8, otMem16, otMem64, otMem128, otMem256, otMem512, otREG64, otREG32, otREG16, otREG8, otRM32, otRM64, otIMM8, + otXMEM32, otXMEM64, otYMEM32, otYMEM64, otZMEM32, otZMEM64, + otB32, otB64, otKREG); + + TOpMemType = Set of TOpType; + + TAsmCompareMode = (cmKORTESTNC, cmXORTestNZ); + + TOpMode = (omUnknown, + omMX, omMY, omMZ, + omXB32, omXB64, omYB32, omYB64, omZB32, omZB64, + omXM, omYM, omZM, + + + omKXM, omKYM, omKZM, + omKXB32, omKXB64, omKYB32, omKYB64, omKZB32, omKZB64, + omKXB32I, omKXB64I, omKXMI, omKYB32I, omKYB64I, omKYMI, omKZB32I, omKZB64I, omKZMI, + + omKMI, omKB32I, omKB64I, + omMXI, omMYI, omMZI, + omXXM, omXXB32, omXXB64, omXMI, omXB32I, omXB64I, + omXXMI, omXXB32I, omXXB64I, + + omYYM, omYYB32, omYYB64, omYMI, omYB32I, omYB64I, + omYYMI, omYYB32I, omYYB64I, + omZZM, omZZB32, omZZB64, omZMI, omZB32I, omZB64I, + omZZMI, omZZB32I, omZZB64I); + + TOperandListItem = class(TObject) + private + FOpActive: boolean; + FOpNumber: integer; + FOpTyp: TOpType; + FValues: TStringList; + public + constructor Create; + destructor Destroy; override; + + property OpNumber: integer read FOpNumber write FOpNumber; + property OpTyp: TOpType read FOpTyp write FOpTyp; + property OpActive: boolean read FOpActive write FOpActive; + + property Values: TStringList read FValues; + end; + + TOperandList = class(TBaseList) + private + function GetItems(aIndex: integer): TOperandListItem; + + public + function Add(aItem: TOperandListItem): integer; + + property Items[aIndex: integer]: TOperandListItem read GetItems; + end; + + + { TAsmTestGenerator } + + TAsmTestGenerator = class(TObject) + private + FReg8 : TStringList; + FReg16 : TStringList; + FReg32Base : TStringList; + FReg32Index : TStringList; + FReg64Base : TStringList; + FReg64Index : TStringList; + FReg6432Base : TStringList; + FReg6432Index : TStringList; + FReg32XMMIndex : TStringList; + FReg32YMMIndex : TStringList; + FReg32ZMMIndex : TStringList; + FReg64XMMIndex : TStringList; + FReg64YMMIndex : TStringList; + FReg64ZMMIndex : TStringList; + FRegKREG : TStringList; + + Fx64: boolean; + FAVX512: boolean; + FSAE: boolean; + + procedure MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); + procedure MemRegBaseIndexCombiCDISP8N(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); + procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); + function ParseBaseIndexReg(const aOp: string; var aBaseReg, aIndexReg: string): boolean; + + function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + function InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + function InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList; + public + constructor Create; + destructor Destroy; override; + + class procedure CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + class procedure CalcTestDataCDisp8(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); + + + class procedure CalcTestInstFile; + class procedure ListMemRefState; + + property x64: boolean read Fx64; + end; + +implementation + +uses SysUtils, Dialogs, typinfo; + +type + TAsmOp={$i ../../../compiler/x86_64/x8664op.inc} + TAttSuffix = (AttSufNONE,AttSufINT,AttSufFPU,AttSufFPUint,AttSufINTdual,AttSufMM,AttSufMMX,AttSufMMS); + + TMemRefSizeInfo = (msiUnknown, msiUnsupported, msiNoSize, msiNoMemRef, + msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32, + msiMultipleMinSize64, msiMultipleMinSize128, msiMultipleminSize256, msiMultipleMinSize512, + msiMemRegSize, msiMemRegx16y32, msiMemRegx16y32z64, msiMemRegx32y64, msiMemRegx32y64z128, msiMemRegx64y128, msiMemRegx64y128z256, + msiMemRegx64y256, msiMemRegx64y256z512, + msiMem8, msiMem16, msiMem32, msiBMem32, msiMem64, msiBMem64, msiMem128, msiMem256, msiMem512, + msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64, + msiVMemMultiple, msiVMemRegSize, + msiMemRegConst128,msiMemRegConst256,msiMemRegConst512); + + TMemRefSizeInfoBCST = (msbUnknown, msbBCST32, msbBCST64, msbMultiple); + TMemRefSizeInfoBCSTType = (btUnknown, bt1to2, bt1to4, bt1to8, bt1to16); + + TEVEXTupleState = (etsUnknown, etsIsTuple, etsNotTuple); + TConstSizeInfo = (csiUnknown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64); + + + TInsTabMemRefSizeInfoRec = record + MemRefSize : TMemRefSizeInfo; + MemRefSizeBCST : TMemRefSizeInfoBCST; + BCSTXMMMultiplicator : byte; + ExistsSSEAVX : boolean; + ConstSize : TConstSizeInfo; + BCSTTypes : Set of TMemRefSizeInfoBCSTType; + RegXMMSizeMask : int64; + RegYMMSizeMask : int64; + RegZMMSizeMask : int64; + end; + + + TInsTabMemRefSizeInfoCache=array[TasmOp] of TInsTabMemRefSizeInfoRec; + PInsTabMemRefSizeInfoCache=^TInsTabMemRefSizeInfoCache; + + TInsTabCache=array[TasmOp] of longint; + PInsTabCache=^TInsTabCache; + + +const + instabentries = {$i ../../../compiler/x86_64/x8664nop.inc} + gas_needsuffix:array[tasmop] of TAttSuffix={$i ../../../compiler/x86_64/x8664ats.inc} + + MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultipleMinSize8, + msiMultipleMinSize16, msiMultipleMinSize32, + msiMultipleMinSize64, msiMultipleMinSize128, + msiMultipleMinSize256, msiMultipleMinSize512, + msiVMemMultiple]; + + MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64, + msiZMem32, msiZMem64, + msiVMemMultiple, msiVMemRegSize]; + + MEMTYPES: TOpMemType = [otXMMRM, otXMMRM16, otXMMRM8, otYMMRM, otZMMRM, + otMem8, otMem16, otMem32, otMem64, otMem128, otMem256, otMem512, + otRM32, otRM64]; + BMEMTYPES: TOpMemType = [otB32, otB64]; + +var + InsTabCache : PInsTabCache; + InsTabMemRefSizeInfoCache: PInsTabMemRefSizeInfoCache; + +type + + + op2strtable=array[tasmop] of string[16]; + + {Instruction flags } + tinsflag = ( + { please keep these in order and in sync with IF_SMASK } + IF_SM, { size match first two operands } + IF_SM2, + IF_SB, { unsized operands can't be non-byte } + IF_SW, { unsized operands can't be non-word } + IF_SD, { unsized operands can't be nondword } + + { unsized argument spec } + { please keep these in order and in sync with IF_ARMASK } + IF_AR0, { SB, SW, SD applies to argument 0 } + IF_AR1, { SB, SW, SD applies to argument 1 } + IF_AR2, { SB, SW, SD applies to argument 2 } + + IF_PRIV, { it's a privileged instruction } + IF_SMM, { it's only valid in SMM } + IF_PROT, { it's protected mode only } + IF_NOX86_64, { removed instruction in x86_64 } + IF_UNDOC, { it's an undocumented instruction } + IF_FPU, { it's an FPU instruction } + IF_MMX, { it's an MMX instruction } + { it's a 3DNow! instruction } + IF_3DNOW, + { it's a SSE (KNI, MMX2) instruction } + IF_SSE, + { SSE2 instructions } + IF_SSE2, + { SSE3 instructions } + IF_SSE3, + { SSE64 instructions } + IF_SSE64, + { SVM instructions } + IF_SVM, + { SSE4 instructions } + IF_SSE4, + IF_SSSE3, + IF_SSE41, + IF_SSE42, + IF_MOVBE, + IF_CLMUL, + IF_AVX, + IF_AVX2, + IF_AVX512, + IF_BMI1, + IF_BMI2, + { Intel ADX (Multi-Precision Add-Carry Instruction Extensions) } + IF_ADX, + IF_16BITONLY, + IF_FMA, + IF_FMA4, + IF_TSX, + IF_RAND, + IF_XSAVE, + IF_PREFETCHWT1, + + { mask for processor level } + { please keep these in order and in sync with IF_PLEVEL } + IF_8086, { 8086 instruction } + IF_186, { 186+ instruction } + IF_286, { 286+ instruction } + IF_386, { 386+ instruction } + IF_486, { 486+ instruction } + IF_PENT, { Pentium instruction } + IF_P6, { P6 instruction } + IF_KATMAI, { Katmai instructions } + IF_WILLAMETTE, { Willamette instructions } + IF_PRESCOTT, { Prescott instructions } + IF_X86_64, + IF_SANDYBRIDGE, { Sandybridge-specific instruction } + IF_NEC, { NEC V20/V30 instruction } + + { the following are not strictly part of the processor level, because + they are never used standalone, but always in combination with a + separate processor level flag. Therefore, they use bits outside of + IF_PLEVEL, otherwise they would mess up the processor level they're + used in combination with. + The following combinations are currently used: + [IF_AMD, IF_P6], + [IF_CYRIX, IF_486], + [IF_CYRIX, IF_PENT], + [IF_CYRIX, IF_P6] } + IF_CYRIX, { Cyrix, Centaur or VIA-specific instruction } + IF_AMD, { AMD-specific instruction } + + { added flags } + IF_PRE, { it's a prefix instruction } + IF_PASS2, { if the instruction can change in a second pass } + IF_IMM4, { immediate operand is a nibble (must be in range [0..15]) } + IF_IMM3, { immediate operand is a triad (must be in range [0..7]) } + + IF_BCST2, + IF_BCST4, + IF_BCST8, + IF_BCST16, + IF_T2, { disp8 - tuple - 2 } + IF_T4, { disp8 - tuple - 4 } + IF_T8, { disp8 - tuple - 8 } + IF_T1S, { disp8 - tuple - 1 scalar } + IF_T1S8, + IF_T1S16, + IF_T1F32, + IF_T1F64, + IF_TMDDUP, + IF_TFV, { disp8 - tuple - full vector } + IF_TFVM, { disp8 - tuple - full vector memory } + IF_TQVM, + IF_TMEM128, + IF_THV, + IF_THVM, + IF_TOVM, + + IF_SCL32, + IF_SCL64 + + + ); + tinsflags=set of tinsflag; + + + tinsentry=packed record + opcode : tasmop; + ops : byte; + //optypes : array[0..max_operands-1] of longint; + optypes : array[0..3] of int64; //TG + code : array[0..11] of char; + flags : tinsflags; + end; + pinsentry=^tinsentry; + +const + OT_NONE = $00000000; + + { Bits 0..7: sizes } + OT_BITS8 = $00000001; + OT_BITS16 = $00000002; + OT_BITS32 = $00000004; + OT_BITS64 = $00000008; { x86_64 and FPU } + //OT_BITS128 = $10000000; { 16 byte SSE } + //OT_BITS256 = $20000000; { 32 byte AVX } + //OT_BITS512 = $40000000; { 64 byte AVX512 } + OT_BITS128 = $20000000; { 16 byte SSE } + OT_BITS256 = $40000000; { 32 byte AVX } + OT_BITS512 = $80000000; { 64 byte AVX512 } + + OT_VECTORMASK = $1000000000; { OPTIONAL VECTORMASK AVX512} + OT_VECTORZERO = $2000000000; { OPTIONAL ZERO-FLAG AVX512} + OT_VECTORBCST = $4000000000; { BROADCAST-MEM-FLAG AVX512} + OT_VECTORSAE = $8000000000; { OPTIONAL SAE-FLAG AVX512} + OT_VECTORER = $10000000000; { OPTIONAL ER-FLAG-FLAG AVX512} + + + OT_BITSB32 = OT_BITS32 or OT_VECTORBCST; + OT_BITSB64 = OT_BITS64 or OT_VECTORBCST; + + + OT_VECTOR_EXT_MASK = OT_VECTORMASK or OT_VECTORZERO or OT_VECTORBCST; + + OT_BITS80 = $00000010; { FPU only } + OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP } + OT_NEAR = $00000040; + OT_SHORT = $00000080; + + { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask, + but this requires adjusting the opcode table } + //OT_SIZE_MASK = $3000001F; { all the size attributes } + OT_SIZE_MASK = $E000001F; { all the size attributes } + OT_NON_SIZE = int64(not int64(OT_SIZE_MASK)); + + { Bits 8..11: modifiers } + OT_SIGNED = $00000100; { the operand need to be signed -128-127 } + OT_TO = $00000200; { reverse effect in FADD, FSUB &c } + OT_COLON = $00000400; { operand is followed by a colon } + OT_MODIFIER_MASK = $00000F00; + + { Bits 12..15: type of operand } + OT_REGISTER = $00001000; + OT_IMMEDIATE = $00002000; + OT_MEMORY = $0000C000; { always includes 'OT_REGMEM' bit as well } + OT_REGMEM = $00008000; { for r/m, ie EA, operands } + OT_TYPE_MASK = OT_REGISTER or OT_IMMEDIATE or OT_MEMORY or OT_REGMEM; + + OT_REGNORM = OT_REGISTER or OT_REGMEM; { 'normal' reg, qualifies as EA } + + { Bits 20..22, 24..26: register classes + otf_* consts are not used alone, only to build other constants. } + otf_reg_cdt = $00100000; + otf_reg_gpr = $00200000; + otf_reg_sreg = $00400000; + otf_reg_k = $00800000; + otf_reg_fpu = $01000000; + otf_reg_mmx = $02000000; + otf_reg_xmm = $04000000; + otf_reg_ymm = $08000000; + otf_reg_zmm = $10000000; + + + otf_reg_extra_mask = $0F000000; + { Bits 16..19: subclasses, meaning depends on classes field } + otf_sub0 = $00010000; + otf_sub1 = $00020000; + otf_sub2 = $00040000; + otf_sub3 = $00080000; + OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3; + + //OT_REG_EXTRA_MASK = $0F000000; + OT_REG_EXTRA_MASK = $1F000000; + + OT_REG_TYPMASK = otf_reg_cdt or otf_reg_gpr or otf_reg_sreg or otf_reg_k or otf_reg_extra_mask; + { register class 0: CRx, DRx and TRx } + OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS64; + OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn } + OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn } + OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn } + OT_REG_CR4 = OT_REG_CDT or otf_sub3; { CR4 (Pentium only) } + + { register class 1: general-purpose registers } + OT_REG_GPR = OT_REGNORM or otf_reg_gpr; + OT_RM_GPR = OT_REGMEM or otf_reg_gpr; + OT_REG8 = OT_REG_GPR or OT_BITS8; { 8-bit GPR } + OT_REG16 = OT_REG_GPR or OT_BITS16; + OT_REG32 = OT_REG_GPR or OT_BITS32; + OT_REG64 = OT_REG_GPR or OT_BITS64; + + { GPR subclass 0: accumulator: AL, AX, EAX or RAX } + OT_REG_ACCUM = OT_REG_GPR or otf_sub0; + OT_REG_AL = OT_REG_ACCUM or OT_BITS8; + OT_REG_AX = OT_REG_ACCUM or OT_BITS16; + OT_REG_EAX = OT_REG_ACCUM or OT_BITS32; + OT_REG_RAX = OT_REG_ACCUM or OT_BITS64; + { GPR subclass 1: counter: CL, CX, ECX or RCX } + OT_REG_COUNT = OT_REG_GPR or otf_sub1; + OT_REG_CL = OT_REG_COUNT or OT_BITS8; + OT_REG_CX = OT_REG_COUNT or OT_BITS16; + OT_REG_ECX = OT_REG_COUNT or OT_BITS32; + OT_REG_RCX = OT_REG_COUNT or OT_BITS64; + { GPR subclass 2: data register: DL, DX, EDX or RDX } + OT_REG_DX = OT_REG_GPR or otf_sub2 or OT_BITS16; + OT_REG_EDX = OT_REG_GPR or otf_sub2 or OT_BITS32; + + { register class 2: Segment registers } + OT_REG_SREG = OT_REGISTER or otf_reg_sreg or OT_BITS16; + OT_REG_CS = OT_REG_SREG or otf_sub0; { CS } + OT_REG_DESS = OT_REG_SREG or otf_sub1; { DS, ES, SS (non-CS 86 registers) } + OT_REG_FSGS = OT_REG_SREG or otf_sub2; { FS, GS (386 extended registers) } + + { register class 3: FPU registers } + OT_FPUREG = OT_REGISTER or otf_reg_fpu; + OT_FPU0 = OT_FPUREG or otf_sub0; { FPU stack register zero } + + { register class 4: MMX (both reg and r/m) } + OT_MMXREG = OT_REGNORM or otf_reg_mmx; + OT_MMXRM = OT_REGMEM or otf_reg_mmx; + + { register class 5: XMM (both reg and r/m) } + OT_XMMREG = OT_REGNORM or otf_reg_xmm; + OT_XMMRM = OT_REGMEM or otf_reg_xmm; + OT_XMEM32 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS32; + OT_XMEM32_M = OT_XMEM32 or OT_VECTORMASK; + OT_XMEM64 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS64; + OT_XMEM64_M = OT_XMEM64 or OT_VECTORMASK; + + OT_XMMREG_M = OT_XMMREG or OT_VECTORMASK; + OT_XMMREG_MZ = OT_XMMREG or OT_VECTORMASK or OT_VECTORZERO; + OT_XMMRM_MZ = OT_XMMRM or OT_VECTORMASK or OT_VECTORZERO; + OT_XMMREG_SAE = OT_XMMREG or OT_VECTORSAE; + OT_XMMRM_SAE = OT_XMMRM or OT_VECTORSAE; + OT_XMMREG_ER = OT_XMMREG or OT_VECTORER; + OT_XMMRM_ER = OT_XMMRM or OT_VECTORER; + + + + { register class 5: YMM (both reg and r/m) } + OT_YMMREG = OT_REGNORM or otf_reg_ymm; + OT_YMMRM = OT_REGMEM or otf_reg_ymm; + OT_YMEM32 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS32; + OT_YMEM32_M = OT_YMEM32 or OT_VECTORMASK; + OT_YMEM64 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS64; + OT_YMEM64_M = OT_YMEM64 or OT_VECTORMASK; + + OT_YMMREG_M = OT_YMMREG or OT_VECTORMASK; + OT_YMMREG_MZ = OT_YMMREG or OT_VECTORMASK or OT_VECTORZERO; + OT_YMMRM_MZ = OT_YMMRM or OT_VECTORMASK or OT_VECTORZERO; + OT_YMMREG_SAE = OT_YMMREG or OT_VECTORSAE; + OT_YMMRM_SAE = OT_YMMRM or OT_VECTORSAE; + OT_YMMREG_ER = OT_YMMREG or OT_VECTORER; + OT_YMMRM_ER = OT_YMMRM or OT_VECTORER; + + + { register class 5: ZMM (both reg and r/m) } + OT_ZMMREG = OT_REGNORM or otf_reg_zmm; + OT_ZMMRM = OT_REGMEM or otf_reg_zmm; + OT_ZMEM32 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS32; + OT_ZMEM32_M = OT_ZMEM32 or OT_VECTORMASK; + OT_ZMEM64 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS64; + OT_ZMEM64_M = OT_ZMEM64 or OT_VECTORMASK; + + OT_ZMMREG_M = OT_ZMMREG or OT_VECTORMASK; + OT_ZMMREG_MZ = OT_ZMMREG or OT_VECTORMASK or OT_VECTORZERO; + OT_ZMMRM_MZ = OT_ZMMRM or OT_VECTORMASK or OT_VECTORZERO; + OT_ZMMREG_SAE = OT_ZMMREG or OT_VECTORSAE; + OT_ZMMRM_SAE = OT_ZMMRM or OT_VECTORSAE; + OT_ZMMREG_ER = OT_ZMMREG or OT_VECTORER; + OT_ZMMRM_ER = OT_ZMMRM or OT_VECTORER; + + + OT_KREG = OT_REGNORM or otf_reg_k; + OT_KREG_M = OT_KREG or OT_VECTORMASK; + + { Vector-Memory operands } + OT_VMEM_ANY = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64 or OT_ZMEM32 or OT_ZMEM64; + + { Memory operands } + OT_MEM8 = OT_MEMORY or OT_BITS8; + OT_MEM16 = OT_MEMORY or OT_BITS16; + OT_MEM16_M = OT_MEM16 or OT_VECTORMASK; + OT_MEM32 = OT_MEMORY or OT_BITS32; + OT_MEM32_M = OT_MEMORY or OT_BITS32 or OT_VECTORMASK; + OT_BMEM32 = OT_MEMORY or OT_BITS32 or OT_VECTORBCST; + OT_BMEM32_SAE= OT_MEMORY or OT_BITS32 or OT_VECTORBCST or OT_VECTORSAE; + OT_MEM64 = OT_MEMORY or OT_BITS64; + OT_MEM64_M = OT_MEMORY or OT_BITS64 or OT_VECTORMASK; + OT_BMEM64 = OT_MEMORY or OT_BITS64 or OT_VECTORBCST; + OT_BMEM64_SAE= OT_MEMORY or OT_BITS64 or OT_VECTORBCST or OT_VECTORSAE; + OT_MEM128 = OT_MEMORY or OT_BITS128; + OT_MEM128_M = OT_MEMORY or OT_BITS128 or OT_VECTORMASK; + OT_MEM256 = OT_MEMORY or OT_BITS256; + OT_MEM256_M = OT_MEMORY or OT_BITS256 or OT_VECTORMASK; + OT_MEM512 = OT_MEMORY or OT_BITS512; + OT_MEM512_M = OT_MEMORY or OT_BITS512 or OT_VECTORMASK; + OT_MEM80 = OT_MEMORY or OT_BITS80; + + + + + OT_MEM_OFFS = OT_MEMORY or otf_sub0; { special type of EA } + { simple [address] offset } + + { Matches any type of r/m operand } + OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK; + + { Immediate operands } + OT_IMM8 = OT_IMMEDIATE or OT_BITS8; + OT_IMM16 = OT_IMMEDIATE or OT_BITS16; + OT_IMM32 = OT_IMMEDIATE or OT_BITS32; + OT_IMM64 = OT_IMMEDIATE or OT_BITS64; + + OT_ONENESS = otf_sub0; { special type of immediate operand } + OT_UNITY = OT_IMMEDIATE or OT_ONENESS; { for shift/rotate instructions } + + std_op2str:op2strtable={$i ../../../compiler/x86_64/x8664int.inc} + + InsTab:array[0..instabentries-1] of TInsEntry={$i ../../../compiler/x86_64/x8664tab.inc} + + procedure BuildInsTabCache; + var + i : longint; + begin + new(instabcache); + FillChar(instabcache^,sizeof(tinstabcache),$ff); + i:=0; + while (i= 0 then + begin + + + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 0; + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := false; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := []; + + insentry:=@instab[i]; + + RegMMXSizeMask := 0; + RegXMMSizeMask := 0; + RegYMMSizeMask := 0; + RegZMMSizeMask := 0; + + RegMMXConstSizeMask := 0; + RegXMMConstSizeMask := 0; + RegYMMConstSizeMask := 0; + RegZMMConstSizeMask := 0; + + RegBCSTSizeMask:= 0; + RegBCSTXMMSizeMask := 0; + RegBCSTYMMSizeMask := 0; + RegBCSTZMMSizeMask := 0; + ExistsMemRef := false; + + while (insentry^.opcode=AsmOp) do + begin + MRefInfo := msiUnknown; + + actRegSize := 0; + actRegCount := 0; + actRegTypes := 0; + NewRegSize := 0; + + actMemSize := 0; + actMemCount := 0; + actRegMemTypes := 0; + + actVMemCount := 0; + actVMemTypes := 0; + + actConstSize := 0; + actConstCount := 0; + + ExistsCode336 := false; // indicate fixed operand size 32 bit + ExistsCode337 := false; // indicate fixed operand size 64 bit + ExistsSSEAVXReg := false; + + // parse insentry^.code for &336 and &337 + // &336 (octal) = 222 (decimal) == fixed operand size 32 bit + // &337 (octal) = 223 (decimal) == fixed operand size 64 bit + for i := low(insentry^.code) to high(insentry^.code) do + begin + case insentry^.code[i] of + #222: ExistsCode336 := true; + #223: ExistsCode337 := true; + #0,#1,#2,#3: break; + end; + end; + + for i := 0 to insentry^.ops -1 do + begin + if (insentry^.optypes[i] and OT_REGISTER) = OT_REGISTER then + case insentry^.optypes[i] and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of + OT_XMMREG, + OT_YMMREG, + OT_ZMMREG: ExistsSSEAVXReg := true; + else; + end; + end; + + + for j := 0 to insentry^.ops -1 do + begin + if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR + ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR + ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR + ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) OR + ((insentry^.optypes[j] and OT_ZMEM32) = OT_ZMEM32) OR + ((insentry^.optypes[j] and OT_ZMEM64) = OT_ZMEM64) then + begin + inc(actVMemCount); + + case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64 OR OT_ZMEM32 OR OT_ZMEM64) of + OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32; + OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64; + OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32; + OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64; + OT_ZMEM32: actVMemTypes := actVMemTypes or OT_ZMEM32; + OT_ZMEM64: actVMemTypes := actVMemTypes or OT_ZMEM64; + else; + end; + end + else if (insentry^.optypes[j] and OT_REGISTER) = OT_REGISTER then + begin + inc(actRegCount); + + NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK); + if NewRegSize = 0 then + begin + case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of + OT_MMXREG: begin + NewRegSize := OT_BITS64; + end; + OT_XMMREG: begin + NewRegSize := OT_BITS128; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_YMMREG: begin + NewRegSize := OT_BITS256; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_ZMMREG: begin + NewRegSize := OT_BITS512; + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + OT_KREG: begin + InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true; + end; + + else NewRegSize := not(0); + end; + end; + + actRegSize := actRegSize or NewRegSize; + actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK)); + end + else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then + begin + inc(actMemCount); + + + if ExistsSSEAVXReg and ExistsCode336 then + actMemSize := actMemSize or OT_BITS32 + else if ExistsSSEAVXReg and ExistsCode337 then + actMemSize := actMemSize or OT_BITS64 + else + actMemSize:=actMemSize or (insentry^.optypes[j] and (OT_SIZE_MASK OR OT_VECTORBCST)); + + if (insentry^.optypes[j] and OT_REGMEM) = OT_REGMEM then + begin + actRegMemTypes := actRegMemTypes or insentry^.optypes[j]; + end; + end + else if ((insentry^.optypes[j] and OT_IMMEDIATE) = OT_IMMEDIATE) then + begin + inc(actConstCount); + + actConstSize := actConstSize or (insentry^.optypes[j] and OT_SIZE_MASK); + end + end; + + if actConstCount > 0 then + begin + case actConstSize of + 0: SConstInfo := csiNoSize; + OT_BITS8: SConstInfo := csiMem8; + OT_BITS16: SConstInfo := csiMem16; + OT_BITS32: SConstInfo := csiMem32; + OT_BITS64: SConstInfo := csiMem64; + else SConstInfo := csiMultiple; + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize = csiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := SConstInfo; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize <> SConstInfo then + begin + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiMultiple; + end; + end; + + if actVMemCount > 0 then + begin + if actVMemCount = 1 then + begin + if actVMemTypes > 0 then + begin + case actVMemTypes of + OT_XMEM32: MRefInfo := msiXMem32; + OT_XMEM64: MRefInfo := msiXMem64; + OT_YMEM32: MRefInfo := msiYMem32; + OT_YMEM64: MRefInfo := msiYMem64; + OT_ZMEM32: MRefInfo := msiZMem32; + OT_ZMEM64: MRefInfo := msiZMem64; + else; + end; + + case actRegTypes of + OT_XMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS512; + else; + end; + OT_YMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS512; + else; + end; + OT_ZMMREG: case MRefInfo of + msiXMem32, + msiXMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS128; + msiYMem32, + msiYMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS256; + msiZMem32, + msiZMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS512; + else; + end; + + //else InternalError(777209); + end; + + + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64] then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple; + end + else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> msiVMemMultiple then; + end; + + end; + end + else; + end + else + begin + if (actMemCount=2) and ((AsmOp=A_MOVS) or (AsmOp=A_CMPS)) then actMemCount:=1; + + ExistsMemRef := ExistsMemRef or (actMemCount > 0); + + case actMemCount of + 0: ; // nothing todo + 1: begin + MRefInfo := msiUnknown; + + if not(ExistsCode336 or ExistsCode337) then + case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of + OT_MMXRM: actMemSize := actMemSize or OT_BITS64; + OT_XMMRM: actMemSize := actMemSize or OT_BITS128; + OT_YMMRM: actMemSize := actMemSize or OT_BITS256; + OT_ZMMRM: actMemSize := actMemSize or OT_BITS512; + end; + + case actMemSize of + 0: MRefInfo := msiNoSize; + OT_BITS8: MRefInfo := msiMem8; + OT_BITS16: MRefInfo := msiMem16; + OT_BITS32: MRefInfo := msiMem32; + OT_BITSB32: MRefInfo := msiBMem32; + OT_BITS64: MRefInfo := msiMem64; + OT_BITSB64: MRefInfo := msiBMem64; + OT_BITS128: MRefInfo := msiMem128; + OT_BITS256: MRefInfo := msiMem256; + OT_BITS512: MRefInfo := msiMem512; + OT_BITS80, + OT_FAR, + OT_NEAR, + OT_SHORT: ; // ignore + else + begin + bitcount := bitcnt(actMemSize); + + if bitcount > 1 then MRefInfo := msiMultiple + else; + end; + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo; + end + else + begin + // ignore broadcast-memory + if not(MRefInfo in [msiBMem32, msiBMem64]) then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then + begin + with InsTabMemRefSizeInfoCache^[AsmOp] do + begin + if ((MemRefSize in [msiMem8, msiMULTIPLEMinSize8]) OR (MRefInfo = msiMem8)) then MemRefSize := msiMultipleMinSize8 + else if ((MemRefSize in [ msiMem16, msiMULTIPLEMinSize16]) OR (MRefInfo = msiMem16)) then MemRefSize := msiMultipleMinSize16 + else if ((MemRefSize in [ msiMem32, msiMULTIPLEMinSize32]) OR (MRefInfo = msiMem32)) then MemRefSize := msiMultipleMinSize32 + else if ((MemRefSize in [ msiMem64, msiMULTIPLEMinSize64]) OR (MRefInfo = msiMem64)) then MemRefSize := msiMultipleMinSize64 + else if ((MemRefSize in [msiMem128, msiMULTIPLEMinSize128]) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultipleMinSize128 + else if ((MemRefSize in [msiMem256, msiMULTIPLEMinSize256]) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultipleMinSize256 + else if ((MemRefSize in [msiMem512, msiMULTIPLEMinSize512]) OR (MRefInfo = msiMem512)) then MemRefSize := msiMultipleMinSize512 + else MemRefSize := msiMultiple; + end; + end; + end; + end; + + //if not(MRefInfo in [msiBMem32, msiBMem64]) and (actRegCount > 0) then + if actRegCount > 0 then + begin + if MRefInfo in [msiBMem32, msiBMem64] then + begin + if IF_BCST2 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to2]; + if IF_BCST4 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to4]; + if IF_BCST8 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to8]; + if IF_BCST16 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to16]; + + //InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + + // BROADCAST - OPERAND + RegBCSTSizeMask := RegBCSTSizeMask or actMemSize; + + case actRegTypes and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of + OT_XMMREG: RegBCSTXMMSizeMask := RegBCSTXMMSizeMask or actMemSize; + OT_YMMREG: RegBCSTYMMSizeMask := RegBCSTYMMSizeMask or actMemSize; + OT_ZMMREG: RegBCSTZMMSizeMask := RegBCSTZMMSizeMask or actMemSize; + else begin + + RegBCSTXMMSizeMask := not(0); + RegBCSTYMMSizeMask := not(0); + RegBCSTZMMSizeMask := not(0); + end; + end; + end + else + case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of + OT_MMXREG: if actConstCount > 0 then RegMMXConstSizeMask := RegMMXConstSizeMask or actMemSize + else RegMMXSizeMask := RegMMXSizeMask or actMemSize; + OT_XMMREG: if actConstCount > 0 then RegXMMConstSizeMask := RegXMMConstSizeMask or actMemSize + else RegXMMSizeMask := RegXMMSizeMask or actMemSize; + OT_YMMREG: if actConstCount > 0 then RegYMMConstSizeMask := RegYMMConstSizeMask or actMemSize + else RegYMMSizeMask := RegYMMSizeMask or actMemSize; + OT_ZMMREG: if actConstCount > 0 then RegZMMConstSizeMask := RegZMMConstSizeMask or actMemSize + else RegZMMSizeMask := RegZMMSizeMask or actMemSize; + else begin + RegMMXSizeMask := not(0); + RegXMMSizeMask := not(0); + RegYMMSizeMask := not(0); + RegZMMSizeMask := not(0); + + RegMMXConstSizeMask := not(0); + RegXMMConstSizeMask := not(0); + RegYMMConstSizeMask := not(0); + RegZMMConstSizeMask := not(0); + end; + end; + end + else + + + end + else; + end; + end; + + inc(insentry); + end; + + if InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX then + begin + case RegBCSTSizeMask of + 0: ; // ignore; + OT_BITSB32: begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST32; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 4; + end; + OT_BITSB64: begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST64; + InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 2; + end; + else begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbMultiple; + end; + end; + end; + + + if (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples) and + (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX)then + begin + if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiVMemMultiple then + begin + if ((RegXMMSizeMask = OT_BITS128) or (RegXMMSizeMask = 0)) and + ((RegYMMSizeMask = OT_BITS256) or (RegYMMSizeMask = 0)) and + ((RegZMMSizeMask = OT_BITS512) or (RegZMMSizeMask = 0)) and + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) <> 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemRegSize; + end; + end + else if (RegMMXSizeMask or RegMMXConstSizeMask) <> 0 then + begin + if ((RegMMXSizeMask or RegMMXConstSizeMask) = OT_BITS64) and + ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = 0) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; + end; + end + else if (((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) or ((RegXMMSizeMask or RegXMMConstSizeMask) = 0)) and + (((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) or ((RegYMMSizeMask or RegYMMConstSizeMask) = 0)) and + (((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) or ((RegZMMSizeMask or RegZMMConstSizeMask) = 0)) and + (((RegXMMSizeMask or RegXMMConstSizeMask or + RegYMMSizeMask or RegYMMConstSizeMask or + RegZMMSizeMask or RegZMMConstSizeMask)) <> 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize; + end + else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and + (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and + (RegZMMSizeMask or RegZMMConstSizeMask = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32; + end + else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and + (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and + (RegZMMSizeMask or RegZMMConstSizeMask = OT_BITS64) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32z64; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS32) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS64) then + begin + if ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64; + end + else if ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS128) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64z128; + end; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS256) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128z256; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256; + end + else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and + ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and + ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256z512; + end + else if ((RegXMMConstSizeMask = 0) or (RegXMMConstSizeMask = OT_BITS128)) and + ((RegYMMConstSizeMask = 0) or (RegYMMConstSizeMask = OT_BITS256)) and + ((RegZMMConstSizeMask = 0) or (RegZMMConstSizeMask = OT_BITS512)) and + ((RegXMMConstSizeMask or RegYMMConstSizeMask or RegZMMConstSizeMask) <> 0) and + ( + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS128) or + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS256) or + ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS512) + ) then + begin + case RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask of + OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst128; + OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst256; + OT_BITS512: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst512; + else InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMultiple; + end; + end + else + begin + if not( + (AsmOp = A_CVTSI2SS) or + (AsmOp = A_CVTSI2SD) or + (AsmOp = A_CVTPD2DQ) or + (AsmOp = A_VCVTPD2DQ) or + (AsmOp = A_VCVTPD2PS) or + (AsmOp = A_VCVTSI2SD) or + (AsmOp = A_VCVTSI2SS) or + (AsmOp = A_VCVTTPD2DQ) or + (AsmOp = A_VCVTPD2UDQ) or + (AsmOp = A_VCVTQQ2PS) or + (AsmOp = A_VCVTTPD2UDQ) or + (AsmOp = A_VCVTUQQ2PS) or + (AsmOp = A_VCVTUSI2SD) or + (AsmOp = A_VCVTUSI2SS) or + + + // TODO check + (AsmOp = A_VCMPSS) + + + ) then; + + end; + + end + else if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and + (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown) and + (not(ExistsMemRef)) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiNoMemRef; + end; + + InsTabMemRefSizeInfoCache^[AsmOp].RegXMMSizeMask:=RegXMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask; + InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask; + + end; + end; + + for AsmOp := low(TAsmOp) to high(TAsmOp) do + begin + + + // only supported intructiones with SSE- or AVX-operands + if not(InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) then + begin + InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown; + InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown; + end; + end; + end; + +{ TOperandListItem } + +constructor TOperandListItem.Create; +begin + inherited; + + FOpActive := false; + FOpNumber := -1; + FOpTyp := otUnknown; + FValues := TStringList.Create; +end; + +destructor TOperandListItem.Destroy; +begin + FreeAndNil(FValues); + inherited; +end; + +{ TOperandList } + +function TOperandList.Add(aItem: TOperandListItem): integer; +begin + result := FList.Add(aItem); +end; + +function TOperandList.GetItems(aIndex: integer): TOperandListItem; +begin + result := TOperandListItem(FList[aIndex]); +end; + +{ TAsmTestGenerator } + +function TAsmTestGenerator.InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, + aOp4: String): TStringList; +var + i: integer; + Item: TOperandListItem; + OItem1: TOperandListItem; + OItem2: TOperandListItem; + OItem3: TOperandListItem; + OItem4: TOperandListItem; + + il_Op: integer; + il_Op1: integer; + il_Op2: integer; + il_Op3: integer; + il_Op4: integer; + + sSuffix: string; + sl_Operand: String; + sl_Inst : String; + sl_RegCombi: String; + sl_Prefix: String; + UsePrefix: boolean; + il_Operands: integer; + UsedParams: cardinal; + UseDefault: boolean; + sl_RegCombi1: string; + sl_RegCombi2: string; + sl_RegCombi3: string; + MaskRegNeeded:boolean; + + + function PrepareOperandTyp(const aTyp: String): String; + begin + result := aTyp; + if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); + if result = 'XMMRM128' then result := 'XMMRM'; + if result = 'YMMRM256' then result := 'YMMRM'; + end; + + +begin + result := TStringList.Create; + + OItem1 := TOperandListItem.Create; + try + OItem2 := TOperandListItem.Create; + try + OItem3 := TOperandListItem.Create; + try + OItem4 := TOperandListItem.Create; + try + + UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR + (UpperCase(aInst) = 'VCVTPD2PS') OR + (UpperCase(aInst) = 'VCVTSI2SD') OR + (UpperCase(aInst) = 'VCVTSI2SS') OR + (UpperCase(aInst) = 'VCVTTPD2DQ') or + (UpperCase(aInst) = 'VPMOVZXWQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTTPD2UDQ') or + (UpperCase(aInst) = 'VCVTUQQ2PS') or + (UpperCase(aInst) = 'VCVTQQ2PS') or + (UpperCase(aInst) = 'VCVTUSI2SD') or + (UpperCase(aInst) = 'VCVTUSI2SS') or + (UpperCase(aInst) = 'VFPCLASSPD') or + (UpperCase(aInst) = 'VFPCLASSPS') or + (UpperCase(aInst) = 'VCMPSS') + + ; + + + MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or + (Pos('VPGATHER', Uppercase(aInst)) = 1) or + (Pos('VPSCATTER', Uppercase(aInst)) = 1) or + (Pos('VSCATTER', Uppercase(aInst)) = 1); + + for il_Op := 1 to 4 do + begin + sl_Prefix := ''; + + case il_Op of + 1: begin + Item := OItem1; + sl_Operand := aOp1; + end; + 2: begin + Item := OItem2; + sl_Operand := aOp2; + end; + 3: begin + Item := OItem3; + sl_Operand := aOp3; + end; + 4: begin + Item := OItem4; + sl_Operand := aOp4; + end; + end; + + sl_Operand := PrepareOperandTyp(sl_Operand); + + if (AnsiSameText(sl_Operand, 'XMMREG')) or + (AnsiSameText(sl_Operand, 'XMMREG_M')) or + (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'XMMREG_ER')) or + (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM1' + sSuffix); + Item.Values.Add('XMM2' + sSuffix); + Item.Values.Add('XMM3' + sSuffix); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM5' + sSuffix); + Item.Values.Add('XMM6' + sSuffix); + Item.Values.Add('XMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM9' + sSuffix); + Item.Values.Add('XMM18' + sSuffix); + Item.Values.Add('XMM27' + sSuffix); + Item.Values.Add('XMM31' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('XMM0'); + Item.Values.Add('XMM9'); + Item.Values.Add('XMM18'); + Item.Values.Add('XMM27'); + Item.Values.Add('XMM31'); + end; + end + else + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM8' + sSuffix); + Item.Values.Add('XMM12' + sSuffix); + Item.Values.Add('XMM15' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('XMM0'); + Item.Values.Add('XMM4'); + Item.Values.Add('XMM8'); + Item.Values.Add('XMM12'); + Item.Values.Add('XMM15'); + end; + end; + end; + end + else if (AnsiSameText(sl_Operand, 'XMMRM')) or + (AnsiSameText(sl_Operand, 'XMMRM_M')) or + (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM1' + sSuffix); + Item.Values.Add('XMM2' + sSuffix); + Item.Values.Add('XMM3' + sSuffix); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM5' + sSuffix); + Item.Values.Add('XMM6' + sSuffix); + Item.Values.Add('XMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM9' + sSuffix); + Item.Values.Add('XMM9'); + Item.Values.Add('XMM18' + sSuffix); + Item.Values.Add('XMM18'); + Item.Values.Add('XMM27' + sSuffix); + Item.Values.Add('XMM27'); + Item.Values.Add('XMM31' + sSuffix); + Item.Values.Add('XMM31'); + end + else + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM4'); + Item.Values.Add('XMM8' + sSuffix); + Item.Values.Add('XMM8'); + Item.Values.Add('XMM12' + sSuffix); + Item.Values.Add('XMM15'); + Item.Values.Add('XMM15' + sSuffix); + end; + + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end; + end + else if (AnsiSameText(sl_Operand, 'XMMRM8')) or + (AnsiSameText(sl_Operand, 'XMMRM8_M')) or + (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM1' + sSuffix); + Item.Values.Add('XMM2' + sSuffix); + Item.Values.Add('XMM3' + sSuffix); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM5' + sSuffix); + Item.Values.Add('XMM6' + sSuffix); + Item.Values.Add('XMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM9' + sSuffix); + Item.Values.Add('XMM9'); + Item.Values.Add('XMM18' + sSuffix); + Item.Values.Add('XMM18'); + Item.Values.Add('XMM27' + sSuffix); + Item.Values.Add('XMM27'); + Item.Values.Add('XMM31' + sSuffix); + Item.Values.Add('XMM31'); + end + else + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM4'); + Item.Values.Add('XMM8' + sSuffix); + Item.Values.Add('XMM8'); + Item.Values.Add('XMM12' + sSuffix); + Item.Values.Add('XMM12'); + Item.Values.Add('XMM15' + sSuffix); + Item.Values.Add('XMM15'); + end; + + //Item.Values.Add('[RIP]'); + //Item.Values.Add('[RIP + 16]'); + + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end; + end + else if (AnsiSameText(sl_Operand, 'XMMRM16')) or + (AnsiSameText(sl_Operand, 'XMMRM16_M')) or + (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM1' + sSuffix); + Item.Values.Add('XMM2' + sSuffix); + Item.Values.Add('XMM3' + sSuffix); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM5' + sSuffix); + Item.Values.Add('XMM6' + sSuffix); + Item.Values.Add('XMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM9' + sSuffix); + Item.Values.Add('XMM9'); + Item.Values.Add('XMM18' + sSuffix); + Item.Values.Add('XMM18'); + Item.Values.Add('XMM27' + sSuffix); + Item.Values.Add('XMM27'); + Item.Values.Add('XMM31' + sSuffix); + Item.Values.Add('XMM31'); + end + else + begin + Item.Values.Add('XMM0' + sSuffix); + Item.Values.Add('XMM0'); + Item.Values.Add('XMM4' + sSuffix); + Item.Values.Add('XMM4'); + Item.Values.Add('XMM8' + sSuffix); + Item.Values.Add('XMM8'); + Item.Values.Add('XMM12' + sSuffix); + Item.Values.Add('XMM12'); + Item.Values.Add('XMM15' + sSuffix); + Item.Values.Add('XMM15'); + end; + + //Item.Values.Add('[RIP]'); + //Item.Values.Add('[RIP + 16]'); + + MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else + begin + MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end; + end + else if (AnsiSameText(sl_Operand, 'YMMREG')) or + (AnsiSameText(sl_Operand, 'YMMREG_M')) or + (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'YMMREG_ER')) or + (AnsiSameText(sl_Operand, 'YMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM1' + sSuffix); + Item.Values.Add('YMM2' + sSuffix); + Item.Values.Add('YMM3' + sSuffix); + Item.Values.Add('YMM4' + sSuffix); + Item.Values.Add('YMM5' + sSuffix); + Item.Values.Add('YMM6' + sSuffix); + Item.Values.Add('YMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM9' + sSuffix); + Item.Values.Add('YMM18' + sSuffix); + Item.Values.Add('YMM27' + sSuffix); + Item.Values.Add('YMM31' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('YMM0'); + Item.Values.Add('YMM9'); + Item.Values.Add('YMM18'); + Item.Values.Add('YMM27'); + Item.Values.Add('YMM31'); + end; + end + else + begin + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM4' + sSuffix); + Item.Values.Add('YMM8' + sSuffix); + Item.Values.Add('YMM12' + sSuffix); + Item.Values.Add('YMM15' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('YMM0'); + Item.Values.Add('YMM4'); + Item.Values.Add('YMM8'); + Item.Values.Add('YMM12'); + Item.Values.Add('YMM15'); + end; + end; + end; + end + else if (AnsiSameText(sl_Operand, 'YMMRM')) or + (AnsiSameText(sl_Operand, 'YMMRM_M')) or + (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'YMMRM_ER')) or + (AnsiSameText(sl_Operand, 'YMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM1' + sSuffix); + Item.Values.Add('YMM2' + sSuffix); + Item.Values.Add('YMM3' + sSuffix); + Item.Values.Add('YMM4' + sSuffix); + Item.Values.Add('YMM5' + sSuffix); + Item.Values.Add('YMM6' + sSuffix); + Item.Values.Add('YMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM9' + sSuffix); + Item.Values.Add('YMM18' + sSuffix); + Item.Values.Add('YMM27' + sSuffix); + Item.Values.Add('YMM31' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('YMM0'); + Item.Values.Add('YMM9'); + Item.Values.Add('YMM18'); + Item.Values.Add('YMM27'); + Item.Values.Add('YMM31'); + end; + end + else + begin + Item.Values.Add('YMM0' + sSuffix); + Item.Values.Add('YMM4' + sSuffix); + Item.Values.Add('YMM8' + sSuffix); + Item.Values.Add('YMM12' + sSuffix); + Item.Values.Add('YMM15' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('YMM0'); + Item.Values.Add('YMM4'); + Item.Values.Add('YMM8'); + Item.Values.Add('YMM12'); + Item.Values.Add('YMM15'); + end; + end; + + MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end; + end + else if (AnsiSameText(sl_Operand, 'ZMMREG')) or + (AnsiSameText(sl_Operand, 'ZMMREG_M')) or + (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or + (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM1' + sSuffix); + Item.Values.Add('ZMM2' + sSuffix); + Item.Values.Add('ZMM3' + sSuffix); + Item.Values.Add('ZMM4' + sSuffix); + Item.Values.Add('ZMM5' + sSuffix); + Item.Values.Add('ZMM6' + sSuffix); + Item.Values.Add('ZMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM9' + sSuffix); + Item.Values.Add('ZMM18' + sSuffix); + Item.Values.Add('ZMM27' + sSuffix); + Item.Values.Add('ZMM31' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('ZMM0'); + Item.Values.Add('ZMM9'); + Item.Values.Add('ZMM18'); + Item.Values.Add('ZMM27'); + Item.Values.Add('ZMM31'); + end; + end + else + begin + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM4' + sSuffix); + Item.Values.Add('ZMM8' + sSuffix); + Item.Values.Add('ZMM12' + sSuffix); + Item.Values.Add('ZMM15' + sSuffix); + end; + end; + end + else if (AnsiSameText(sl_Operand, 'ZMMRM')) or + (AnsiSameText(sl_Operand, 'ZMMRM_M')) or + (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + sSuffix := ''; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM1' + sSuffix); + Item.Values.Add('ZMM2' + sSuffix); + Item.Values.Add('ZMM3' + sSuffix); + Item.Values.Add('ZMM4' + sSuffix); + Item.Values.Add('ZMM5' + sSuffix); + Item.Values.Add('ZMM6' + sSuffix); + Item.Values.Add('ZMM7' + sSuffix); + + if x64 then + begin + Item.Values.Clear; + if FAVX512 then + begin + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM9' + sSuffix); + Item.Values.Add('ZMM18' + sSuffix); + Item.Values.Add('ZMM27' + sSuffix); + Item.Values.Add('ZMM31' + sSuffix); + + if (sSuffix <> '') and + (MaskRegNeeded = false) then + begin + Item.Values.Add('ZMM0'); + Item.Values.Add('ZMM9'); + Item.Values.Add('ZMM18'); + Item.Values.Add('ZMM27'); + Item.Values.Add('ZMM31'); + end; + end + else + begin + Item.Values.Add('ZMM0' + sSuffix); + Item.Values.Add('ZMM4' + sSuffix); + Item.Values.Add('ZMM8' + sSuffix); + Item.Values.Add('ZMM12' + sSuffix); + Item.Values.Add('ZMM15' + sSuffix); + end; + + MemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end; + end + else if AnsiSameText(sl_Operand, 'MEM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM8; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'byte '; + + + sSuffix := ''; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM16') or + AnsiSameText(sl_Operand, 'MEM16_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM32') or + AnsiSameText(sl_Operand, 'MEM32_M') or + AnsiSameText(sl_Operand, 'MEM32_MZ') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'dword '; + + sSuffix := ''; + + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM64')) or + (AnsiSameText(sl_Operand, 'MEM64_M')) or + (AnsiSameText(sl_Operand, 'MEM64_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'qword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM128')) or + (AnsiSameText(sl_Operand, 'MEM128_M')) or + (AnsiSameText(sl_Operand, 'MEM128_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM128; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM256')) or + (AnsiSameText(sl_Operand, 'MEM256_M')) or + (AnsiSameText(sl_Operand, 'MEM256_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM256; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM512')) or + (AnsiSameText(sl_Operand, 'MEM512_M')) or + (AnsiSameText(sl_Operand, 'MEM512_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM512; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'REG8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG8; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg8); + end + else Item.Values.AddStrings(FReg8); + end + else if AnsiSameText(sl_Operand, 'REG16') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG16; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg16); + end + else Item.Values.AddStrings(FReg16); + end + else if AnsiSameText(sl_Operand, 'REG32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG32; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg32Base); + end + else Item.Values.AddStrings(FReg32Base); + end + else if AnsiSameText(sl_Operand, 'REG64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG64; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + end; + end + else if AnsiSameText(sl_Operand, 'RM32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + Item.Values.AddStrings(FReg32Base); + + if UsePrefix then sl_Prefix := 'dword '; + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'RM64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'qword '; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + MemRegBaseIndexCombi(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'IMM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otIMM8; + Item.OpActive := true; + + Item.Values.Add('0'); + end + else if AnsiSameText(sl_Operand, 'XMEM32') or + AnsiSameText(sl_Operand, 'XMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + end + else if AnsiSameText(sl_Operand, 'XMEM64') or + AnsiSameText(sl_Operand, 'XMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM64; + Item.OpActive := true; + + //if UsePrefix then sl_Prefix := 'oword '; + // + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM32') or + AnsiSameText(sl_Operand, 'YMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM64') or + AnsiSameText(sl_Operand, 'YMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM32') or + AnsiSameText(sl_Operand, 'ZMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM64') or + AnsiSameText(sl_Operand, 'ZMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, '2B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '2B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombi(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombi(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'KREG') or + AnsiSameText(sl_Operand, 'KREG_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otKREG; + Item.OpActive := true; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if UsePrefix then sl_Prefix := ''; + + for i := 0 to FRegKREG.Count - 1 do + Item.Values.Add(FRegKREG[i] + sSuffix); + end + else if trim(sl_Operand) = '' then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add(''); + end + else + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add('?' + sl_Operand); + end + + end; + + sl_RegCombi := ''; + + + il_Operands := 0; + UsedParams := 0; + + if OItem1.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 1; + end; + + if OItem2.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 2; + end; + + if OItem3.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 4; + end; + + if OItem4.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 8; + end; + + case il_Operands of + 1: UseDefault := UsedParams <> 1; + 2: UseDefault := UsedParams <> 3; + 3: UseDefault := UsedParams <> 7; + 4: UseDefault := UsedParams <> 15; + else UseDefault := true; + end; + + //UseDefault := true; + + if UseDefault then + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sl_RegCombi := ''; + + if OItem1.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + end; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end + else + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + if OItem1.OpActive then + begin + sl_RegCombi1 := OItem1.Values[il_Op1]; + end + else sl_RegCombi1 := ''; + + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + if OItem2.OpActive then + begin + sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + end + else sl_RegCombi2 := sl_RegCombi1; + + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + if OItem3.OpActive then + begin + sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + end + else sl_RegCombi3 := sl_RegCombi2; + + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + if OItem4.OpActive then + begin + sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + end + else sl_RegCombi := sl_RegCombi3; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end; + finally + FreeAndNil(OItem4); + end; + finally + FreeAndNil(OItem3); + end; + finally + FreeAndNil(OItem2); + end; + finally + FreeAndNil(OItem1); + end; +end; + + +function TAsmTestGenerator.InternalCalcTestDataMREF(const aInst, aOp1, aOp2, aOp3, + aOp4: String): TStringList; +var + i: integer; + Item: TOperandListItem; + OItem1: TOperandListItem; + OItem2: TOperandListItem; + OItem3: TOperandListItem; + OItem4: TOperandListItem; + + il_Op: integer; + il_Op1: integer; + il_Op2: integer; + il_Op3: integer; + il_Op4: integer; + + sSuffix: string; + sl_Operand: String; + sl_Inst : String; + sl_RegCombi: String; + sl_Prefix: String; + UsePrefix: boolean; + il_Operands: integer; + UsedParams: cardinal; + UseDefault: boolean; + sl_RegCombi1: string; + sl_RegCombi2: string; + sl_RegCombi3: string; + + function PrepareOperandTyp(const aTyp: String): String; + begin + result := aTyp; + if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); + if result = 'XMMRM128' then result := 'XMMRM'; + if result = 'YMMRM256' then result := 'YMMRM'; + end; + + +begin + result := TStringList.Create; + + OItem1 := TOperandListItem.Create; + try + OItem2 := TOperandListItem.Create; + try + OItem3 := TOperandListItem.Create; + try + OItem4 := TOperandListItem.Create; + try + + UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR + (UpperCase(aInst) = 'VCVTPD2PS') OR + (UpperCase(aInst) = 'VCVTSI2SD') OR + (UpperCase(aInst) = 'VCVTSI2SS') OR + (UpperCase(aInst) = 'VCVTTPD2DQ') or + (UpperCase(aInst) = 'VPMOVZXWQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTTPD2UDQ') or + (UpperCase(aInst) = 'VCVTUQQ2PS') or + (UpperCase(aInst) = 'VCVTQQ2PS') or + (UpperCase(aInst) = 'VCVTUSI2SD') or + (UpperCase(aInst) = 'VCVTUSI2SS') or + (UpperCase(aInst) = 'VFPCLASSPD') or + (UpperCase(aInst) = 'VFPCLASSPS') or + (UpperCase(aInst) = 'VCMPSS') + + ; + + + + for il_Op := 1 to 4 do + begin + sl_Prefix := ''; + + case il_Op of + 1: begin + Item := OItem1; + sl_Operand := aOp1; + end; + 2: begin + Item := OItem2; + sl_Operand := aOp2; + end; + 3: begin + Item := OItem3; + sl_Operand := aOp3; + end; + 4: begin + Item := OItem4; + sl_Operand := aOp4; + end; + end; + + sl_Operand := PrepareOperandTyp(sl_Operand); + + if (AnsiSameText(sl_Operand, 'XMMREG')) or + (AnsiSameText(sl_Operand, 'XMMREG_M')) or + (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'XMMREG_ER')) or + (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + Item.Values.Add('XMM0'); + end + else if (AnsiSameText(sl_Operand, 'XMMRM')) or + (AnsiSameText(sl_Operand, 'XMMRM_M')) or + (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + Item.Values.Add(' lOWord'); + Item.Values.Add(' gOWord'); + Item.Values.Add(' clOWord'); + Item.Values.Add(' cgOWord'); + + Item.Values.Add(' oword lOWord'); + Item.Values.Add(' oword gOWord'); + Item.Values.Add(' oword clOWord'); + Item.Values.Add(' oword cgOWord'); + + Item.Values.Add(' byte lOWord'); + Item.Values.Add(' byte gOWord'); + Item.Values.Add(' byte clOWord'); + Item.Values.Add(' byte cgOWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' oword lRec'); + Item.Values.Add(' oword gRec'); + + Item.Values.Add(' oword lRec.rOWord'); + Item.Values.Add(' oword gRec.rOWord'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'XMMRM8')) or + (AnsiSameText(sl_Operand, 'XMMRM8_M')) or + (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + Item.Values.Add('lbyte'); + Item.Values.Add('gbyte'); + Item.Values.Add('clbyte'); + Item.Values.Add('cgbyte'); + + Item.Values.Add('byte lbyte'); + Item.Values.Add('byte gbyte'); + Item.Values.Add('byte clbyte'); + Item.Values.Add('byte cgbyte'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' byte lRec'); + Item.Values.Add(' byte gRec'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'XMMRM16')) or + (AnsiSameText(sl_Operand, 'XMMRM16_M')) or + (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM16; + Item.OpActive := true; + + Item.Values.Add('lword'); + Item.Values.Add('gword'); + Item.Values.Add('clword'); + Item.Values.Add('cgword'); + + Item.Values.Add('word lword'); + Item.Values.Add('word gword'); + Item.Values.Add('word clword'); + Item.Values.Add('word cgword'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' word lRec'); + Item.Values.Add(' word gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'YMMREG')) or + (AnsiSameText(sl_Operand, 'YMMREG_M')) or + (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'YMMREG_ER')) or + (AnsiSameText(sl_Operand, 'YMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + Item.Values.Add('YMM0'); + end + else if (AnsiSameText(sl_Operand, 'YMMRM')) or + (AnsiSameText(sl_Operand, 'YMMRM_M')) or + (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'YMMRM_ER')) or + (AnsiSameText(sl_Operand, 'YMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMRM; + Item.OpActive := true; + + Item.Values.Add('lYWord'); + Item.Values.Add('gYWord'); + Item.Values.Add('clYWord'); + Item.Values.Add('cgYWord'); + + Item.Values.Add('yword lYWord'); + Item.Values.Add('yword gYWord'); + Item.Values.Add('yword clYWord'); + Item.Values.Add('yword cgYWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' yword lRec'); + Item.Values.Add(' yword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'ZMMREG')) or + (AnsiSameText(sl_Operand, 'ZMMREG_M')) or + (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or + (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + Item.Values.Add('ZMM0'); + end + else if (AnsiSameText(sl_Operand, 'ZMMRM')) or + (AnsiSameText(sl_Operand, 'ZMMRM_M')) or + (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMRM; + Item.OpActive := true; + + Item.Values.Add('lZWord'); + Item.Values.Add('gZWord'); + Item.Values.Add('clZWord'); + Item.Values.Add('cgZWord'); + + Item.Values.Add('zword lZWord'); + Item.Values.Add('zword gZWord'); + Item.Values.Add('zword clZWord'); + Item.Values.Add('zword cgZWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' zword lRec'); + Item.Values.Add(' zword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if AnsiSameText(sl_Operand, 'MEM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM8; + Item.OpActive := true; + + Item.Values.Add('lByte'); + Item.Values.Add('gByte'); + Item.Values.Add('clByte'); + Item.Values.Add('cgByte'); + + Item.Values.Add('byte lByte'); + Item.Values.Add('byte gByte'); + Item.Values.Add('byte clByte'); + Item.Values.Add('byte cgByte'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' byte lRec'); + Item.Values.Add(' byte gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + end + else if AnsiSameText(sl_Operand, 'MEM16') or + AnsiSameText(sl_Operand, 'MEM16_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM16; + Item.OpActive := true; + + Item.Values.Add('lWord'); + Item.Values.Add('gWord'); + Item.Values.Add('clWord'); + Item.Values.Add('cgWord'); + + Item.Values.Add('word lWord'); + Item.Values.Add('word gWord'); + Item.Values.Add('word clWord'); + Item.Values.Add('word cgWord'); + + Item.Values.Add(' word lRec'); + Item.Values.Add(' word gRec'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + end + else if AnsiSameText(sl_Operand, 'MEM32') or + AnsiSameText(sl_Operand, 'MEM32_M') or + AnsiSameText(sl_Operand, 'MEM32_MZ') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM32; + Item.OpActive := true; + + Item.Values.Add('lDWord'); + Item.Values.Add('gDWord'); + Item.Values.Add('clDWord'); + Item.Values.Add('cgDWord'); + + Item.Values.Add('dword lDWord'); + Item.Values.Add('dword gDWord'); + Item.Values.Add('dword clDWord'); + Item.Values.Add('dword cgDWord'); + + Item.Values.Add(' dword lRec'); + Item.Values.Add(' dword gRec'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + end + else if (AnsiSameText(sl_Operand, 'MEM64')) or + (AnsiSameText(sl_Operand, 'MEM64_M')) or + (AnsiSameText(sl_Operand, 'MEM64_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM64; + Item.OpActive := true; + + Item.Values.Add('lQWord'); + Item.Values.Add('gQWord'); + Item.Values.Add('clQWord'); + Item.Values.Add('cgQWord'); + + Item.Values.Add('qword lQWord'); + Item.Values.Add('qword gQWord'); + Item.Values.Add('qword clQWord'); + Item.Values.Add('qword cgQWord'); + + Item.Values.Add(' qword lRec'); + Item.Values.Add(' qword gRec'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + end + else if (AnsiSameText(sl_Operand, 'MEM128')) or + (AnsiSameText(sl_Operand, 'MEM128_M')) or + (AnsiSameText(sl_Operand, 'MEM128_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM128; + Item.OpActive := true; + + Item.Values.Add('lOWord'); + Item.Values.Add('gOWord'); + Item.Values.Add('clOWord'); + Item.Values.Add('cgOWord'); + + Item.Values.Add('oword lOWord'); + Item.Values.Add('oword gOWord'); + Item.Values.Add('oword clOWord'); + Item.Values.Add('oword cgOWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' oword lRec'); + Item.Values.Add(' oword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'MEM256')) or + (AnsiSameText(sl_Operand, 'MEM256_M')) or + (AnsiSameText(sl_Operand, 'MEM256_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM256; + Item.OpActive := true; + + Item.Values.Add('lYWord'); + Item.Values.Add('gYWord'); + Item.Values.Add('clYWord'); + Item.Values.Add('cgYWord'); + + Item.Values.Add('yword lYWord'); + Item.Values.Add('yword gYWord'); + Item.Values.Add('yword clYWord'); + Item.Values.Add('yword cgYWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' yword lRec'); + Item.Values.Add(' yword gRec'); + + Item.Values.Add(' lRec.rByte'); + Item.Values.Add(' gRec.rByte'); + + Item.Values.Add(' lRec.rWord'); + Item.Values.Add(' gRec.rWord'); + + Item.Values.Add(' lRec.rDWord'); + Item.Values.Add(' gRec.rDWord'); + + Item.Values.Add(' lRec.rQWord'); + Item.Values.Add(' gRec.rQWord'); + + Item.Values.Add(' lRec.rOWord'); + Item.Values.Add(' gRec.rOWord'); + + Item.Values.Add(' lRec.rYWord'); + Item.Values.Add(' gRec.rYWord'); + + Item.Values.Add(' lRec.rZWord'); + Item.Values.Add(' gRec.rZWord'); + + end + else if (AnsiSameText(sl_Operand, 'MEM512')) or + (AnsiSameText(sl_Operand, 'MEM512_M')) or + (AnsiSameText(sl_Operand, 'MEM512_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM512; + Item.OpActive := true; + + Item.Values.Add('lZWord'); + Item.Values.Add('gZWord'); + Item.Values.Add('clZWord'); + Item.Values.Add('cgZWord'); + + Item.Values.Add('zword lZWord'); + Item.Values.Add('zword gZWord'); + Item.Values.Add('zword clZWord'); + Item.Values.Add('zword cgZWord'); + + Item.Values.Add(' lRec'); + Item.Values.Add(' gRec'); + + Item.Values.Add(' zword lRec'); + Item.Values.Add(' zword gRec'); + + + end + else if AnsiSameText(sl_Operand, 'REG8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG8; + Item.OpActive := true; + + Item.Values.Add('al'); + end + else if AnsiSameText(sl_Operand, 'REG16') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG16; + Item.OpActive := true; + + Item.Values.Add('ax'); + end + else if AnsiSameText(sl_Operand, 'REG32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG32; + Item.OpActive := true; + + Item.Values.Add('eax'); + end + else if AnsiSameText(sl_Operand, 'REG64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG64; + Item.OpActive := true; + + Item.Values.Add('rax'); + end + else if AnsiSameText(sl_Operand, 'RM32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + Item.Values.Add('lDWord'); + Item.Values.Add('gDWord'); + end + else if AnsiSameText(sl_Operand, 'RM64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM64; + Item.OpActive := true; + + Item.Values.Add('lQWord'); + Item.Values.Add('gQWord'); + end + else if AnsiSameText(sl_Operand, 'IMM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otIMM8; + Item.OpActive := true; + + Item.Values.Add('0'); + end + else if AnsiSameText(sl_Operand, 'XMEM32') or + AnsiSameText(sl_Operand, 'XMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM32; + Item.OpActive := true; + end + else if AnsiSameText(sl_Operand, 'XMEM64') or + AnsiSameText(sl_Operand, 'XMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM64; + Item.OpActive := true; + end + else if AnsiSameText(sl_Operand, 'YMEM32') or + AnsiSameText(sl_Operand, 'YMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM32; + Item.OpActive := true; + end + else if AnsiSameText(sl_Operand, 'YMEM64') or + AnsiSameText(sl_Operand, 'YMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + end + else if AnsiSameText(sl_Operand, 'ZMEM32') or + AnsiSameText(sl_Operand, 'ZMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + end + else if AnsiSameText(sl_Operand, 'ZMEM64') or + AnsiSameText(sl_Operand, 'ZMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + end + else if AnsiSameText(sl_Operand, '2B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('lDWord {1to2}'); + Item.Values.Add('gDWord {1to2}'); + end + else if AnsiSameText(sl_Operand, '4B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('lDWord {1to4}'); + Item.Values.Add('gDWord {1to4}'); + end + else if AnsiSameText(sl_Operand, '8B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('lDWord {1to8}'); + Item.Values.Add('gDWord {1to8}'); + end + else if AnsiSameText(sl_Operand, '16B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + Item.Values.Add('lDWord {1to16}'); + Item.Values.Add('gDWord {1to16}'); + end + else if AnsiSameText(sl_Operand, '2B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('lQWord {1to2}'); + Item.Values.Add('gQWord {1to2}'); + end + else if AnsiSameText(sl_Operand, '4B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('lQWord {1to4}'); + Item.Values.Add('gQWord {1to4}'); + end + else if AnsiSameText(sl_Operand, '8B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('lQWord {1to8}'); + Item.Values.Add('gQWord {1to8}'); + end + else if AnsiSameText(sl_Operand, '16B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + Item.Values.Add('lQWord {1to16}'); + Item.Values.Add('gQWord {1to16}'); + end + else if AnsiSameText(sl_Operand, 'KREG') or + AnsiSameText(sl_Operand, 'KREG_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otKREG; + Item.OpActive := true; + + Item.Values.Add('k1'); + end + else if trim(sl_Operand) = '' then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add(''); + end + else + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add('?' + sl_Operand); + end + + end; + + sl_RegCombi := ''; + + + il_Operands := 0; + UsedParams := 0; + + if OItem1.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 1; + end; + + if OItem2.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 2; + end; + + if OItem3.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 4; + end; + + if OItem4.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 8; + end; + + case il_Operands of + 1: UseDefault := UsedParams <> 1; + 2: UseDefault := UsedParams <> 3; + 3: UseDefault := UsedParams <> 7; + 4: UseDefault := UsedParams <> 15; + else UseDefault := true; + end; + + //UseDefault := true; + + if UseDefault then + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sl_RegCombi := ''; + + if OItem1.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + end; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end + else + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + if OItem1.OpActive then + begin + sl_RegCombi1 := OItem1.Values[il_Op1]; + end + else sl_RegCombi1 := ''; + + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + if OItem2.OpActive then + begin + sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + end + else sl_RegCombi2 := sl_RegCombi1; + + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + if OItem3.OpActive then + begin + sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + end + else sl_RegCombi3 := sl_RegCombi2; + + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + if OItem4.OpActive then + begin + sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + end + else sl_RegCombi := sl_RegCombi3; + + if sl_RegCombi <> '' then + begin + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(sl_Inst + sl_RegCombi); + sl_RegCombi := ''; + end; + end; + end; + end; + end; + end; + finally + FreeAndNil(OItem4); + end; + finally + FreeAndNil(OItem3); + end; + finally + FreeAndNil(OItem2); + end; + finally + FreeAndNil(OItem1); + end; +end; + +function TAsmTestGenerator.InternalCalcTestDataCDISP8(const aInst, aOp1, aOp2, + aOp3, aOp4: String): TStringList; +var + i: integer; + Item: TOperandListItem; + OItem1: TOperandListItem; + OItem2: TOperandListItem; + OItem3: TOperandListItem; + OItem4: TOperandListItem; + + il_Op: integer; + il_Op1: integer; + il_Op2: integer; + il_Op3: integer; + il_Op4: integer; + iAsmCounter: integer; + + sSuffix: string; + sReg: string; + sl_Operand: String; + sl_Inst : String; + sRegCombi: String; + sRegCombi1: String; + sRegCombi2: String; + sRegCombi3: String; + sRegCombi4: String; + sBaseReg : String; + sIndexReg : String; + + sl_Prefix: String; + UsePrefix: boolean; + il_Operands: integer; + UsedParams: cardinal; + UseDefault: boolean; + sl_RegCombi1: string; + sl_RegCombi2: string; + sl_RegCombi3: string; + sInstruction: string; + sMREF: string; + sLogMsg: string; + MaskRegNeeded:boolean; + slRegCombi: TStringList; + OpMode: TOpMode; + iOpNumMRef: integer; + + function PrepareOperandTyp(const aTyp: String): String; + begin + result := aTyp; + if copy(result, length(result), 1) = '*' then result := copy(result, 1, length(result) - 1); + if result = 'XMMRM128' then result := 'XMMRM'; + if result = 'YMMRM256' then result := 'YMMRM'; + end; + + procedure SplitOperands(const aOperand1, aOperand2, aOperand3, aOperand4: string; var aRegCombi0, aRegCombi1, aRegCombi2, aRegCombi3, aRegCombi4: string); + var + i: integer; + s1: string; + s2: string; + s3: string; + s4: string; + iCnt1: integer; + iCnt2: integer; + iCnt3: integer; + iCnt4: integer; + iMaxCnt: integer; + + begin + with TStringList.Create do + try + Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); + iCnt1 := Count; + + Text := StringReplace(trim(aOperand2), '|', #13#10, [rfReplaceAll]); + iCnt2 := Count; + + Text := StringReplace(trim(aOperand3), '|', #13#10, [rfReplaceAll]); + iCnt3 := Count; + + Text := StringReplace(trim(aOperand4), '|', #13#10, [rfReplaceAll]); + iCnt4 := Count; + + iMaxCnt := iCnt1; + if iCnt2 > iMaxCnt then iMaxCnt := iCnt2; + if iCnt3 > iMaxCnt then iMaxCnt := iCnt3; + if iCnt4 > iMaxCnt then iMaxCnt := iCnt4; + + + if (aOperand1 <> '') and (aRegCombi0 <> '') then + begin + aRegCombi0 := aRegCombi0 + ','; + aRegCombi1 := aRegCombi1 + ','; + aRegCombi2 := aRegCombi2 + ','; + aRegCombi3 := aRegCombi3 + ','; + aRegCombi4 := aRegCombi4 + ','; + end; + + + Text := StringReplace(trim(aOperand1), '|', #13#10, [rfReplaceAll]); + if Count = iMaxCnt then + begin + for i := 0 to iMaxCnt - 1 do + begin + case i of + 0: aRegCombi0 := aRegCombi0 + ',' + Strings[i]; + 1: aRegCombi1 := aRegCombi1 + ',' + Strings[i]; + 2: aRegCombi2 := aRegCombi2 + ',' + Strings[i]; + 3: aRegCombi3 := aRegCombi3 + ',' + Strings[i]; + 4: aRegCombi4 := aRegCombi4 + ',' + Strings[i]; + end; + end; + end + else + begin + if Count = 1 then + begin + for i := 0 to iMaxCnt - 1 do + begin + case i of + 0: aRegCombi0 := aRegCombi0 + ',' + Strings[0]; + 1: aRegCombi1 := aRegCombi1 + ',' + Strings[0]; + 2: aRegCombi2 := aRegCombi2 + ',' + Strings[0]; + 3: aRegCombi3 := aRegCombi3 + ',' + Strings[0]; + 4: aRegCombi4 := aRegCombi4 + ',' + Strings[0]; + end; + end; + end + else + begin + // TODO log + end; + end; + finally + Free; + end; + end; + + function MapOperand(aOpTyp: TOpType): String; + begin + case aOpTyp of + otXMMReg: result := 'X'; + otYMMReg: result := 'Y'; + otZMMReg: result := 'Z'; + otEAX, + otRAX, + otREG64, + otREG32, + otREG16, + otREG8: result := 'R'; + otRM32, + otRM64, + otXMMRM, + otXMMRM8, + otXMMRM16, + otYMMRM, + otZMMRM, + otMem32, + otMem8, + otMem16, + otMem64, + otMem128, + otMem256, + otMem512: result := 'M'; + otIMM8: result := 'I'; + otXMEM32: result := 'X32'; + otXMEM64: result := 'X64'; + otYMEM32: result := 'Y32'; + otYMEM64: result := 'Y64'; + otZMEM32: result := 'Z32'; + otZMEM64: result := 'Z64'; + otB32: result := 'B32'; + otB64: result := 'B64'; + otKREG: result := 'K'; + else result := ''; + end; + end; + + function AsmCodeBlockCompare(aAsmCounter: integer; aCompareMode: TAsmCompareMode): String; + var + sReg: string; + begin + result := ''; + + case Fx64 of + true: sReg := 'RAX'; + else sReg := 'EAX'; + end; + + with TStringList.Create do + try + Add(format('%20s%6s ', [' push', sReg])); + Add(format('%20s%6s,%s', [' mov', sReg, inttostr(aAsmCounter)])); + Add(format('%20s%6s,%s', [' kmovd', 'K7', 'EAX'])); + Add(format('%20s%6s', [' pop', sReg])); + + case aComparemode of + cmKORTESTNC: begin + Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); + Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); + end; + cmXORTestNZ: begin + Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); + Add(format('%20s %6s', [' jnz', '@@CHECKRESULT'])); + end; + end; + + result := Text; + finally + Free; + end; + end; + +begin + result := TStringList.Create; + + iAsmCounter := 0; + + OItem1 := TOperandListItem.Create; + try + OItem2 := TOperandListItem.Create; + try + OItem3 := TOperandListItem.Create; + try + OItem4 := TOperandListItem.Create; + try + + UsePrefix := (UpperCase(aInst) = 'VCVTPD2DQ') OR + (UpperCase(aInst) = 'VCVTPD2PS') OR + (UpperCase(aInst) = 'VCVTSI2SD') OR + (UpperCase(aInst) = 'VCVTSI2SS') OR + (UpperCase(aInst) = 'VCVTTPD2DQ') or + (UpperCase(aInst) = 'VPMOVZXWQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTPD2UDQ') or + (UpperCase(aInst) = 'VCVTTPD2UDQ') or + (UpperCase(aInst) = 'VCVTUQQ2PS') or + (UpperCase(aInst) = 'VCVTQQ2PS') or + (UpperCase(aInst) = 'VCVTUSI2SD') or + (UpperCase(aInst) = 'VCVTUSI2SS') or + (UpperCase(aInst) = 'VFPCLASSPD') or + (UpperCase(aInst) = 'VFPCLASSPS') or + (UpperCase(aInst) = 'VCMPSS') + + ; + + + MaskRegNeeded := (Pos('VGATHER', Uppercase(aInst)) = 1) or + (Pos('VPGATHER', Uppercase(aInst)) = 1) or + (Pos('VPSCATTER', Uppercase(aInst)) = 1) or + (Pos('VSCATTER', Uppercase(aInst)) = 1); + + for il_Op := 1 to 4 do + begin + sl_Prefix := ''; + + case il_Op of + 1: begin + Item := OItem1; + sl_Operand := aOp1; + end; + 2: begin + Item := OItem2; + sl_Operand := aOp2; + end; + 3: begin + Item := OItem3; + sl_Operand := aOp3; + end; + 4: begin + Item := OItem4; + sl_Operand := aOp4; + end; + end; + + sl_Operand := PrepareOperandTyp(sl_Operand); + + if (AnsiSameText(sl_Operand, 'XMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + Item.Values.Add('XMM16'); + end + else if (AnsiSameText(sl_Operand, 'XMMREG_M')) or + (AnsiSameText(sl_Operand, 'XMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'XMMREG_ER')) or + (AnsiSameText(sl_Operand, 'XMMREG_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMReg; + Item.OpActive := true; + + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', sl_Operand) > 0 then sSuffix := ', {ru-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + // + //Item.Values.Add('XMM0' + sSuffix); + //if (sSuffix <> '') and + // (MaskRegNeeded = false) then Item.Values.Add('XMM0'); + + Item.Values.Add('XMM16'); + end + else if (AnsiSameText(sl_Operand, 'XMMRM')) or + (AnsiSameText(sl_Operand, 'XMMRM_M')) or + (AnsiSameText(sl_Operand, 'XMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'XMMRM8')) or + (AnsiSameText(sl_Operand, 'XMMRM8_M')) or + (AnsiSameText(sl_Operand, 'XMMRM8_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM8_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM8_SAE')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM8; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'byte '; + + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'XMMRM16')) or + (AnsiSameText(sl_Operand, 'XMMRM16_M')) or + (AnsiSameText(sl_Operand, 'XMMRM16_MZ')) or + (AnsiSameText(sl_Operand, 'XMMRM16_ER')) or + (AnsiSameText(sl_Operand, 'XMMRM16_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMMRM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'YMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + Item.Values.Add('YMM16'); + end + else if (AnsiSameText(sl_Operand, 'YMMREG_M')) or + (AnsiSameText(sl_Operand, 'YMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'YMMREG_ER')) or + (AnsiSameText(sl_Operand, 'YMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMReg; + Item.OpActive := true; + + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + // + //Item.Values.Add('YMM0' + sSuffix); + //if (sSuffix <> '') and + // (MaskRegNeeded = false) then Item.Values.Add('YMM0'); + + Item.Values.Add('YMM16'); + end + else if (AnsiSameText(sl_Operand, 'YMMRM')) or + (AnsiSameText(sl_Operand, 'YMMRM_M')) or + (AnsiSameText(sl_Operand, 'YMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'YMMRM_ER')) or + (AnsiSameText(sl_Operand, 'YMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'ZMMREG')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + Item.Values.Add('ZMM16'); + end + else if (AnsiSameText(sl_Operand, 'ZMMREG_M')) or + (AnsiSameText(sl_Operand, 'ZMMREG_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMREG_ER')) or + (AnsiSameText(sl_Operand, 'ZMMREG_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMReg; + Item.OpActive := true; + + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + Item.Values.Add('ZMM16'); + end + else if (AnsiSameText(sl_Operand, 'ZMMRM')) or + (AnsiSameText(sl_Operand, 'ZMMRM_M')) or + (AnsiSameText(sl_Operand, 'ZMMRM_MZ')) or + (AnsiSameText(sl_Operand, 'ZMMRM_ER')) or + (AnsiSameText(sl_Operand, 'ZMMRM_SAE')) + then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMMRM; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //sSuffix := ''; + //if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}' + // else if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + // + //if Pos('_ER', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ', {rd-sae}' + // else if FSAE and (Pos('_SAE', AnsiUppercase(sl_Operand)) > 0) then sSuffix := ', {sae}'; + + if x64 then MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values) + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM8; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'byte '; + + + sSuffix := ''; + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM16') or + AnsiSameText(sl_Operand, 'MEM16_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM16; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'word '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'MEM32') or + AnsiSameText(sl_Operand, 'MEM32_M') or + AnsiSameText(sl_Operand, 'MEM32_MZ') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'dword '; + + sSuffix := ''; + + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM64')) or + (AnsiSameText(sl_Operand, 'MEM64_M')) or + (AnsiSameText(sl_Operand, 'MEM64_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'qword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM128')) or + (AnsiSameText(sl_Operand, 'MEM128_M')) or + (AnsiSameText(sl_Operand, 'MEM128_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM128; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM256')) or + (AnsiSameText(sl_Operand, 'MEM256_M')) or + (AnsiSameText(sl_Operand, 'MEM256_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM256; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if (AnsiSameText(sl_Operand, 'MEM512')) or + (AnsiSameText(sl_Operand, 'MEM512_M')) or + (AnsiSameText(sl_Operand, 'MEM512_MZ')) then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otMEM512; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + if Pos('_MZ', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1} {z}'; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, sSuffix, FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'REG8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG8; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg8); + end + else Item.Values.AddStrings(FReg8); + end + else if AnsiSameText(sl_Operand, 'REG16') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG16; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg16); + end + else Item.Values.AddStrings(FReg16); + end + else if AnsiSameText(sl_Operand, 'REG32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG32; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg32Base); + end + else Item.Values.AddStrings(FReg32Base); + end + else if AnsiSameText(sl_Operand, 'REG64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otREG64; + Item.OpActive := true; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + end; + end + else if AnsiSameText(sl_Operand, 'RM32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + Item.Values.AddStrings(FReg32Base); + + if UsePrefix then sl_Prefix := 'dword '; + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'RM64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otRM32; + Item.OpActive := true; + + + + if UsePrefix then sl_Prefix := 'qword '; + + if x64 then + begin + Item.Values.AddStrings(FReg64Base); + MemRegBaseIndexCombiCDISP8N(sl_Prefix, '', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, '', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'IMM8') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otIMM8; + Item.OpActive := true; + + Item.Values.Add('0'); + end + else if AnsiSameText(sl_Operand, 'XMEM32') or + AnsiSameText(sl_Operand, 'XMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'oword '; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + end + else if AnsiSameText(sl_Operand, 'XMEM64') or + AnsiSameText(sl_Operand, 'XMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otXMEM64; + Item.OpActive := true; + + //if UsePrefix then sl_Prefix := 'oword '; + // + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64XMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32XMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM32') or + AnsiSameText(sl_Operand, 'YMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'YMEM64') or + AnsiSameText(sl_Operand, 'YMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otYMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'yword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64YMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32YMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM32') or + AnsiSameText(sl_Operand, 'ZMEM32_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM32; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, 'ZMEM64') or + AnsiSameText(sl_Operand, 'ZMEM64_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otZMEM64; + Item.OpActive := true; + + if UsePrefix then sl_Prefix := 'zword '; + + //if x64 then + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values); + //end + //else + //begin + // VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values); + //end; + + sSuffix := ''; + if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}'; + + if x64 then + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg64Base, FReg64ZMMIndex, Item.Values); + end + else + begin + VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values); + if (sSuffix <> '') and + (MaskRegNeeded = false) + then + VectorMemRegBaseIndexCombi(sl_prefix, '', FReg32Base, FReg32ZMMIndex, Item.Values); + end; + + end + else if AnsiSameText(sl_Operand, '2B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B32') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB32; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '2B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to2}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to2}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '4B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to4}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to4}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '8B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to8}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to8}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, '16B64') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otB64; + Item.OpActive := true; + + + if x64 then + begin + MemRegBaseIndexCombiCDISP8N(sl_Prefix, ' {1to16}', FReg64Base, FReg64Index, Item.Values); + //MemRegBaseIndexCombi(FReg6432Base, FReg6432Index, Item.Values); + end + else MemRegBaseIndexCombiCDISP8N(sl_prefix, ' {1to16}', FReg32Base, FReg32Index, Item.Values); + end + else if AnsiSameText(sl_Operand, 'KREG') or + AnsiSameText(sl_Operand, 'KREG_M') then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otKREG; + Item.OpActive := true; + + Item.Values.Add('K1'); + end + else if trim(sl_Operand) = '' then + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add(''); + end + else + begin + Item.OpNumber := il_Op; + Item.OpTyp := otUnknown; + Item.OpActive := false; + + Item.Values.Add('?' + sl_Operand); + end + + end; + + //sl_RegCombi := ''; + + + il_Operands := 0; + UsedParams := 0; + + if OItem1.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 1; + end; + + if OItem2.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 2; + end; + + if OItem3.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 4; + end; + + if OItem4.OpActive then + begin + inc(il_Operands); + UsedParams := UsedParams or 8; + end; + + case il_Operands of + 1: UseDefault := UsedParams <> 1; + 2: UseDefault := UsedParams <> 3; + 3: UseDefault := UsedParams <> 7; + 4: UseDefault := UsedParams <> 15; + else UseDefault := true; + end; + + // TODO deaktivieren + //UseDefault := true; + + if UseDefault then + begin + sl_Inst := format('%-20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + slRegCombi := TStringList.Create; + try + while slRegCombi.Count < 5 do + slRegCombi.Add(''); + + + //SplitOperands(OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4] + if OItem1.OpActive then + begin + // SplitOperand(OItem1.Values[il_Op1], sRegCombi0,sRegCombi1,sRegCombi2,sRegCombi3,sRegCombi4); + // + end; + finally + FreeAndNil(slRegCombi); + end; + + //sRegCombi0 := ''; + //sRegCombi1 := ''; + //sRegCombi2 := ''; + //sRegCombi3 := ''; + //sRegCombi4 := ''; + // + //if OItem1.OpActive then + //begin + // if sRegCombi0 <> '' then + // begin + // sRegCombi0 := sRegCombi0 + ', '; + // sRegCombi1 := sRegCombi1 + ', '; + // sRegCombi2 := sRegCombi2 + ', '; + // sRegCombi3 := sRegCombi3 + ', '; + // sRegCombi4 := sRegCombi4 + ', '; + // end; + // + // if Pos('|', OItem1.Values[il_Op1]) > 0 then + // begin + // with TStringList.Create do + // try + // Text := Stringreplace(OItem1.Values[il_Op1], '|', #13#10,[rfReplaceAll]); + // iCnt := Count; + // while Count < 5 do Add(''); + // + // sRegCombi0 := sRegCombi0 + Strings[0]; + // sRegCombi1 := sRegCombi1 + Strings[1]; + // sRegCombi2 := sRegCombi2 + Strings[2]; + // sRegCombi3 := sRegCombi3 + Strings[3]; + // sRegCombi4 := sRegCombi4 + Strings[4]; + // + // finally + // Free; + // end; + // end + // else + // begin + // sRegCombi0 := sRegCombi0 + OItem1.Values[il_Op1]; + // sRegCombi1 := sRegCombi1 + OItem1.Values[il_Op1]; + // sRegCombi2 := sRegCombi2 + OItem1.Values[il_Op1]; + // sRegCombi3 := sRegCombi3 + OItem1.Values[il_Op1]; + // sRegCombi4 := sRegCombi4 + OItem1.Values[il_Op1]; + // end; + //end; + // + //if OItem2.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem2.Values[il_Op2]; + //end; + // + //if OItem3.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem3.Values[il_Op3]; + //end; + // + //if OItem4.OpActive then + //begin + // if sl_RegCombi <> '' then sl_RegCombi := sl_RegCombi + ', '; + // sl_RegCombi := sl_RegCombi + OItem4.Values[il_Op4]; + //end; + // + //if sl_RegCombi <> '' then + //begin + // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + // result.Add(sl_Inst + sl_RegCombi); + // sl_RegCombi := ''; + //end; + end; + end; + end; + end; + end + else + begin + OpMode := omUnknown; + + iOpNumMRef := -1; + if (OItem1.OpTyp in MEMTYPES) or + (OItem1.OpTyp in BMEMTYPES) then iOpNumMRef := 1 + else if (OItem2.OpTyp in MEMTYPES) or + (OItem2.OpTyp in BMEMTYPES) then iOpNumMRef := 2 + else if (OItem3.OpTyp in MEMTYPES) or + (OItem3.OpTyp in BMEMTYPES) then iOpNumMRef := 3 + else if (OItem4.OpTyp in MEMTYPES) or + (OItem4.OpTyp in BMEMTYPES) then iOpNumMRef := 4; + + + // TODO delete + //if il_Operands = 4 then + + case il_Operands of + 2: begin + if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otXMMReg) then OpMode := omMX + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otYMMReg) then OpMode := omMY + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otZMMReg) then OpMode := omMZ + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omXB32 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omXB64 + + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omYB32 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omYB64 + + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB32) then OpMode := omZB32 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB64) then OpMode := omZB64 + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omXM + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omYM + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp in MEMTYPES) then OpMode := omZM + + + + + else + begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + if sLogMsg <> '' then + begin + + if (sLogMsg <> 'KX') and + (sLogMsg <> 'KY') and + (sLogMsg <> 'KZ') and + (sLogMsg <> 'RM') and + (sLogMsg <> 'RX') and + (sLogMsg <> 'XK') and + (sLogMsg <> 'XR') and + (sLogMsg <> 'XX') and + (sLogMsg <> 'XY') and + (sLogMsg <> 'XZ') and + (sLogMsg <> 'YK') and + (sLogMsg <> 'YR') and + (sLogMsg <> 'YX') and + (sLogMsg <> 'YY') and + (sLogMsg <> 'YZ') and + (sLogMsg <> 'ZK') and + (sLogMsg <> 'ZR') and + (sLogMsg <> 'ZX') and + (sLogMsg <> 'ZY') and + (sLogMsg <> 'ZZ') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; + end; + 3: if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omKXM + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omKYM + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omKZM + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKXB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKXB64 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKYB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKYB64 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omKZB32 + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omKZB64 + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omKMI + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omKB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omKB64I + + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMXI + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMYI + else if (OItem1.OpTyp in MEMTYPES) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otIMM8) then OpMode := omMZI + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omXXM + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omXXB32 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omXXB64 + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omXB32I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omXB64I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omXMI + + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omYYM + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omYYB32 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omYYB64 + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omYB32I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omYB64I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omYMI + + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) then OpMode := omZZM + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) then OpMode := omZZB32 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) then OpMode := omZZB64 + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB32) and + (OItem3.OpTyp = otIMM8) then OpMode := omZB32I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otB64) and + (OItem3.OpTyp = otIMM8) then OpMode := omZB64I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp in MEMTYPES) and + (OItem3.OpTyp = otIMM8) then OpMode := omZMI + + + else + begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + if sLogMsg <> '' then + begin + if (sLogMsg <> 'RMI') and + (sLogMsg <> 'RRM') and + (sLogMsg <> 'RMR') and + (sLogMsg <> 'KKK') and + (sLogMsg <> 'KKI') and + (sLogMsg <> 'XXX') and + (sLogMsg <> 'YYY') and + (sLogMsg <> 'ZZZ') and + (sLogMsg <> 'XXI') and + (sLogMsg <> 'YYI') and + (sLogMsg <> 'ZZI') and + (sLogMsg <> 'XYI') and + (sLogMsg <> 'YZI') and + (sLogMsg <> 'XZI') and + (sLogMsg <> 'RXI') and + (sLogMsg <> 'RYI') and + (sLogMsg <> 'RZI') and + + + (sLogMsg <> 'XXR') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; + 4: if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKXMI + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKYMI + + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZB32I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZB64I + else if (OItem1.OpTyp = otKReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omKZMI + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXB32I + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXB64I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYB32I + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYB64I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB32) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZB32I + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp = otB64) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZB64I + + + else if (OItem1.OpTyp = otXMMReg) and + (OItem2.OpTyp = otXMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omXXMI + else if (OItem1.OpTyp = otYMMReg) and + (OItem2.OpTyp = otYMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omYYMI + else if (OItem1.OpTyp = otZMMReg) and + (OItem2.OpTyp = otZMMReg) and + (OItem3.OpTyp in MEMTYPES) and + (OItem4.OpTyp = otIMM8) then OpMode := omZZMI + else + begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp) + MapOperand(OItem4.Optyp); + if sLogMsg <> '' then + begin + + if (sLogMsg <> 'KXXI') and + (sLogMsg <> 'KYYI') and + (sLogMsg <> 'KZZI') and + (sLogMsg <> 'XXRI') and + (sLogMsg <> 'XXXI') and + (sLogMsg <> 'YYYI') and + (sLogMsg <> 'ZZZI') then + + writeln('offen : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; + + else; + end; + + if OpMode <> omUnknown then + begin + sInstruction := format('%20s', [aInst]); + + for il_Op1 := 0 to OItem1.Values.Count - 1 do + begin + for il_Op2 := 0 to OItem2.Values.Count - 1 do + begin + for il_Op3 := 0 to OItem3.Values.Count - 1 do + begin + for il_Op4 := 0 to OItem4.Values.Count - 1 do + begin + sRegCombi := ''; + + if OItem1.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem1.Values[il_Op1]; + end; + + if OItem2.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem2.Values[il_Op2]; + end; + + if OItem3.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem3.Values[il_Op3]; + end; + + if OItem4.OpActive then + begin + if sRegCombi <> '' then sRegCombi := sRegCombi + ', '; + sRegCombi := sRegCombi + OItem4.Values[il_Op4]; + end; + + if sRegCombi <> '' then + begin + case iOpNumMRef of + 1: sMRef := OItem1.Values[il_Op1]; + 2: sMRef := OItem2.Values[il_Op2]; + 3: sMRef := OItem3.Values[il_Op3]; + 4: sMRef := OItem1.Values[il_Op4]; + else sMRef := ''; + end; + + if ParseBaseIndexReg(sMRef, sBaseReg, sIndexReg) then + begin + result.Add(format('%20s %s', [' pop', sBaseReg])); + result.Add(format('%20s %s', [' push', sBaseReg])); + + if trim(sIndexReg) <> '' then + result.Add(format('%20s%6s, %s', [' xor', sIndexReg, sIndexReg])); + + if OpMode in [omMXI, omMYI, omMZI] then + begin + case Fx64 of + true: begin + result.Add(format('%20s %6s', ['push', 'RDI'])); + result.Add(format('%20s %6s', ['push', 'RCX'])); + result.Add(format('%20s %6s', ['push', 'RAX'])); + + result.Add(format('%20s %6s', ['push', sBaseReg])); + result.Add(format('%20s %6s', ['pop', 'RDI'])); + result.Add(format('%20s %6s', ['mov', 'RCX, sizeof(DataBlock)'])); + result.Add(format('%20s %6s, %s', ['xor', 'RAX', 'RAX'])); + result.Add(format('%20s ', ['rep stosb'])); + result.Add(format('%20s %6s', ['pop', 'RAX'])); + result.Add(format('%20s %6s', ['pop', 'RCX'])); + result.Add(format('%20s %6s', ['pop', 'RDI'])); + end; + else begin + result.Add(format('%20s %6s', ['push', 'EDI'])); + result.Add(format('%20s %6s', ['push', 'ECX'])); + result.Add(format('%20s %6s', ['push', 'EAX'])); + + result.Add(format('%20s %6s', ['push', sBaseReg])); + result.Add(format('%20s %6s', ['pop', 'EDI'])); + result.Add(format('%20s %6s', ['mov', 'ECX, sizeof(DataBlock)'])); + result.Add(format('%20s %6s, %s', ['xor', 'EAX', 'EAX'])); + result.Add(format('%20s ', ['rep stosb'])); + result.Add(format('%20s %6s', ['pop', 'EAX'])); + result.Add(format('%20s %6s', ['pop', 'ECX'])); + result.Add(format('%20s %6s', ['pop', 'EDI'])); + end; + end; + end; + + end; + + + //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + result.Add(format('%-20s %6s', [sInstruction, sRegCombi])); + + inc(iAsmCounter); + case OpMode of + omKXM, + omKYM, + omKZM: begin + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKXB32, + omKXB64, + omKYB32, + omKYB64, + omKZB32, + omKZB64: begin + sMREF := OItem3.Values[il_Op3]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'K2', OItem2.Values[il_Op2], sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKMI: begin + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKB32I, + omKB64I: + begin + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + + omMX: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omMXI: begin + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'xmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'xmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', 'XMM0', 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omMY: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omMYI: begin + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'ymm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'ymm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', 'YMM0', 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omMZ: begin + result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omMZI: begin + result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omXB32, + omXB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'XMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + + omXB32I, + omXB64I: begin + sMREF := OItem2.Values[il_Op2]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omXM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'XMM1', OItem2.Values[il_Op2] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omXXM: begin + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omXXB32, + omXXB64: begin + sMREF := OItem3.Values[il_Op3]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'XMM1', 'XMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omXMI: begin + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omYB32, + omYB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'YMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYB32I, + omYB64I: + begin + sMREF := OItem2.Values[il_Op2]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s%6s,%6s + $2000, %s', [aInst, 'YMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'YMM1', OItem2.Values[il_Op2] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omYYM: begin + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYYB32, + omYYB64: begin + sMREF := OItem3.Values[il_Op3]; + //if Pos('{1to4}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to4}', '{1to2}', []) + // else if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to4}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to8}', []); + + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'YMM1', 'YMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + + end; + omYMI: begin + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'YMM1', 'YMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omZB32, + omZB64: begin + sMREF := OItem2.Values[il_Op2]; + result.Add(format('%20s%6s,%6s + $2000', [aInst, 'ZMM1', sMREF])); + result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omZB32I, + omZB64I: + begin + sMREF := OItem2.Values[il_Op2]; + //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', sMREF, OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', sMREF, OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', sMREF, OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + + end; + omZM: begin + result.Add(format('%20s %6s, %s + $2000', [aInst, 'ZMM1', OItem2.Values[il_Op2] ])); + result.Add(format('%20s %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omZZM: begin + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', OItem3.Values[il_Op3] ])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omZZB32, + omZZB64: begin + sMREF := OItem3.Values[il_Op3]; + //if Pos('{1to8}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to8}', '{1to2}', []) + // else if Pos('{1to16}', sMREF) > 0 then sMREF := StringReplace(sMREF, '{1to16}', '{1to4}', []); + + //result.Add(format('%20s%6s,%6s, %s + $00', [aInst, 'XMM1', 'XMM1', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $10', [aInst, 'XMM2', 'XMM2', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $20', [aInst, 'XMM3', 'XMM3', sMREF])); + //result.Add(format('%20s%6s,%6s, %s + $30', [aInst, 'XMM4', 'XMM4', sMREF])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + + result.Add(format('%20s %6s,%6s, %s + $2000', [aInst, 'ZMM1', 'ZMM1', sMREF])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + + end; + omZMI: begin + //result.Add(format('%20s%6s,%6s + $00, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $10, %s', [aInst, 'XMM2', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $20, %s', [aInst, 'XMM3', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + //result.Add(format('%20s%6s,%6s + $30, %s', [aInst, 'XMM4', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + // + //result.Add(format('%20s%6s,%6s, %s, 01', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM2'])); + //result.Add(format('%20s%6s,%6s, %s, 02', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM3'])); + //result.Add(format('%20s%6s,%6s, %s, 03', ['vinserti32x4', 'ZMM1', 'ZMM1', 'XMM4'])); + // + //result.Add(format('%20s%6s,%6s, %s', ['vpcmpeqb', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + //result.Add(format('%20s%6s,%6s, %s', ['kandq', 'K1', 'K1', 'K2'])); + //result.Add(''); + result.Add(format('%20s %6s,%6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], OItem3.Values[il_Op3]])); + result.Add(format('%20s %6s,%6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + + omKXB32I, + omKXB64I: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKXMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKYB32I, + omKYB64I: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + omKYMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s,%6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + + omXXB32I, + omXXB64I: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omXXMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'XMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omYYB32I, + omYYB64I, + omYYMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'YMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + omKZB32I, + omKZB64I, + omKZMI: + begin + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'K2', OItem2.Values[il_Op2], OItem3.Values[il_Op3], OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %s', ['kxorq', 'K2', OItem1.Values[il_Op1], 'K2'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmXORTestNZ)); + end; + //omKZMI: + // begin + // sMREF := OItem3.Values[il_Op3]; + // + // result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + // result.Add(format('%20s %6s, %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + // + // result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + // end; + + omZZB32I, + omZZB64I, + omZZMI: + begin + sMREF := OItem3.Values[il_Op3]; + + result.Add(format('%20s %6s, %6s, %6s + $2000, %s', [aInst, 'ZMM1', OItem2.Values[il_Op2], sMREF, OItem4.Values[il_Op4]])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + + result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); + end; + else begin + sLogMsg := ''; + sLogMsg := MapOperand(OItem1.Optyp) + MapOperand(OItem2.Optyp) + MapOperand(OItem3.Optyp); + writeln('offen - : ' + sLogMsg + ' (' + aInst + ')'); + end; + end; + + sRegCombi := ''; + end; + end; + end; + end; + end; + end; + + + + //sl_Inst := format('%-20s', [aInst]); + // + //for il_Op1 := 0 to OItem1.Values.Count - 1 do + //begin + // if OItem1.OpActive then + // begin + // sl_RegCombi1 := OItem1.Values[il_Op1]; + // end + // else sl_RegCombi1 := ''; + // + // for il_Op2 := 0 to OItem2.Values.Count - 1 do + // begin + // if OItem2.OpActive then + // begin + // sl_RegCombi2 := sl_RegCombi1 + ', ' + OItem2.Values[il_Op2]; + // end + // else sl_RegCombi2 := sl_RegCombi1; + // + // for il_Op3 := 0 to OItem3.Values.Count - 1 do + // begin + // if OItem3.OpActive then + // begin + // sl_RegCombi3 := sl_RegCombi2 + ', ' + OItem3.Values[il_Op3]; + // end + // else sl_RegCombi3 := sl_RegCombi2; + // + // for il_Op4 := 0 to OItem4.Values.Count - 1 do + // begin + // if OItem4.OpActive then + // begin + // sl_RegCombi := sl_RegCombi3 + ', ' + OItem4.Values[il_Op4]; + // end + // else sl_RegCombi := sl_RegCombi3; + // + // if (sl_RegCombi <> '') and + // ( + // (OItem1.OpActive and (OItem1.OpTyp in OTMEMTYPES)) or + // (OItem2.OpActive and (OItem2.OpTyp in OTMEMTYPES)) or + // (OItem3.OpActive and (OItem3.OpTyp in OTMEMTYPES)) or + // (OItem4.OpActive and (OItem4.OpTyp in OTMEMTYPES)) + // ) then + // begin + // //result.Add(format('%-20s%s', [aInst, sl_RegCombi])); + // result.Add(sl_Inst + sl_RegCombi); + // + // + // + // sl_RegCombi := ''; + // end; + // end; + // end; + // end; + //end; + end; + finally + FreeAndNil(OItem4); + end; + finally + FreeAndNil(OItem3); + end; + finally + FreeAndNil(OItem2); + end; + finally + FreeAndNil(OItem1); + end; +end; + + +constructor TAsmTestGenerator.Create; +begin + inherited; + + FX64 := true; + FAVX512 := false; + + FReg8 := TStringList.Create; + FReg16 := TStringList.Create; + + FReg32Base := TStringList.Create; + FReg32Index := TStringList.Create; + FReg64Base := TStringList.Create; + FReg64Index := TStringList.Create; + FReg6432Base := TStringList.Create; + FReg6432Index := TStringList.Create; + FReg32XMMIndex := TStringList.Create; + FReg32YMMIndex := TStringList.Create; + FReg32ZMMIndex := TStringList.Create; + FReg64XMMIndex := TStringList.Create; + FReg64YMMIndex := TStringList.Create; + FReg64ZMMIndex := TStringList.Create; + FRegKREG := TStringList.Create; + + FReg8.Add('AL'); + FReg8.Add('BL'); + FReg8.Add('CL'); + FReg8.Add('DL'); + + + FReg16.Add('AX'); + FReg16.Add('BX'); + FReg16.Add('CX'); + FReg16.Add('DX'); + + + FReg32Base.Add('EAX'); + FReg32Base.Add('EBX'); + FReg32Base.Add('ECX'); + FReg32Base.Add('EDX'); + //FReg32Base.Add('ESP'); + //FReg32Base.Add('EBP'); + FReg32Base.Add('EDI'); + FReg32Base.Add('ESI'); + + + FReg32Index.Add('EAX'); + FReg32Index.Add('EBX'); + FReg32Index.Add('ECX'); + FReg32Index.Add('EDX'); + //FReg32Index.Add('EBP'); + FReg32Index.Add('EDI'); + FReg32Index.Add('ESI'); + + + FReg64Base.Add('RAX'); + FReg64Base.Add('RBX'); + FReg64Base.Add('RCX'); + FReg64Base.Add('RDX'); + //FReg64Base.Add('RSP'); + //FReg64Base.Add('RBP'); + FReg64Base.Add('RDI'); + FReg64Base.Add('RSI'); + FReg64Base.Add('R8'); + FReg64Base.Add('R9'); + FReg64Base.Add('R10'); + FReg64Base.Add('R11'); + FReg64Base.Add('R12'); + FReg64Base.Add('R13'); + FReg64Base.Add('R14'); + FReg64Base.Add('R15'); + + FReg64Index.Add('RAX'); + FReg64Index.Add('RBX'); + FReg64Index.Add('RCX'); + FReg64Index.Add('RDX'); + //FReg64Index.Add('RBP'); + FReg64Index.Add('RDI'); + FReg64Index.Add('RSI'); + FReg64Index.Add('R8'); + FReg64Index.Add('R9'); + FReg64Index.Add('R10'); + FReg64Index.Add('R11'); + FReg64Index.Add('R12'); + FReg64Index.Add('R13'); + FReg64Index.Add('R14'); + FReg64Index.Add('R15'); + + FReg6432Base.Add('EAX'); + FReg6432Base.Add('EBX'); + FReg6432Base.Add('ECX'); + FReg6432Base.Add('EDX'); + FReg6432Base.Add('ESP'); + //FReg6432Base.Add('EBP'); + FReg6432Base.Add('EDI'); + FReg6432Base.Add('ESI'); + FReg6432Base.Add('R8D'); + FReg6432Base.Add('R9D'); + FReg6432Base.Add('R10D'); + FReg6432Base.Add('R11D'); + FReg6432Base.Add('R12D'); + FReg6432Base.Add('R13D'); + FReg6432Base.Add('R14D'); + FReg6432Base.Add('R15D'); + + FReg6432Index.Add('EAX'); + FReg6432Index.Add('EBX'); + FReg6432Index.Add('ECX'); + FReg6432Index.Add('EDX'); + //FReg6432Index.Add('EBP'); + FReg6432Index.Add('EDI'); + FReg6432Index.Add('ESI'); + FReg6432Index.Add('R8D'); + FReg6432Index.Add('R9D'); + FReg6432Index.Add('R10D'); + FReg6432Index.Add('R11D'); + FReg6432Index.Add('R12D'); + FReg6432Index.Add('R13D'); + FReg6432Index.Add('R14D'); + FReg6432Index.Add('R15D'); + + FReg32XMMIndex.ADD('XMM0'); + FReg32XMMIndex.ADD('XMM1'); + FReg32XMMIndex.ADD('XMM2'); + FReg32XMMIndex.ADD('XMM3'); + FReg32XMMIndex.ADD('XMM4'); + FReg32XMMIndex.ADD('XMM5'); + FReg32XMMIndex.ADD('XMM6'); + FReg32XMMIndex.ADD('XMM7'); + + FReg32YMMIndex.ADD('YMM0'); + FReg32YMMIndex.ADD('YMM1'); + FReg32YMMIndex.ADD('YMM2'); + FReg32YMMIndex.ADD('YMM3'); + FReg32YMMIndex.ADD('YMM4'); + FReg32YMMIndex.ADD('YMM5'); + FReg32YMMIndex.ADD('YMM6'); + FReg32YMMIndex.ADD('YMM7'); + + FReg32ZMMIndex.ADD('ZMM0'); + FReg32ZMMIndex.ADD('ZMM1'); + FReg32ZMMIndex.ADD('ZMM2'); + FReg32ZMMIndex.ADD('ZMM3'); + FReg32ZMMIndex.ADD('ZMM4'); + FReg32ZMMIndex.ADD('ZMM5'); + FReg32ZMMIndex.ADD('ZMM6'); + FReg32ZMMIndex.ADD('ZMM7'); + + + FReg64XMMIndex.ADD('XMM0'); + FReg64XMMIndex.ADD('XMM1'); + FReg64XMMIndex.ADD('XMM2'); + FReg64XMMIndex.ADD('XMM3'); + FReg64XMMIndex.ADD('XMM4'); + FReg64XMMIndex.ADD('XMM5'); + FReg64XMMIndex.ADD('XMM6'); + FReg64XMMIndex.ADD('XMM7'); + FReg64XMMIndex.ADD('XMM8'); + FReg64XMMIndex.ADD('XMM9'); + FReg64XMMIndex.ADD('XMM10'); + FReg64XMMIndex.ADD('XMM11'); + FReg64XMMIndex.ADD('XMM12'); + FReg64XMMIndex.ADD('XMM13'); + FReg64XMMIndex.ADD('XMM14'); + FReg64XMMIndex.ADD('XMM15'); + + + FReg64YMMIndex.ADD('YMM0'); + FReg64YMMIndex.ADD('YMM1'); + FReg64YMMIndex.ADD('YMM2'); + FReg64YMMIndex.ADD('YMM3'); + FReg64YMMIndex.ADD('YMM4'); + FReg64YMMIndex.ADD('YMM5'); + FReg64YMMIndex.ADD('YMM6'); + FReg64YMMIndex.ADD('YMM7'); + FReg64YMMIndex.ADD('YMM8'); + FReg64YMMIndex.ADD('YMM9'); + FReg64YMMIndex.ADD('YMM10'); + FReg64YMMIndex.ADD('YMM11'); + FReg64YMMIndex.ADD('YMM12'); + FReg64YMMIndex.ADD('YMM13'); + FReg64YMMIndex.ADD('YMM14'); + FReg64YMMIndex.ADD('YMM15'); + + FReg64ZMMIndex.ADD('ZMM0'); + FReg64ZMMIndex.ADD('ZMM1'); + FReg64ZMMIndex.ADD('ZMM2'); + FReg64ZMMIndex.ADD('ZMM3'); + FReg64ZMMIndex.ADD('ZMM4'); + FReg64ZMMIndex.ADD('ZMM5'); + FReg64ZMMIndex.ADD('ZMM6'); + FReg64ZMMIndex.ADD('ZMM7'); + FReg64ZMMIndex.ADD('ZMM8'); + FReg64ZMMIndex.ADD('ZMM9'); + FReg64ZMMIndex.ADD('ZMM10'); + FReg64ZMMIndex.ADD('ZMM11'); + FReg64ZMMIndex.ADD('ZMM12'); + FReg64ZMMIndex.ADD('ZMM13'); + FReg64ZMMIndex.ADD('ZMM14'); + FReg64ZMMIndex.ADD('ZMM15'); + FReg64ZMMIndex.ADD('ZMM16'); + FReg64ZMMIndex.ADD('ZMM17'); + FReg64ZMMIndex.ADD('ZMM18'); + FReg64ZMMIndex.ADD('ZMM19'); + FReg64ZMMIndex.ADD('ZMM20'); + FReg64ZMMIndex.ADD('ZMM21'); + FReg64ZMMIndex.ADD('ZMM22'); + FReg64ZMMIndex.ADD('ZMM23'); + FReg64ZMMIndex.ADD('ZMM24'); + FReg64ZMMIndex.ADD('ZMM25'); + FReg64ZMMIndex.ADD('ZMM26'); + FReg64ZMMIndex.ADD('ZMM27'); + FReg64ZMMIndex.ADD('ZMM28'); + FReg64ZMMIndex.ADD('ZMM29'); + FReg64ZMMIndex.ADD('ZMM30'); + FReg64ZMMIndex.ADD('ZMM31'); + + FRegKREG.ADD('K0'); + FRegKREG.ADD('K1'); + FRegKREG.ADD('K2'); + FRegKREG.ADD('K3'); + FRegKREG.ADD('K4'); + FRegKREG.ADD('K5'); + FRegKREG.ADD('K6'); + FRegKREG.ADD('K7'); + +end; + +destructor TAsmTestGenerator.Destroy; +begin + FreeAndNil(FReg8); + FreeAndNil(FReg16); + + FreeAndNil(FReg32Base); + FreeAndNil(FReg32Index); + FreeAndNil(FReg64Base); + FreeAndNil(FReg64Index); + FreeAndNil(FReg6432Base); + FreeAndNil(FReg6432Index); + + FreeAndNil(FReg32XMMIndex); + FreeAndNil(FReg32YMMIndex); + FreeAndNil(FReg32ZMMIndex); + FreeAndNil(FReg64XMMIndex); + FreeAndNil(FReg64YMMIndex); + FreeAndNil(FReg64ZMMIndex); + + FreeAndnil(FRegKREG); + + inherited; +end; + +procedure TAsmTestGenerator.MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, + aSLIndexReg, aRList: TStringList); +var + il_Base: integer; + il_Index: integer; +begin + + for il_Base := 0 to aSLBaseReg.Count - 1 do + begin + aRList.Add(format(aPrefix + '[%s]%s', [aSLBaseReg[il_Base], aSuffix])); + + for il_Index := 0 to aSLIndexReg.Count - 1 do + begin + aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s + $10]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s + $40]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s - $10]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s - $40]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + + + aRList.Add(format(aPrefix + '[%s + %s * 2]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 4]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 8]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + + aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 8 + 64]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + end; + end; +end; + +procedure TAsmTestGenerator.MemRegBaseIndexCombiCDISP8N(const aPrefix, + aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList); +var + iBase: integer; + iIndex: integer; + iOffset: integer; +begin + + for iBase := 0 to aSLBaseReg.Count - 1 do + begin + for iOffset := 0 to 63 do + begin + aRList.Add(format(aPrefix + '[%s +%2d]', [aSLBaseReg[iBase], iOffset])); + + for iIndex := 0 to aSLIndexReg.Count - 1 do + begin + if aSLBaseReg[iBase] <> aSLIndexReg[iIndex] then + begin + aRList.Add(format(aPrefix + '[%s + %s + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 2 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 4 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + aRList.Add(format(aPrefix + '[%s + %s * 8 + %2d]', [aSLBaseReg[iBase], aSLIndexReg[iIndex], iOffset])); + end; + end; + end; + end; +end; + +procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; + aSLBaseReg, aSLIndexReg, aRList: TStringList); +var + il_Base: integer; + il_Index: integer; +begin + + //for il_Index := 0 to aSLIndexReg.Count - 1 do + //begin + // aRList.Add(format(aPrefix + '[%s]', [aSLIndexReg[il_Index]])); + // + // aRList.Add(format(aPrefix + '[%s * 2]', [aSLIndexReg[il_Index]])); + // aRList.Add(format(aPrefix + '[%s * 4]', [aSLIndexReg[il_Index]])); + // aRList.Add(format(aPrefix + '[%s * 8]', [aSLIndexReg[il_Index]])); + // + // aRList.Add(format(aPrefix + '[%s * 2 + 16]', [aSLIndexReg[il_Index]])); + // aRList.Add(format(aPrefix + '[%s * 4 + 32]', [aSLIndexReg[il_Index]])); + // aRList.Add(format(aPrefix + '[%s * 8 + 48]', [aSLIndexReg[il_Index]])); + //end; + + + for il_Base := 0 to aSLBaseReg.Count - 1 do + begin + //aRList.Add(format(aPrefix + '[%s]', [aSLBaseReg[il_Base]])); + + for il_Index := 0 to aSLIndexReg.Count - 1 do + begin + aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + + aRList.Add(format(aPrefix + '[%s + %s * 2]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 4]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + aRList.Add(format(aPrefix + '[%s + %s * 8]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix])); + + //aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); + //aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); + //aRList.Add(format(aPrefix + '[%s + %s * 8 + 48]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]])); + + + aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLIndexReg[il_Index], aSLBaseReg[il_Base], aSuffix])); + + //aRList.Add(format(aPrefix + '[%s + %s + 16]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]])); + end; + end; +end; + +function TAsmTestGenerator.ParseBaseIndexReg(const aOp: string; var aBaseReg, + aIndexReg: string): boolean; +var + iStartPos: integer; + iEndPos: integer; + iPos: integer; + sOp: string; + sBaseReg: string; + sIndexReg: string; +begin + result := false; + + aBaseReg := ''; + aIndexReg := ''; + + iStartPos := Pos('[', aOp); + iEndPos := Pos(']', aOp); + + if (iStartPos > 0) and + (iEndPos > 0) and + (iStartPos < iEndPos) then + begin + sOp := trim(copy(aOp, iStartPos + 1, iEndPos - iStartPos - 1)); + + with TStringList.Create do + try + CommaText := StringReplace(sOp, '+', ',', [rfReplaceAll]); + + while Count < 2 do Add(''); + + sBaseReg := trim(Strings[0]); + + if (FReg32Base.IndexOf(sBasereg) >= 0) or + (FReg64Base.IndexOf(sBasereg) >= 0) or + (FReg6432Base.IndexOf(sBasereg) >= 0) then + aBaseReg := sBaseReg; + + sIndexReg := trim(Strings[1]); + + if (FReg32Index.IndexOf(sIndexReg) >= 0) or + (FReg64Index.IndexOf(sIndexReg) >= 0) or + (FReg6432Index.IndexOf(sIndexReg) >= 0) then + aIndexReg := sIndexReg; + + result := trim(aBasereg) <> ''; + finally + Free; + end; + end; +end; + +class procedure TAsmTestGenerator.CalcTestData(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, + aOp4: String; aSL: TStringList); +var + sl: TStringList; +begin + with TAsmTestGenerator.Create do + try + Fx64 := aX64; + FAVX512 := aAVX512; + FSAE := aSAE; + + sl := InternalCalcTestData(aInst, aOp1, aOp2, aOp3, aOp4); + try + aSL.AddStrings(sl); + finally + FreeAndNil(sl); + end; + finally + Free; + end; +end; + +class procedure TAsmTestGenerator.CalcTestDataMREF(aX64, aAVX512, aSAE: boolean; const aInst, aOp1, aOp2, aOp3, + aOp4: String; aSL: TStringList); +var + sl: TStringList; +begin + with TAsmTestGenerator.Create do + try + Fx64 := aX64; + FAVX512 := aAVX512; + FSAE := aSAE; + + sl := InternalCalcTestDataMREF(aInst, aOp1, aOp2, aOp3, aOp4); + try + aSL.AddStrings(sl); + finally + FreeAndNil(sl); + end; + finally + Free; + end; +end; + +class procedure TAsmTestGenerator.CalcTestDataCDisp8(aX64, aAVX512, + aSAE: boolean; const aInst, aOp1, aOp2, aOp3, aOp4: String; aSL: TStringList); +var + sl: TStringList; +begin + with TAsmTestGenerator.Create do + try + Fx64 := aX64; + FAVX512 := aAVX512; + FSAE := aSAE; + + sl := InternalCalcTestDataCDisp8(aInst, aOp1, aOp2, aOp3, aOp4); + try + aSL.AddStrings(sl); + finally + FreeAndNil(sl); + end; + finally + Free; + end; +end; + + + +class procedure TAsmTestGenerator.CalcTestInstFile; +var + i,j: integer; + sInst: string; + sI386: string; + sX8664: string; + sAVX512: string; + sOperands: string; + + sLine: string; + + + sl: TStringList; + bVEX: boolean; + bEVEX: boolean; + b256 : boolean; + b512 : boolean; +begin + sl := TStringList.Create; + try + + //tinsentry=packed record + // opcode : tasmop; + // ops : byte; + // //optypes : array[0..max_operands-1] of longint; + // optypes : array[0..3] of int64; //TG + // code : array[0..11] of char; + // flags : tinsflags; + //end; + + for i := 0 to length(InsTab) - 1 do + begin + bVEX := false; + bEVEX := false; + b256 := false; + b512 := false; + + //TG TODO delete + if instab[i].opcode = a_vtestps then + begin + b512 := b512; + end; + + for j := 0 to length(InsTab[i].code) - 1 do + begin + case ord(InsTab[i].code[j]) of + 0: break; + 1,2,3: break; + 232: bEVEX := true; + 233: b512 := true; + 242: bVEX := true; + 244: b256 := true; + end; + end; + + if bVEX or bEVEX then + begin + sInst := std_op2str[InsTab[i].opcode]; + sI386 := '1'; + sX8664 := '1'; + if IF_X86_64 in InsTab[i].flags then + begin + sI386 := '0'; + end; + + if bEVEX then sAVX512 := '1' + else sAVX512 := '0'; + + sOperands := ''; + for j := 0 to 3 do + begin + case InsTab[i].optypes[j] of + OT_XMMREG: sOperands := sOperands + 'XMMREG,'; + OT_XMMREG_M: sOperands := sOperands + 'XMMREG_M,'; + OT_XMMREG_MZ: sOperands := sOperands + 'XMMREG_MZ,'; + OT_XMMREG_ER: sOperands := sOperands + 'XMMREG_ER,'; + OT_XMMREG_SAE: sOperands := sOperands + 'XMMREG_SAE,'; + OT_XMMRM: sOperands := sOperands + 'XMMRM,'; + OT_XMMRM_MZ: sOperands := sOperands + 'XMMRM_MZ,'; + + OT_YMMREG: sOperands := sOperands + 'YMMREG,'; + OT_YMMREG_M: sOperands := sOperands + 'YMMREG_M,'; + OT_YMMREG_MZ: sOperands := sOperands + 'YMMREG_MZ,'; + OT_YMMREG_ER: sOperands := sOperands + 'YMMREG_ER,'; + OT_YMMREG_SAE: sOperands := sOperands + 'YMMREG_SAE,'; + OT_YMMRM: sOperands := sOperands + 'YMMRM,'; + OT_YMMRM_MZ: sOperands := sOperands + 'YMMRM_MZ,'; + + OT_ZMMREG: sOperands := sOperands + 'ZMMREG,'; + OT_ZMMREG_M: sOperands := sOperands + 'ZMMREG_M,'; + OT_ZMMREG_MZ: sOperands := sOperands + 'ZMMREG_MZ,'; + OT_ZMMREG_ER: sOperands := sOperands + 'ZMMREG_ER,'; + OT_ZMMREG_SAE: sOperands := sOperands + 'ZMMREG_SAE,'; + OT_ZMMRM: sOperands := sOperands + 'ZMMRM,'; + OT_ZMMRM_MZ: sOperands := sOperands + 'ZMMRM_MZ,'; + + OT_MEM32: sOperands := sOperands + 'MEM32,'; + OT_MEM64: sOperands := sOperands + 'MEM64,'; + OT_MEM128: sOperands := sOperands + 'MEM128,'; + OT_MEM256: sOperands := sOperands + 'MEM256,'; + OT_MEM512: sOperands := sOperands + 'MEM512,'; + + OT_REG32: sOperands := sOperands + 'REG32,'; + OT_REG64: sOperands := sOperands + 'REG64,'; + ot_rm_gpr or ot_bits32: + sOperands := sOperands + 'RM32,'; + ot_rm_gpr or ot_bits64: + sOperands := sOperands + 'RM64,'; + + OT_XMEM32: sOperands := sOperands + 'XMEM32,'; + OT_XMEM64: sOperands := sOperands + 'XMEM64,'; + + OT_YMEM32: sOperands := sOperands + 'YMEM32,'; + OT_YMEM64: sOperands := sOperands + 'YMEM64,'; + + OT_IMM8: sOperands := sOperands + 'IMM8,'; + OT_NONE: sOperands := sOperands + ','; + + OT_BMEM32: if b512 then sOperands := sOperands + '16B32,' + else if b256 then sOperands := sOperands + '8B32,' + else sOperands := sOperands + '4B32,'; + OT_BMEM64: if b512 then sOperands := sOperands + '8B32,' + else if b256 then sOperands := sOperands + '4B32,' + else sOperands := sOperands + '2B64,'; + + OT_KREG: sOperands := sOperands + 'KREG,'; + OT_KREG_M: sOperands := sOperands + 'KREG_M,'; + + else sOperands := sOperands; + end; + end; + + sOperands := copy(sOperands, 1, length(sOperands) - 1); + + sl.Add(format('FOpCodeList.Add(''%s,%s,%s,%s,%s'');', [sInst, sI386, sX8664, sAVX512, sOperands])); + end; + + end; + + sl.Savetofile('/tmp/fpcavx512.txt'); + + // std_op2str + + finally + FreeAndnil(sl); + end; +end; + +class procedure TAsmTestGenerator.ListMemRefState; +var + i: integer; + sGasSufffix: string; + mrsize: TMemRefSizeInfo; + opcode: tasmop; + sl: TStringList; + slEmpty: TStringList; +begin + BuildInsTabCache; + BuildInsTabMemRefSizeInfoCache; + + slEmpty := TStringList.Create; + try + for mrsize := low(TMemRefSizeInfo) to high(TMemRefSizeInfo) do + begin + + sl := TStringList.Create; + try + for opcode:=low(tasmop) to high(tasmop) do + begin + if InsTabMemRefSizeInfoCache^[opcode].MemRefSize = mrsize then + begin + sGasSufffix:=''; + if gas_needsuffix[opcode] <> AttSufNone then + sGasSufffix:=GetEnumName(Typeinfo(TAttSuffix), ord(gas_needsuffix[opcode])); + + sl.add(format('%-25s: %s: %s', [GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize)), std_op2str[opcode], sGasSufffix])); + end; + end; + + sl.Sort; + + if sl.Count > 0 then + begin + writeln; + + writeln(sl.text); + end + else slEmpty.Add(GetEnumName(Typeinfo(TMemRefSizeInfo), ord(mrsize))); + + + finally + FreeAndNil(sl); + end; + end; + + slEmpty.Sort; + writeln(''); + writeln(slEmpty.Text); + finally + FreeAndNil(slEmpty); + end; + + if assigned(instabcache) then + begin + dispose(instabcache); + instabcache:=nil; + end; + + if assigned(InsTabMemRefSizeInfoCache) then + begin + dispose(InsTabMemRefSizeInfoCache); + InsTabMemRefSizeInfoCache:=nil; + end; + + +end; + +end. From ad753c0bbd52d42685ef5cdb0406c2c7e369c605 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 5 Mar 2021 16:08:34 +0000 Subject: [PATCH 071/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48880 - --- tests/utils/avx/asmtestgenerator.pas | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 6ad2dbc817..522d5f749b 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -5277,8 +5277,8 @@ begin omMZ: begin result.Add(format('%20s %6s + $2000, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2]])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s', ['vmovdqu8', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu8', 'zmm1', OItem1.Values[il_Op1]])); result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); @@ -5287,8 +5287,8 @@ begin omMZI: begin result.Add(format('%20s %6s + $2000, %6s, %s', [aInst, OItem1.Values[il_Op1], OItem2.Values[il_Op2], OItem3.Values[il_Op3] ])); - result.Add(format('%20s %6s, %s', ['vmovdqu', 'zmm0', OItem1.Values[il_Op1]])); - result.Add(format('%20s %6s, %s + $2000', ['vmovdqu', 'zmm1', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s', ['vmovdqu8', 'zmm0', OItem1.Values[il_Op1]])); + result.Add(format('%20s %6s, %s + $2000', ['vmovdqu8', 'zmm1', OItem1.Values[il_Op1]])); result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', 'ZMM0', 'ZMM1'])); @@ -5320,7 +5320,7 @@ begin omXM: begin result.Add(format('%20s %6s, %s + $2000', [aInst, 'XMM1', OItem2.Values[il_Op2] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqw', 'K2', OItem1.Values[il_Op1], 'XMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5380,7 +5380,7 @@ begin end; omYM: begin result.Add(format('%20s %6s, %s + $2000', [aInst, 'YMM1', OItem2.Values[il_Op2] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqd', 'K2', OItem1.Values[il_Op1], 'YMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; @@ -5468,7 +5468,7 @@ begin end; omZM: begin result.Add(format('%20s %6s, %s + $2000', [aInst, 'ZMM1', OItem2.Values[il_Op2] ])); - result.Add(format('%20s %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); + result.Add(format('%20s %6s, %6s, %s', ['vpcmpeqq', 'K2', OItem1.Values[il_Op1], 'ZMM1'])); result.Add(AsmCodeBlockCompare(iAsmCounter, cmKORTESTNC)); end; From b4a002e3e777f7a26040bf42a2372a8f1908e9ba Mon Sep 17 00:00:00 2001 From: tg74 Date: Tue, 9 Mar 2021 16:31:02 +0000 Subject: [PATCH 072/116] working on new testmethods avx512-memref-operands - 'compressed disp8*N' git-svn-id: branches/tg74/avx512-0037785@48927 - --- tests/utils/avx/asmtestgenerator.pas | 31 +++++++++++++++++++++------- tests/utils/avx/avxopcodes.pas | 6 ++++++ 2 files changed, 29 insertions(+), 8 deletions(-) diff --git a/tests/utils/avx/asmtestgenerator.pas b/tests/utils/avx/asmtestgenerator.pas index 522d5f749b..89f1adccd7 100644 --- a/tests/utils/avx/asmtestgenerator.pas +++ b/tests/utils/avx/asmtestgenerator.pas @@ -3776,14 +3776,29 @@ var Add(format('%20s%6s', [' pop', sReg])); case aComparemode of - cmKORTESTNC: begin - Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); - Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); - end; - cmXORTestNZ: begin - Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); - Add(format('%20s %6s', [' jnz', '@@CHECKRESULT'])); - end; + //cmKORTESTNC: begin + // Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); + // Add(format('%20s %6s', [' jnc', '@@CHECKRESULT'])); + // end; + //cmXORTestNZ: begin + // Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); + // Add(format('%20s %6s', [' jnz', '@@CHECKRESULT'])); + // end; + cmKORTESTNC: begin + Add(format('%20s%6s, %s', ['ktestb', 'K2', 'K1'])); + Add(format('%20s%6s, %s', [' kmovq', 'R10', 'K6'])); + Add(format('%20s%6s, @@%d[RIP]', ['cmovc', 'R10', aAsmCounter])); + Add(format('%20s %6s', [' jmp', 'R10'])); + Add(format(' @@%d%s', [aAsmCounter, ':'])); + end; + cmXORTestNZ: begin + Add(format('%20s%6s, %s', ['kortestq', 'K2', 'K2'])); + Add(format('%20s%6s, %s', [' kmovq', 'R10', 'K6'])); + Add(format('%20s%6s, @@%d[RIP]', ['cmovz', 'R10', aAsmCounter])); + Add(format('%20s %6s', [' jmp', 'R10'])); + Add(format(' @@%d%s', [aAsmCounter, ':'])); + end; + end; result := Text; diff --git a/tests/utils/avx/avxopcodes.pas b/tests/utils/avx/avxopcodes.pas index 4644562c23..e31b7f2c1b 100644 --- a/tests/utils/avx/avxopcodes.pas +++ b/tests/utils/avx/avxopcodes.pas @@ -3734,11 +3734,17 @@ begin if aX64 then begin + slHeader.Add(' lea rax, @@CHECKRESULT'); + slHeader.Add(' kmovq k6, rax'); + slHeader.Add(' lea rax, DataBlock'); slHeader.Add(' push rax'); end else begin + slHeader.Add(' lea eax, @@CHECKRESULT'); + slHeader.Add(' kmovd k6, eax'); + slHeader.Add(' lea eax, DataBlock'); slHeader.Add(' push eax'); end; From 43b29375899276a2734571d2be8daef68e5b9008 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 18 Jun 2021 14:06:55 +0000 Subject: [PATCH 073/116] activate 'compressed disp8*N' for VCVTQQ2PS xmmreg, xmmrm and VCVTTPD2UDQ xmmreg, xmmrm git-svn-id: branches/tg74/avx512-0037785@49512 - --- compiler/x86/x86ins.dat | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index e30a93c7ff..431323eae5 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -7351,7 +7351,7 @@ zmmreg_mz,zmmreg_er \333\350\351\352\370\1\xE6\110 [VCVTQQ2PS,vcvtqq2psN] (Ch_Wop2, Ch_Rop1) xmmreg_mz,mem256 \350\352\364\370\1\x5B\110 AVX512,TFV -xmmreg_mz,xmmrm \350\352\370\1\x5B\110 AVX512 +xmmreg_mz,xmmrm \350\352\370\1\x5B\110 AVX512,TFV xmmreg_mz,bmem64 \350\352\370\1\x5B\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x5B\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x5B\110 AVX512 @@ -7388,7 +7388,7 @@ zmmreg_mz,zmmreg_sae \350\351\352\361\370\1\x7A\110 [VCVTTPD2UDQ,vcvttpd2udqN] (Ch_Wop2, Ch_Rop1) xmmreg_mz,mem256 \350\352\364\370\1\x78\110 AVX512,TFV -xmmreg_mz,xmmrm \350\352\370\1\x78\110 AVX512 +xmmreg_mz,xmmrm \350\352\370\1\x78\110 AVX512,TFV xmmreg_mz,bmem64 \350\352\370\1\x78\110 AVX512,BCST2,TFV xmmreg_mz,bmem64 \350\352\364\370\1\x78\110 AVX512,BCST4,TFV xmmreg_mz,ymmreg \350\352\364\370\1\x78\110 AVX512 From 7368fcf4c5a6845a0c2257ae0479556850184565 Mon Sep 17 00:00:00 2001 From: tg74 Date: Fri, 18 Jun 2021 14:07:13 +0000 Subject: [PATCH 074/116] activate 'compressed disp8*N' for VCVTQQ2PS xmmreg, xmmrm and VCVTTPD2UDQ xmmreg, xmmrm git-svn-id: branches/tg74/avx512-0037785@49513 - --- compiler/i386/i386tab.inc | 4 ++-- compiler/i8086/i8086tab.inc | 4 ++-- compiler/x86_64/x8664tab.inc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc index 0e77fd38ac..f7408d9277 100644 --- a/compiler/i386/i386tab.inc +++ b/compiler/i386/i386tab.inc @@ -21614,7 +21614,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTQQ2PS; @@ -21768,7 +21768,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTTPD2UDQ; diff --git a/compiler/i8086/i8086tab.inc b/compiler/i8086/i8086tab.inc index 8b3ff20eae..02ef547d88 100644 --- a/compiler/i8086/i8086tab.inc +++ b/compiler/i8086/i8086tab.inc @@ -21838,7 +21838,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTQQ2PS; @@ -21992,7 +21992,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTTPD2UDQ; diff --git a/compiler/x86_64/x8664tab.inc b/compiler/x86_64/x8664tab.inc index 35d40e3eb9..dc04d4260a 100644 --- a/compiler/x86_64/x8664tab.inc +++ b/compiler/x86_64/x8664tab.inc @@ -22048,7 +22048,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#91#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTQQ2PS; @@ -22202,7 +22202,7 @@ ops : 2; optypes : (ot_xmmreg_mz,ot_xmmrm,ot_none,ot_none); code : #232#234#248#1#120#72; - flags : [if_avx512] + flags : [if_avx512,if_tfv] ), ( opcode : A_VCVTTPD2UDQ; From 4401ef32bb51ed138015821fc2c8f51c467fec6d Mon Sep 17 00:00:00 2001 From: mattias Date: Wed, 18 Aug 2021 09:45:26 +0200 Subject: [PATCH 075/116] pastojs: emulate compile time assign integer constant of different type --- packages/fcl-passrc/src/pasresolveeval.pas | 4 +- packages/fcl-passrc/src/pasresolver.pp | 22 ++++- packages/pastojs/src/fppas2js.pp | 107 ++++++++++++++++++++- packages/pastojs/tests/tcmodules.pas | 105 +++++++++++++++++++- 4 files changed, 230 insertions(+), 8 deletions(-) diff --git a/packages/fcl-passrc/src/pasresolveeval.pas b/packages/fcl-passrc/src/pasresolveeval.pas index ef77d79f55..3731543297 100644 --- a/packages/fcl-passrc/src/pasresolveeval.pas +++ b/packages/fcl-passrc/src/pasresolveeval.pas @@ -787,7 +787,7 @@ type function EvalStrFunc(Params: TParamsExpr; Flags: TResEvalFlags): TResEvalValue; virtual; function EvalStringAddExpr(Expr, LeftExpr, RightExpr: TPasExpr; LeftValue, RightValue: TResEvalValue): TResEvalValue; virtual; - function LoHiValue(Value: TResEvalValue; ShiftSize: Integer; Mask: LongWord; + function ShiftAndMaskValue(Value: TResEvalValue; ShiftSize: Integer; Mask: LongWord; ErrorEl: TPasElement): TResEvalValue; virtual; function EnumTypeCast(EnumType: TPasEnumType; Expr: TPasExpr; Flags: TResEvalFlags): TResEvalEnum; virtual; @@ -5273,7 +5273,7 @@ begin end; end; -function TResExprEvaluator.LoHiValue(Value: TResEvalValue; ShiftSize: Integer; +function TResExprEvaluator.ShiftAndMaskValue(Value: TResEvalValue; ShiftSize: Integer; Mask: LongWord; ErrorEl: TPasElement): TResEvalValue; var uint: LongWord; diff --git a/packages/fcl-passrc/src/pasresolver.pp b/packages/fcl-passrc/src/pasresolver.pp index f6619307a2..45d10fea4c 100644 --- a/packages/fcl-passrc/src/pasresolver.pp +++ b/packages/fcl-passrc/src/pasresolver.pp @@ -20088,7 +20088,7 @@ begin try ComputeElement(Param,ResolvedParam,[]); Shift := GetShiftAndMaskForLoHiFunc(ResolvedParam.BaseType, Proc.BuiltIn=bfLo, Mask); - Evaluated := fExprEvaluator.LoHiValue(Value,Shift,Mask,Params); + Evaluated := fExprEvaluator.ShiftAndMaskValue(Value,Shift,Mask,Params); finally ReleaseEvalValue(Value); end; @@ -27920,7 +27920,7 @@ begin writeln('TPasResolver.ComputeElement Unary Kind=',TUnaryExpr(El).Kind,' OpCode=',TUnaryExpr(El).OpCode,' OperandResolved=',GetResolverResultDbg(ResolvedEl),' ',GetElementSourcePosStr(El)); {$ENDIF} case TUnaryExpr(El).OpCode of - eopAdd, eopSubtract: + eopAdd: if ResolvedEl.BaseType in (btAllInteger+btAllFloats) then exit else if IsGenericTemplType(ResolvedEl) then @@ -27928,6 +27928,24 @@ begin else RaiseMsg(20170216152532,nIllegalQualifierInFrontOf,sIllegalQualifierInFrontOf, [OpcodeStrings[TUnaryExpr(El).OpCode],GetResolverResultDescription(ResolvedEl)],El); + eopSubtract: + if ResolvedEl.BaseType in (btAllSignedInteger+btAllFloats) then + exit + else if ResolvedEl.BaseType in btAllInteger then + begin + case ResolvedEl.BaseType of + btByte,btWord: + ResolvedEl.BaseType:=btLongint; + btLongWord,btUIntDouble: + ResolvedEl.BaseType:=btIntDouble; + end; + exit; + end + else if IsGenericTemplType(ResolvedEl) then + exit + else + RaiseMsg(20210815225815,nIllegalQualifierInFrontOf,sIllegalQualifierInFrontOf, + [OpcodeStrings[TUnaryExpr(El).OpCode],GetResolverResultDescription(ResolvedEl)],El); eopNot: begin if ResolvedEl.BaseType in (btAllInteger+btAllBooleans) then diff --git a/packages/pastojs/src/fppas2js.pp b/packages/pastojs/src/fppas2js.pp index 9ebb12f78d..a520805493 100644 --- a/packages/pastojs/src/fppas2js.pp +++ b/packages/pastojs/src/fppas2js.pp @@ -462,6 +462,9 @@ unit FPPas2Js; {$define HasInt64} {$endif} +{$IFOPT Q+}{$DEFINE OverflowCheckOn}{$ENDIF} +{$IFOPT R+}{$DEFINE RangeCheckOn}{$ENDIF} + interface uses @@ -2076,6 +2079,7 @@ type RTLFunc: TPas2JSBuiltInName; PosEl: TPasElement): TJSCallExpression; virtual; Function CreateRangeCheckCall_TypeRange(aType: TPasType; GetExpr: TJSElement; AContext: TConvertContext; PosEl: TPasElement): TJSCallExpression; virtual; + Procedure PrepareAssignDifferentIntegers(El: TPasImplAssign; AssignContext: TAssignContext); virtual; // reference Function CreateReferencePath(El: TPasElement; AContext: TConvertContext; Kind: TRefPathKind; Full: boolean = false; Ref: TResolvedReference = nil): string; virtual; @@ -13745,7 +13749,6 @@ begin end; btString: begin - writeln('AAA1 TPasToJSConverter.ConvertBuiltIn_LowHigh ',IsLow); if isLow then // low(aString) -> 1 Result:=CreateLiteralNumber(El,1) @@ -14262,7 +14265,7 @@ begin RaiseInconsistency(20190129102200,El); Param := El.Params[0]; AContext.Resolver.ComputeElement(Param,ResolvedParam,[]); - if not (ResolvedParam.BaseType in btAllInteger) then + if not (ResolvedParam.BaseType in btAllJSInteger) then DoError(20190129121100,nXExpectedButYFound,sXExpectedButYFound,['integer type', AContext.Resolver.GetResolverResultDescription(ResolvedParam)],Param); Shift := AContext.Resolver.GetShiftAndMaskForLoHiFunc(ResolvedParam.BaseType,IsLoFunc,Mask); @@ -22301,6 +22304,7 @@ begin end; if AssignContext.RightSide=nil then AssignContext.RightSide:=ConvertExpression(El.right,AContext); + if (AssignContext.RightResolved.BaseType in [btSet,btArrayOrSet]) and (AssignContext.RightResolved.IdentEl<>nil) then begin @@ -22335,6 +22339,13 @@ begin // e.g. double := currency -> double := currency/10000 AssignContext.RightSide:=CreateDivideNumber(El,AssignContext.RightSide,10000); end + else if (AssignContext.LeftResolved.BaseType<>AssignContext.RightResolved.BaseType) + and (AssignContext.LeftResolved.BaseType in btAllJSInteger) + and (AssignContext.RightResolved.BaseType in btAllJSInteger) then + begin + // AnInteger := OtherInteger + PrepareAssignDifferentIntegers(El,AssignContext); + end else if AssignContext.RightResolved.BaseType in btAllStringAndChars then begin if AssignContext.LeftResolved.BaseType=btContext then @@ -22539,6 +22550,7 @@ begin if (bsRangeChecks in AContext.ScannerBoolSwitches) and not (T.Expr is TJSLiteral) then begin + // range checks if AssignContext.LeftResolved.BaseType in btAllJSInteger then begin if LeftTypeEl is TPasUnresolvedSymbolRef then @@ -24800,6 +24812,97 @@ begin end; end; +procedure TPasToJSConverter.PrepareAssignDifferentIntegers(El: TPasImplAssign; + AssignContext: TAssignContext); + + function CutToUIntDouble(IntValue: TMaxPrecInt): TMaxPrecInt; + begin + {$IFDEF pas2js} + Result:=((IntValue div $80000000) and $003fffff)*$80000000 +(IntValue and $7FFFFFFF); + {$ELSE} + Result:=IntValue and MaxSafeIntDouble; + {$ENDIF} + end; + +var + aResolver: TPas2JSResolver; + LeftBT, RightBT: TResolverBaseType; + Value: TResEvalValue; + IntValue, LeftMinVal, LeftMaxVal, RightMinVal, RightMaxVal: TMaxPrecInt; +begin + aResolver:=AssignContext.Resolver; + LeftBT:=AssignContext.LeftResolved.BaseType; + RightBT:=AssignContext.RightResolved.BaseType; + + if not aResolver.GetIntegerRange(LeftBT,LeftMinVal,LeftMaxVal) then + RaiseNotSupported(El.left,AssignContext,20210815195159); + if not aResolver.GetIntegerRange(RightBT,RightMinVal,RightMaxVal) then + RaiseNotSupported(El.right,AssignContext,20210815195228); + if (LeftMinVal<=RightMinVal) and (LeftMaxVal>=RightMaxVal) then + exit; // right is subset of left + + // right might not fit into left + + Value:=aResolver.Eval(El.right,[]); + try + if Value<>nil then + begin + if Value.Kind=revkInt then + begin + IntValue:=TResEvalInt(Value).Int; + if (IntValue>=LeftMinVal) and (IntValue<=LeftMaxVal) then + exit; + end + else if Value.Kind=revkUInt then + begin + if TResEvalUInt(Value).UInt<=HighIntAsUInt then + begin + IntValue:=TMaxPrecInt(TResEvalUInt(Value).UInt); + if (IntValue>=LeftMinVal) and (IntValue<=LeftMaxVal) then + exit; + end + else + {$IFDEF Pas2js} + RaiseNotSupported(El.right,AssignContext,20210815214534); + {$ELSE} + IntValue:=PMaxPrecInt(@TResEvalUInt(Value).UInt)^; + {$ENDIF} + end + else + RaiseNotSupported(El.right,AssignContext,20210815204203,'right='+Value.AsDebugString); + + case LeftBT of + btByte: IntValue:=IntValue and $FF; // Note: "and" handles negative numbers + btShortInt: + begin + IntValue:=(IntValue and $FF); + if IntValue>$7F then IntValue:=IntValue-$100; + end; + btWord: IntValue:=IntValue and $FFFF; + btSmallInt: + begin + IntValue:=(IntValue and $FFFF); + if IntValue>$7FFF then IntValue:=IntValue-$10000; + end; + btLongWord: IntValue:=IntValue and $FFFFFFFF; + btLongint: + begin + IntValue:=(IntValue and $FFFFFFFF); + if IntValue>$7FFFFFFF then IntValue:=IntValue-$100000000; + end; + btUIntDouble: + IntValue:=CutToUIntDouble(IntValue); + btIntDouble: + IntValue:=CutToUIntDouble(IntValue); + end; + + AssignContext.RightSide:=CreateLiteralNumber(El.right,IntValue); + end; + finally + ReleaseEvalValue(Value); + end; +end; + function TPasToJSConverter.CreateReferencePath(El: TPasElement; AContext: TConvertContext; Kind: TRefPathKind; Full: boolean; Ref: TResolvedReference): string; diff --git a/packages/pastojs/tests/tcmodules.pas b/packages/pastojs/tests/tcmodules.pas index 9bc86951a8..c258b255de 100644 --- a/packages/pastojs/tests/tcmodules.pas +++ b/packages/pastojs/tests/tcmodules.pas @@ -277,6 +277,7 @@ type Procedure TestInteger_BitwiseShrNativeInt; Procedure TestInteger_BitwiseShlNativeInt; Procedure TestInteger_SystemFunc; + Procedure TestInteger_AssignOutsideConst; Procedure TestCurrency; Procedure TestForBoolDo; Procedure TestForIntDo; @@ -3159,8 +3160,8 @@ begin 'this.HiByte2 = (0x1234 >> 8) & 0xFF;', 'this.LoWord1 = 0x1234CDEF & 0xFFFF;', 'this.HiWord1 = (0x1234CDEF >> 16) & 0xFFFF;', - 'this.LoWord2 = -0x1234CDEF & 0xFFFF;', - 'this.HiWord2 = (-0x1234CDEF >> 16) & 0xFFFF;', + 'this.LoWord2 = -0x1234CDEF >>> 0;', + 'this.HiWord2 = Math.floor(-0x1234CDEF / 4294967296) >>> 0;', 'this.lo4 = 0x34 & 0xF;', 'this.hi4 = (0x34 >> 4) & 0xF;', 'this.lo5 = (((-0x34 & 255) << 24) >> 24) & 0xFF;', @@ -7463,6 +7464,106 @@ begin ''])); end; +procedure TTestModule.TestInteger_AssignOutsideConst; +begin + StartProgram(false); + Add([ + 'const', + ' MinInt = low(longint);', + ' MaxInt = high(longint);', + 'type', + ' {#TMyInt}TMyInt = MinInt..MaxInt;', + 'var', + ' i: TMyInt;', + ' aByte: byte;', + ' aShortInt: shortint;', + ' aWord: word;', + ' aSmallInt: smallint;', + ' aLongWord: longword;', + ' aLongInt: longint;', + ' aNativeInt: nativeint;', + ' aNativeUInt: nativeuint;', + 'begin', + ' aByte:=$FF;', + ' aByte:=$100;', + ' aByte:=-1;', + ' aByte:=-127;', + ' aByte:=-128;', + ' aByte:=-254;', + ' aByte:=-255;', + ' aByte:=-256;', + ' aShortInt:=127;', + ' aShortInt:=128;', + ' aShortInt:=-128;', + ' aShortInt:=-129;', + ' aWord:=$ffff;', + ' aWord:=$10000;', + ' aWord:=-1;', + ' aWord:=-$ffff;', + ' aWord:=-$10000;', + ' aWord:=-$10001;', + ' aSmallInt:=$7fff;', + ' aSmallInt:=$8000;', + ' aSmallInt:=-$8000;', + ' aSmallInt:=-$8001;', + ' aLongWord:=$ffffffff;', + ' aLongWord:=$100000000;', + ' aLongWord:=-1;', + ' aLongWord:=-$ffffffff;', + ' aNativeInt:=$1fffffffffffff;', + ' aNativeInt:=-$1fffffffffffff;', + ' aNativeUInt:=$1fffffffffffff;', + ' aNativeUInt:=-$1fffffffffffff;', + '']); + ConvertProgram; + CheckSource('TestInteger_AssignOutsideConst', + LinesToStr([ + 'this.MinInt = -2147483648;', + 'this.MaxInt = 2147483647;', + 'this.i = 0;', + 'this.aByte = 0;', + 'this.aShortInt = 0;', + 'this.aWord = 0;', + 'this.aSmallInt = 0;', + 'this.aLongWord = 0;', + 'this.aLongInt = 0;', + 'this.aNativeInt = 0;', + 'this.aNativeUInt = 0;', + '']), + LinesToStr([ + '$mod.aByte = 0xFF;', + '$mod.aByte = 0;', + '$mod.aByte = 255;', + '$mod.aByte = 129;', + '$mod.aByte = 128;', + '$mod.aByte = 2;', + '$mod.aByte = 1;', + '$mod.aByte = 0;', + '$mod.aShortInt = 127;', + '$mod.aShortInt = -128;', + '$mod.aShortInt = -128;', + '$mod.aShortInt = 127;', + '$mod.aWord = 0xffff;', + '$mod.aWord = 0;', + '$mod.aWord = 65535;', + '$mod.aWord = 1;', + '$mod.aWord = 0;', + '$mod.aWord = 65535;', + '$mod.aSmallInt = 0x7fff;', + '$mod.aSmallInt = -32768;', + '$mod.aSmallInt = -0x8000;', + '$mod.aSmallInt = 32767;', + '$mod.aLongWord = 0xffffffff;', + '$mod.aLongWord = 0;', + '$mod.aLongWord = 4294967295;', + '$mod.aLongWord = 1;', + '$mod.aNativeInt = 0x1fffffffffffff;', + '$mod.aNativeInt = -0x1fffffffffffff;', + '$mod.aNativeUInt = 0x1fffffffffffff;', + '$mod.aNativeUInt = 1;', + ''])); +end; + procedure TTestModule.TestCurrency; begin StartProgram(false); From 3e3f99c328be386e9cf6b7f2cceaab9c5283873e Mon Sep 17 00:00:00 2001 From: florian Date: Wed, 18 Aug 2021 10:34:08 +0200 Subject: [PATCH 076/116] * properly check if -unpushed should be appended in revision.inc --- compiler/Makefile | 2 +- compiler/Makefile.fpc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index a11a367b34..2cb7ce56d9 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -575,7 +575,7 @@ ifneq ($(wildcard ../.git),) ifneq ($(GIT),) GITDESCRIBE=$(shell $(GIT) describe --dirty) REVSTR:=$(word 2,$(subst -, ,$(GITDESCRIBE)))-$(word 3,$(subst -, ,$(GITDESCRIBE))) -ifneq (git log @{u}..,) +ifneq ($(shell $(GIT) log @{u}..),) REVSTR:=$(REVSTR)-unpushed endif ifneq ($(word 4,$(subst -, ,$(GITDESCRIBE))),) diff --git a/compiler/Makefile.fpc b/compiler/Makefile.fpc index dbff3e1b8b..c5b4d21b77 100644 --- a/compiler/Makefile.fpc +++ b/compiler/Makefile.fpc @@ -315,7 +315,7 @@ ifneq ($(wildcard ../.git),) ifneq ($(GIT),) GITDESCRIBE=$(shell $(GIT) describe --dirty) REVSTR:=$(word 2,$(subst -, ,$(GITDESCRIBE)))-$(word 3,$(subst -, ,$(GITDESCRIBE))) -ifneq (git log @{u}..,) +ifneq ($(shell $(GIT) log @{u}..),) REVSTR:=$(REVSTR)-unpushed endif ifneq ($(word 4,$(subst -, ,$(GITDESCRIBE))),) From 3da7d62b1a0ff2cb766cd22247f45fced8792897 Mon Sep 17 00:00:00 2001 From: Pierre Muller Date: Wed, 18 Aug 2021 12:00:07 +0200 Subject: [PATCH 077/116] Add support for hash generation for git repository (local modifier not implemented) --- tests/Makefile | 13 ++++++++++++- tests/Makefile.fpc | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/tests/Makefile b/tests/Makefile index 5e714a34b7..470b8f4b73 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -2756,12 +2756,23 @@ distclean: clean fpc_distclean digest : utils -$(DIGEST) $(LOG) SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) +GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) +ifneq ($(wildcard ../.git),) +ifneq ($(GIT),) +GIT_GET_HASH=$(GIT) log -1 --format=%h +SVN_TESTS_REV_STR=$(shell $(GIT_GET_HASH) .) +SVN_COMPILER_REV_STR=$(shell $(GIT_GET_HASH) ../compiler) +SVN_RTL_REV_STR=$(shell $(GIT_GET_HASH) ../rtl) +SVN_PACKAGES_REV_STR=$(shell $(GIT_GET_HASH) ../packages) +else ifneq ($(SVNVERSION),) SVN_TESTS_REV_STR=$(shell $(SVNVERSION) -c .) SVN_COMPILER_REV_STR=$(shell $(SVNVERSION) -c ../compiler) SVN_RTL_REV_STR=$(shell $(SVNVERSION) -c ../rtl) SVN_PACKAGES_REV_STR=$(shell $(SVNVERSION) -c ../packages) endif +endif +endif ifeq ($(TEST_COMMENT),) TEST_COMMENT=$(TEST_OPT) endif @@ -2785,7 +2796,7 @@ endif ifneq ($(TEST_FPC_FULLVERSION),) $(ECHOREDIR) CompilerFullVersion=$(TEST_FPC_FULLVERSION) >> $(TEST_OUTPUTDIR)/dbdigest.cfg endif -ifneq ($(SVNVERSION),) +ifneq ($(SVN_TESTS_REV_STR),) $(ECHOREDIR) svntestsrevision=$(SVN_TESTS_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg $(ECHOREDIR) svncompilerrevision=$(SVN_COMPILER_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg $(ECHOREDIR) svnrtlrevision=$(SVN_RTL_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg diff --git a/tests/Makefile.fpc b/tests/Makefile.fpc index 4d15c48be5..61fe423b44 100644 --- a/tests/Makefile.fpc +++ b/tests/Makefile.fpc @@ -620,12 +620,23 @@ digest : utils SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) +GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) +ifneq ($(wildcard ../.git),) +ifneq ($(GIT),) +GIT_GET_HASH=$(GIT) log -1 --format=%h +SVN_TESTS_REV_STR=$(shell $(GIT_GET_HASH) .) +SVN_COMPILER_REV_STR=$(shell $(GIT_GET_HASH) ../compiler) +SVN_RTL_REV_STR=$(shell $(GIT_GET_HASH) ../rtl) +SVN_PACKAGES_REV_STR=$(shell $(GIT_GET_HASH) ../packages) +else ifneq ($(SVNVERSION),) SVN_TESTS_REV_STR=$(shell $(SVNVERSION) -c .) SVN_COMPILER_REV_STR=$(shell $(SVNVERSION) -c ../compiler) SVN_RTL_REV_STR=$(shell $(SVNVERSION) -c ../rtl) SVN_PACKAGES_REV_STR=$(shell $(SVNVERSION) -c ../packages) endif +endif +endif ifeq ($(TEST_COMMENT),) TEST_COMMENT=$(TEST_OPT) @@ -651,7 +662,7 @@ endif ifneq ($(TEST_FPC_FULLVERSION),) $(ECHOREDIR) CompilerFullVersion=$(TEST_FPC_FULLVERSION) >> $(TEST_OUTPUTDIR)/dbdigest.cfg endif -ifneq ($(SVNVERSION),) +ifneq ($(SVN_TESTS_REV_STR),) $(ECHOREDIR) svntestsrevision=$(SVN_TESTS_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg $(ECHOREDIR) svncompilerrevision=$(SVN_COMPILER_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg $(ECHOREDIR) svnrtlrevision=$(SVN_RTL_REV_STR) >> $(TEST_OUTPUTDIR)/dbdigest.cfg From a4878d892ce392fb3ede434650d246c63e6f4dd6 Mon Sep 17 00:00:00 2001 From: florian Date: Wed, 18 Aug 2021 15:16:51 +0200 Subject: [PATCH 078/116] * always use $(GIT) to call git --- compiler/Makefile | 6 +++--- compiler/Makefile.fpc | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index 2cb7ce56d9..449651f947 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -451,13 +451,15 @@ endif ifndef RTLOPT RTLOPT:=$(OPT) endif +SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) +GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) DATE_FMT = +%Y/%m/%d ifdef SOURCE_DATE_EPOCH COMPDATESTR ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u -r "$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u "$(DATE_FMT)") else GIT_DIR = $(wildcard ../.git) ifneq ($(GIT_DIR),) - COMPDATESTR:=$(shell git log -1 --pretty=%cd --date=format:'%Y/%m/%d') + COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') endif endif ifdef COMPDATESTR @@ -557,8 +559,6 @@ CPUSUF=wasm32 endif NOCPUDEF=1 MSGFILE=msg/error$(FPCLANG).msg -SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) -GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) PPUDUMPPROG:=$(firstword $(strip $(wildcard $(addsuffix /ppudump$(SRCEXEEXT),$(SEARCHPATH))))) ifndef PPUDUMP ifdef PPUDUMPPROG diff --git a/compiler/Makefile.fpc b/compiler/Makefile.fpc index c5b4d21b77..506e575265 100644 --- a/compiler/Makefile.fpc +++ b/compiler/Makefile.fpc @@ -168,6 +168,9 @@ ifndef RTLOPT RTLOPT:=$(OPT) endif +SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) +GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) + DATE_FMT = +%Y/%m/%d ifdef SOURCE_DATE_EPOCH COMPDATESTR ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u -r "$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u "$(DATE_FMT)") @@ -176,7 +179,7 @@ else GIT_DIR = $(wildcard ../.git) ifneq ($(GIT_DIR),) # ... then take date from head - COMPDATESTR:=$(shell git log -1 --pretty=%cd --date=format:'%Y/%m/%d') + COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') endif endif @@ -290,9 +293,6 @@ NOCPUDEF=1 # Default message file MSGFILE=msg/error$(FPCLANG).msg - -SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) -GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) PPUDUMPPROG:=$(firstword $(strip $(wildcard $(addsuffix /ppudump$(SRCEXEEXT),$(SEARCHPATH))))) ifndef PPUDUMP ifdef PPUDUMPPROG From aa9ff6c225997c84ded257d33219b60374470786 Mon Sep 17 00:00:00 2001 From: mattias Date: Wed, 18 Aug 2021 16:03:32 +0200 Subject: [PATCH 079/116] fcl-json: fixed testjson.lpi --- packages/fcl-json/tests/testjson.lpi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/packages/fcl-json/tests/testjson.lpi b/packages/fcl-json/tests/testjson.lpi index bd4363525e..928cf4d09b 100644 --- a/packages/fcl-json/tests/testjson.lpi +++ b/packages/fcl-json/tests/testjson.lpi @@ -1,6 +1,6 @@ - + @@ -13,19 +13,23 @@ - + + + + + - + @@ -53,11 +57,11 @@ - + - + From f6636c9c1c447ce1a2018b3389257c7bc0870a74 Mon Sep 17 00:00:00 2001 From: Don Date: Thu, 19 Aug 2021 07:51:36 +0100 Subject: [PATCH 080/116] Allow custom definition of GIT. --- compiler/Makefile | 2 ++ compiler/Makefile.fpc | 3 +++ 2 files changed, 5 insertions(+) diff --git a/compiler/Makefile b/compiler/Makefile index 449651f947..cca7cd59c9 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -452,7 +452,9 @@ ifndef RTLOPT RTLOPT:=$(OPT) endif SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) +ifndef GIT GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) +endif DATE_FMT = +%Y/%m/%d ifdef SOURCE_DATE_EPOCH COMPDATESTR ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u -r "$(SOURCE_DATE_EPOCH)" "$(DATE_FMT)" 2>/dev/null || date -u "$(DATE_FMT)") diff --git a/compiler/Makefile.fpc b/compiler/Makefile.fpc index 506e575265..672c5eda5e 100644 --- a/compiler/Makefile.fpc +++ b/compiler/Makefile.fpc @@ -169,7 +169,10 @@ RTLOPT:=$(OPT) endif SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH)))) + +ifndef GIT GIT:=$(firstword $(wildcard $(addsuffix /git$(SRCEXEEXT),$(SEARCHPATH)))) +endif DATE_FMT = +%Y/%m/%d ifdef SOURCE_DATE_EPOCH From a45123a87b2b5440928e4bcd053a9b784534816d Mon Sep 17 00:00:00 2001 From: florian Date: Thu, 19 Aug 2021 23:01:00 +0200 Subject: [PATCH 081/116] * fix change information for popcnt --- compiler/i386/i386prop.inc | 2 +- compiler/i8086/i8086prop.inc | 2 +- compiler/x86/x86ins.dat | 2 +- compiler/x86_64/x8664pro.inc | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/i386/i386prop.inc b/compiler/i386/i386prop.inc index dc0d1b4b7e..599c1fcc81 100644 --- a/compiler/i386/i386prop.inc +++ b/compiler/i386/i386prop.inc @@ -676,7 +676,7 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_All]), +(Ch: [Ch_Wop2, Ch_Rop1]), (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), diff --git a/compiler/i8086/i8086prop.inc b/compiler/i8086/i8086prop.inc index 462246df63..45a0a311de 100644 --- a/compiler/i8086/i8086prop.inc +++ b/compiler/i8086/i8086prop.inc @@ -676,7 +676,7 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_All]), +(Ch: [Ch_Wop2, Ch_Rop1]), (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index eda4711ffc..20971be3d7 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -3526,7 +3526,7 @@ xmmreg,xmmrm,imm \361\3\x0F\x3A\x62\110\26 SSE42,SM2,SB,AR2 xmmreg,xmmrm \361\3\x0F\x38\x37\110 SSE42,SM [POPCNT,popcntX] -(Ch_All) +(Ch_Wop2, Ch_Rop1) reg16,rm16 \333\320\2\x0F\xB8\110 386,SM,SSE4 reg32,rm32 \333\320\2\x0F\xB8\110 386,SM,SSE4 reg64,rm64 \333\320\2\x0F\xB8\110 386,SM,SSE4,X86_64 diff --git a/compiler/x86_64/x8664pro.inc b/compiler/x86_64/x8664pro.inc index 70778b7240..926b506f8e 100644 --- a/compiler/x86_64/x8664pro.inc +++ b/compiler/x86_64/x8664pro.inc @@ -669,7 +669,7 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_All]), +(Ch: [Ch_Wop2, Ch_Rop1]), (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), From 9700c036997d0652210a6e29bf4514febc5084f5 Mon Sep 17 00:00:00 2001 From: Pierre Muller Date: Fri, 20 Aug 2021 21:16:48 +0000 Subject: [PATCH 082/116] Add several pattern from tests sub-directory to ignore list (cherry picked from commit a837c8d47a93f1f1c73a6c45b837f49d9d040c30) --- .gitignore | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/.gitignore b/.gitignore index 5f7cd3249d..673a3ec326 100644 --- a/.gitignore +++ b/.gitignore @@ -59,8 +59,19 @@ a.out /packages/fpmkunit/units_bs /utils/fpmake units +/tests/createlst +/tests/gparmake /tests/output +/tests/output* !/tests/test/units +/tests/tstunits/tmp/ +/tests/tstunits/*-*/ +/tests/utils/concat +/tests/utils/digest +/tests/utils/dotest +/tests/utils/fail +/tests/utils/fptime +/tests/utils/testfail bin/ fpmake packages/fcl-db/tests/database.ini From 61a3f6603d2fac4f4b88cabb5c1ab1361bf6429b Mon Sep 17 00:00:00 2001 From: florian Date: Fri, 20 Aug 2021 23:54:49 +0200 Subject: [PATCH 083/116] * change information for round* fixed --- compiler/i386/i386prop.inc | 8 ++++---- compiler/i8086/i8086prop.inc | 8 ++++---- compiler/x86/x86ins.dat | 8 ++++---- compiler/x86_64/x8664pro.inc | 8 ++++---- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/compiler/i386/i386prop.inc b/compiler/i386/i386prop.inc index 599c1fcc81..febdcab4ad 100644 --- a/compiler/i386/i386prop.inc +++ b/compiler/i386/i386prop.inc @@ -666,10 +666,10 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), (Ch: [Ch_Mop1, Ch_Rop2]), (Ch: [Ch_All]), (Ch: [Ch_All]), diff --git a/compiler/i8086/i8086prop.inc b/compiler/i8086/i8086prop.inc index 45a0a311de..16d0079520 100644 --- a/compiler/i8086/i8086prop.inc +++ b/compiler/i8086/i8086prop.inc @@ -666,10 +666,10 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), (Ch: [Ch_Mop1, Ch_Rop2]), (Ch: [Ch_All]), (Ch: [Ch_All]), diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat index 20971be3d7..e35ac7286e 100644 --- a/compiler/x86/x86ins.dat +++ b/compiler/x86/x86ins.dat @@ -3479,19 +3479,19 @@ xmmreg,xmmrm \361\3\x0F\x38\x40\110 SSE41,SM xmmreg,xmmrm \361\3\x0F\x38\x17\110 SSE41,SM [ROUNDPS] -(Ch_Wop2, Ch_Rop1) +(Ch_Wop3, Ch_Rop2) xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE41,SM2,SB,AR2 [ROUNDPD] -(Ch_Wop2, Ch_Rop1) +(Ch_Wop3, Ch_Rop2) xmmreg,xmmrm,imm \361\3\x0F\x3A\x09\110\26 SSE41,SM2,SB,AR2 [ROUNDSS] -(Ch_Wop2, Ch_Rop1) +(Ch_Wop3, Ch_Rop2) xmmreg,xmmrm,imm \336\361\3\x0F\x3A\x0A\110\26 SSE41,SM2,SB,AR2 [ROUNDSD] -(Ch_Wop2, Ch_Rop1) +(Ch_Wop3, Ch_Rop2) xmmreg,xmmrm,imm \337\361\3\x0F\x3A\x0B\110\26 SSE41,SM2,SB,AR2 ;******************************************************************************* diff --git a/compiler/x86_64/x8664pro.inc b/compiler/x86_64/x8664pro.inc index 926b506f8e..2ea9269819 100644 --- a/compiler/x86_64/x8664pro.inc +++ b/compiler/x86_64/x8664pro.inc @@ -659,10 +659,10 @@ (Ch: [Ch_All]), (Ch: [Ch_All]), (Ch: [Ch_All]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), -(Ch: [Ch_Wop2, Ch_Rop1]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), +(Ch: [Ch_Wop3, Ch_Rop2]), (Ch: [Ch_Mop1, Ch_Rop2]), (Ch: [Ch_All]), (Ch: [Ch_All]), From 7b6f273023059d3a905fd35897f2db9eb5bf46d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Van=20Canneyt?= Date: Sat, 21 Aug 2021 09:05:23 +0200 Subject: [PATCH 084/116] * Remove spurious var, prevents fpdoc from handling record --- rtl/objpas/types.pp | 1 - 1 file changed, 1 deletion(-) diff --git a/rtl/objpas/types.pp b/rtl/objpas/types.pp index dd0d7cbceb..2d0e4733a9 100644 --- a/rtl/objpas/types.pp +++ b/rtl/objpas/types.pp @@ -174,7 +174,6 @@ type public Type TSingle3Array = array[0..2] of single; - var constructor Create(const ax,ay,az:single); procedure Offset(const adeltax,adeltay,adeltaz:single); inline; procedure Offset(const adelta:TPoint3D); inline; From 06d99b1e6822a8c8cbf63b0af2b820068feb530b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Van=20Canneyt?= Date: Sat, 21 Aug 2021 09:05:57 +0200 Subject: [PATCH 085/116] * Remove unneeded diagnostic output --- utils/fpdoc/dw_html.pp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/utils/fpdoc/dw_html.pp b/utils/fpdoc/dw_html.pp index b8afe2be7d..e8fb2a047f 100644 --- a/utils/fpdoc/dw_html.pp +++ b/utils/fpdoc/dw_html.pp @@ -1,3 +1,4 @@ + { FPDoc - Free Pascal Documentation Tool Copyright (C) 2000 - 2005 by @@ -1809,9 +1810,7 @@ begin CodeEl := CreateCode(CreatePara(TDEl)); AppendKw(CodeEl, 'type'); - if not Assigned(AClass.GenericTemplateTypes) then - Dolog('ERROR generic init: %s', [AClass.name]); - if AClass.GenericTemplateTypes.Count>0 then + if Assigned(AClass.GenericTemplateTypes) and AClass.GenericTemplateTypes.Count>0 then AppendGeneric(CodeEl, AClass) else AppendText(CodeEl, ' ' + UTF8Decode(AClass.Name) + ' '); @@ -1827,8 +1826,8 @@ begin ThisTreeNode := TreeInterface.GetPasElNode(AClass) else ThisTreeNode := TreeClass.GetPasElNode(AClass); - if not Assigned(ThisTreeNode) Then - DoLog('ERROR Tree Class information: '+ThisClass.PathName); + //if not Assigned(ThisTreeNode) Then + // DoLog('ERROR Tree Class information: '+ThisClass.PathName); if Assigned(AClass.AncestorType) then begin From f069f272670ebc7579e80238ab10a55e37bc3b8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Van=20Canneyt?= Date: Sat, 21 Aug 2021 09:11:24 +0200 Subject: [PATCH 086/116] * fix compilation --- rtl/objpas/types.pp | 1 + 1 file changed, 1 insertion(+) diff --git a/rtl/objpas/types.pp b/rtl/objpas/types.pp index 2d0e4733a9..d2e9367b3b 100644 --- a/rtl/objpas/types.pp +++ b/rtl/objpas/types.pp @@ -177,6 +177,7 @@ type constructor Create(const ax,ay,az:single); procedure Offset(const adeltax,adeltay,adeltaz:single); inline; procedure Offset(const adelta:TPoint3D); inline; + public case Integer of 0: (data:TSingle3Array); 1: (x,y,z : single); From f138af02b9b67d26c31bdf1c5ce4bdd19a359dd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Van=20Canneyt?= Date: Sat, 21 Aug 2021 09:13:06 +0200 Subject: [PATCH 087/116] * Fix by Mark Paley to add IfThen for StringList and TStringDynArray. Issue #39314 --- packages/rtl-objpas/src/inc/strutils.pp | 10 ++++++++++ rtl/objpas/classes/classes.inc | 9 +++++++++ rtl/objpas/classes/classesh.inc | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/packages/rtl-objpas/src/inc/strutils.pp b/packages/rtl-objpas/src/inc/strutils.pp index 6e21eca548..9fb91795d9 100644 --- a/packages/rtl-objpas/src/inc/strutils.pp +++ b/packages/rtl-objpas/src/inc/strutils.pp @@ -74,6 +74,7 @@ Function AnsiReverseString(const AText: AnsiString): AnsiString;inline; Function StuffString(const AText: string; AStart, ALength: Cardinal; const ASubText: string): string; Function RandomFrom(const AValues: array of string): string; overload; Function IfThen(AValue: Boolean; const ATrue: string; const AFalse: string = ''): string; overload; +Function IfThen(AValue: Boolean; const ATrue: TStringDynArray; const AFalse: TStringDynArray = nil): TStringDynArray; overload; function NaturalCompareText (const S1 , S2 : string ): Integer ; function NaturalCompareText(const Str1, Str2: string; const ADecSeparator, AThousandSeparator: Char): Integer; @@ -1227,6 +1228,15 @@ begin result:=afalse; end; +Function IfThen(AValue: Boolean; const ATrue: TStringDynArray; const AFalse: TStringDynArray = nil): TStringDynArray; overload; + +begin + if avalue then + result:=atrue + else + result:=afalse; +end; + function NaturalCompareText(const Str1, Str2: string; const ADecSeparator, AThousandSeparator: Char): Integer; { NaturalCompareBase compares strings in a collated order and diff --git a/rtl/objpas/classes/classes.inc b/rtl/objpas/classes/classes.inc index 97eb5d4dbb..e6519cd9b9 100644 --- a/rtl/objpas/classes/classes.inc +++ b/rtl/objpas/classes/classes.inc @@ -2459,6 +2459,15 @@ end; { Utility routines } + +Function IfThen(AValue: Boolean; const ATrue: TStringList; const AFalse: TStringList = nil): TStringList; overload; +begin + if avalue then + result:=atrue + else + result:=afalse; +end; + function LineStart(Buffer, BufPos: PChar): PChar; begin diff --git a/rtl/objpas/classes/classesh.inc b/rtl/objpas/classes/classesh.inc index b4df19c840..d03cca3428 100644 --- a/rtl/objpas/classes/classesh.inc +++ b/rtl/objpas/classes/classesh.inc @@ -2469,4 +2469,4 @@ function LineStart(Buffer, BufPos: PChar): PChar; procedure BinToHex(BinValue, HexValue: PChar; BinBufSize: Integer); deprecated 'use procedures from unit StrUtils'; function HexToBin(HexValue, BinValue: PChar; BinBufSize: Integer): Integer; function ExtractStrings(Separators, WhiteSpace: TSysCharSet; Content: PChar; Strings: TStrings; AddEmptyStrings : Boolean = False): Integer; - +Function IfThen(AValue: Boolean; const ATrue: TStringList; const AFalse: TStringList = nil): TStringList; overload; From 6c8b7577958cb4d7589ecaf9705a4568e24c7656 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Van=20Canneyt?= Date: Sat, 21 Aug 2021 09:20:50 +0200 Subject: [PATCH 088/116] * Fix compation --- utils/fpdoc/dw_html.pp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/utils/fpdoc/dw_html.pp b/utils/fpdoc/dw_html.pp index e8fb2a047f..5f1497abca 100644 --- a/utils/fpdoc/dw_html.pp +++ b/utils/fpdoc/dw_html.pp @@ -1,4 +1,3 @@ - { FPDoc - Free Pascal Documentation Tool Copyright (C) 2000 - 2005 by @@ -1810,7 +1809,7 @@ begin CodeEl := CreateCode(CreatePara(TDEl)); AppendKw(CodeEl, 'type'); - if Assigned(AClass.GenericTemplateTypes) and AClass.GenericTemplateTypes.Count>0 then + if Assigned(AClass.GenericTemplateTypes) and (AClass.GenericTemplateTypes.Count>0) then AppendGeneric(CodeEl, AClass) else AppendText(CodeEl, ' ' + UTF8Decode(AClass.Name) + ' '); From a77f5221f341b32bb964c03dc61c1e80b71714dd Mon Sep 17 00:00:00 2001 From: florian Date: Sat, 21 Aug 2021 20:36:29 +0200 Subject: [PATCH 089/116] * check if git executable really exists --- compiler/Makefile | 4 +++- compiler/Makefile.fpc | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index cca7cd59c9..b92aa735ae 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -461,7 +461,9 @@ ifdef SOURCE_DATE_EPOCH else GIT_DIR = $(wildcard ../.git) ifneq ($(GIT_DIR),) - COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') + ifneq ($(GIT),) + COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') + endif endif endif ifdef COMPDATESTR diff --git a/compiler/Makefile.fpc b/compiler/Makefile.fpc index 672c5eda5e..a6810b88dc 100644 --- a/compiler/Makefile.fpc +++ b/compiler/Makefile.fpc @@ -182,7 +182,9 @@ else GIT_DIR = $(wildcard ../.git) ifneq ($(GIT_DIR),) # ... then take date from head - COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') + ifneq ($(GIT),) + COMPDATESTR:=$(shell $(GIT) log -1 --pretty=%cd --date=format:'%Y/%m/%d') + endif endif endif From a73ee4f403dc037bdc0d45e2ae793f55f994771a Mon Sep 17 00:00:00 2001 From: Jonas Maebe Date: Sun, 22 Aug 2021 14:56:19 +0000 Subject: [PATCH 090/116] Solves #39296: x86-64 parameter zero/sign extension --- compiler/x86_64/cpupara.pas | 53 ++++++++++++++++++++++++++++++------- tests/webtbs/tw39296.pp | 26 ++++++++++++++++++ 2 files changed, 70 insertions(+), 9 deletions(-) create mode 100644 tests/webtbs/tw39296.pp diff --git a/compiler/x86_64/cpupara.pas b/compiler/x86_64/cpupara.pas index b35b0a2331..734e7f884a 100644 --- a/compiler/x86_64/cpupara.pas +++ b/compiler/x86_64/cpupara.pas @@ -176,15 +176,13 @@ unit cpupara; if size<=4 then begin cl.typ:=X86_64_INTEGERSI_CLASS; - { gcc/clang sign/zero-extend all values to 32 bits, except for - _Bool (= Pascal boolean), which is only zero-extended to 8 bits - as per the x86-64 ABI -> do the same - - some testing showed, that this is not true for 8 bit values: - in case of an 8 bit value, it is not zero/sign extended } + { The ABI does not require any sign/zero extension for parameters, + except for _Bool (= Pascal boolean) to 8 bits. However, some + compilers (clang) extend them to 32 bits anyway and rely on it + -> also do it for compatibility when calling such code } if not assigned(cl.def) or - not(cl.def.typ=orddef) or - not(torddef(cl.def).ordtype in [uchar,u8bit,s8bit,pasbool1]) then + (cl.def.typ<>orddef) or + (torddef(cl.def).ordtype<>pasbool1) then cl.def:=u32inttype; end else @@ -1489,7 +1487,20 @@ unit cpupara; end else if result.intsize in [1,2,4] then begin - paraloc^.size:=def_cgsize(paraloc^.def); + { The ABI does not require sign/zero-extended function + results, but older versions of clang did so and + on Darwin current versions of clang keep doing so + for backward compatibility. On other platforms, it + doesn't and hence we don't either } + if (i=0) and + not(target_info.system in systems_darwin) and + (result.intsize in [1,2]) then + begin + paraloc^.size:=int_cgsize(result.intsize); + paraloc^.def:=cgsize_orddef(paraloc^.size); + end + else + paraloc^.size:=def_cgsize(paraloc^.def); end else begin @@ -1785,6 +1796,30 @@ unit cpupara; end else begin + { some compilers sign/zero-extend on the callerside, + others don't. To be compatible with both, FPC + extends on the callerside, and assumes no + extension has been performed on the calleeside. + This is less efficient, but the alternative is + occasional crashes when calling code generated + by certain other compilers, or being called from + code generated by other compilers. + + Exception: Darwin, since everyone there needs to + be compatible with the system compiler clang + (which extends on the caller side). + + Not for LLVM, since there the zero/signext + attributes by definition only apply to the + caller side } +{$ifndef LLVM} + if not(target_info.system in systems_darwin) and + (side=calleeside) and + (hp.paraloc[side].intsize in [1,2]) then + begin + paraloc^.def:=hp.paraloc[side].def + end; +{$endif not LLVM} paraloc^.size:=def_cgsize(paraloc^.def); { s64comp is pushed in an int register } if paraloc^.size=OS_C64 then diff --git a/tests/webtbs/tw39296.pp b/tests/webtbs/tw39296.pp new file mode 100644 index 0000000000..1e854d2128 --- /dev/null +++ b/tests/webtbs/tw39296.pp @@ -0,0 +1,26 @@ +{ %cpu=x86_64 } +{ %skiptarget=win64 } + +function bytepara(b: byte; s: shortint): boolean; assembler; nostackframe; +asm + xorl %eax, %eax + cmpl $5, %edi + seteb %al + cmpl $-3, %esi + seteb %dl + andb %dl, %al +end; + +var + b1: byte; + s1: shortint; +begin + b1:=5; + s1:=-3; + asm + movl $0x12345678, %edi + movl $0xabcdef01, %esi + end ['rsi', 'rdi']; + if not bytepara(b1,s1) then + halt(1); +end. From 0558fefc5179a79f11240d503789e3e538162a6a Mon Sep 17 00:00:00 2001 From: pierre Date: Fri, 22 Jan 2021 12:51:53 +0000 Subject: [PATCH 091/116] Avoid range check errors (cherry picked from commit 1351ccb3bfe6adad6be0246acb7645203df8b3b0) # Conflicts: # .gitattributes --- tests/bench/bcase.pp | 5328 +++++++++++++++++++++--------------------- 1 file changed, 2667 insertions(+), 2661 deletions(-) diff --git a/tests/bench/bcase.pp b/tests/bench/bcase.pp index effd8b1880..c37c342f3d 100644 --- a/tests/bench/bcase.pp +++ b/tests/bench/bcase.pp @@ -1,2661 +1,2667 @@ -{$goto on} -program bcase; - -{$mode objfpc}{$H+} - -uses - SysUtils; - -{ Utility functions } -function GetRealTime(const st: TSystemTime): Real; - begin - Result := st.Hour*3600.0 + st.Minute*60.0 + st.Second + st.MilliSecond/1000.0; - end; - -{$push} -{$warn 5057 off} -function GetRealTime : Real; - var - st:TSystemTime; - begin - GetLocalTime(st); - result:=GetRealTime(st); - end; -{$pop} - -function IIf(Condition: Boolean; TrueRes, FalseRes: Integer): Integer; inline; - begin - if Condition then - Result := TrueRes - else - Result := FalseRes; - end; - -const - ITERATIONS = 33554432; - - AES_S_Box: array[Byte] of Byte = ( - $63, $7c, $77, $7b, $f2, $6b, $6f, $c5, $30, $01, $67, $2b, $fe, $d7, $ab, $76, - $ca, $82, $c9, $7d, $fa, $59, $47, $f0, $ad, $d4, $a2, $af, $9c, $a4, $72, $c0, - $b7, $fd, $93, $26, $36, $3f, $f7, $cc, $34, $a5, $e5, $f1, $71, $d8, $31, $15, - $04, $c7, $23, $c3, $18, $96, $05, $9a, $07, $12, $80, $e2, $eb, $27, $b2, $75, - $09, $83, $2c, $1a, $1b, $6e, $5a, $a0, $52, $3b, $d6, $b3, $29, $e3, $2f, $84, - $53, $d1, $00, $ed, $20, $fc, $b1, $5b, $6a, $cb, $be, $39, $4a, $4c, $58, $cf, - $d0, $ef, $aa, $fb, $43, $4d, $33, $85, $45, $f9, $02, $7f, $50, $3c, $9f, $a8, - $51, $a3, $40, $8f, $92, $9d, $38, $f5, $bc, $b6, $da, $21, $10, $ff, $f3, $d2, - $cd, $0c, $13, $ec, $5f, $97, $44, $17, $c4, $a7, $7e, $3d, $64, $5d, $19, $73, - $60, $81, $4f, $dc, $22, $2a, $90, $88, $46, $ee, $b8, $14, $de, $5e, $0b, $db, - $e0, $32, $3a, $0a, $49, $06, $24, $5c, $c2, $d3, $ac, $62, $91, $95, $e4, $79, - $e7, $c8, $37, $6d, $8d, $d5, $4e, $a9, $6c, $56, $f4, $ea, $65, $7a, $ae, $08, - $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, - $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, - $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, - $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 - ); - - FirstWeighted: array[0..255] of Byte = ( - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, - $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, - $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, - $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, - $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 - ); - - LastWeighted: array[0..255] of Byte = ( - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, - $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, - $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, - $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, - $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 - ); - - AlmostFullExpected: array[0..255] of Byte = ( - $63, $7c, $77, $7b, $f2, $6b, $6f, $c5, $30, $01, $67, $2b, $fe, $d7, $ab, $76, - $ca, $82, $c9, $7d, $fa, $59, $47, $f0, $ad, $d4, $a2, $af, $9c, $a4, $72, $c0, - $b7, $fd, $93, $26, $36, $3f, $f7, $cc, $34, $a5, $e5, $f1, $71, $d8, $31, $15, - $04, $c7, $23, $c3, $18, $96, $05, $9a, $07, $12, $80, $e2, $eb, $27, $b2, $75, - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, - $d0, $ef, $aa, $fb, $43, $4d, $33, $85, $45, $f9, $02, $7f, $50, $3c, $9f, $a8, - $51, $a3, $40, $8f, $92, $9d, $38, $f5, $bc, $b6, $da, $21, $10, $ff, $f3, $d2, - $cd, $0c, $13, $ec, $5f, $97, $44, $17, $c4, $a7, $7e, $3d, $64, $5d, $19, $73, - $60, $81, $4f, $dc, $22, $2a, $90, $88, $46, $ee, $b8, $14, $de, $5e, $0b, $db, - $e0, $32, $3a, $0a, $49, $06, $24, $5c, $c2, $d3, $ac, $62, $91, $95, $e4, $79, - $e7, $c8, $37, $6d, $8d, $d5, $4e, $a9, $6c, $56, $f4, $ea, $65, $7a, $ae, $08, - $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, - $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, - $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, - $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 - ); - -type - TInstructionSet = ( { Truncated to 1024 entries } - A_NONE = -512, A_ADC, A_ADD, A_AND, A_BSF, A_BSR, A_BSWAP, A_BT, A_BTC, A_BTR, A_BTS, - A_CALL, A_CBW, A_CDQ, A_CLC, A_CLD, A_CLI, A_CLTS, A_CMC, A_CMP, A_CMPSB, - A_CMPSD, A_CMPSW, A_CMPXCHG, A_CMPXCHG486, A_CMPXCHG8B, A_CPUID, A_CWD, A_CWDE, - A_DEC, A_DIV, A_EMMS, A_ENTER, A_F2XM1, A_FABS, A_FADD, A_FADDP, A_FBLD, A_FBSTP, - A_FCHS, A_FCLEX,A_FCMOVB, A_FCMOVBE, A_FCMOVE, A_FCMOVNB, A_FCMOVNBE, A_FCMOVNE, - A_FCMOVNU, A_FCMOVU, A_FCOM, A_FCOMI, A_FCOMIP, A_FCOMP, A_FCOMPP, A_FCOS, - A_FDECSTP, A_FDISI, A_FDIV, A_FDIVP, A_FDIVR, A_FDIVRP, A_FEMMS, A_FENI, A_FFREE, - A_FIADD, A_FICOM, A_FICOMP, A_FIDIV, A_FIDIVR, A_FILD, A_FIMUL, A_FINCSTP, - A_FINIT, A_FIST, A_FISTP, A_FISTTP, A_FISUB, A_FISUBR, A_FLD, A_FLD1, A_FLDCW, - A_FLDENV, A_FLDL2E, A_FLDL2T, A_FLDLG2, A_FLDLN2, A_FLDPI, A_FLDZ, A_FMUL, - A_FMULP, A_FNCLEX, A_FNDISI, A_FNENI, A_FNINIT, A_FNOP, A_FNSAVE, A_FNSTCW, - A_FNSTENV, A_FNSTSW, A_FPATAN, A_FPREM, A_FPREM1, A_FPTAN, A_FRNDINT, A_FRSTOR, - A_FSAVE, A_FSCALE, A_FSETPM, A_FSIN, A_FSINCOS, A_FSQRT, A_FST, A_FSTCW, - A_FSTENV, A_FSTP, A_FSTSW, A_FSUB, A_FSUBP, A_FSUBR, A_FSUBRP, A_FTST, A_FUCOM, - A_FUCOMI, A_FUCOMIP, A_FUCOMP, A_FUCOMPP, A_FWAIT, A_FXAM, A_FXCH, A_FXTRACT, - A_FYL2X, A_FYL2XP1, A_HLT, A_IBTS, A_ICEBP, A_IDIV, A_IMUL, A_IN, A_INC, A_INSB, - A_INSD, A_INSW, A_INT, A_INT01, A_INT1, A_INT03, A_INT3, A_INVD, A_INVLPG, - A_IRET, A_IRETD, A_IRETW, A_IRETQ, A_JECXZ, A_JRCXZ, A_JMP, A_LAHF, A_LAR, - A_LCALL, A_LEA, A_LEAVE, A_LFS, A_LGDT, A_LGS, A_LIDT, A_LJMP, A_LLDT, A_LMSW, - A_LOADALL, A_LOADALL286, A_LOCK, A_LODSB, A_LODSD, A_LODSW, A_LOOP, A_LOOPE, - A_LOOPNE, A_LOOPNZ, A_LOOPZ, A_LSL, A_LSS, A_LTR, A_MONITOR, A_MOV, A_MOVD, - A_MOVQ, A_MOVSB, A_MOVSD, A_MOVSQ, A_MOVSW, A_MOVSX, A_MOVZX, A_MUL, A_MWAIT, - A_NEG, A_NOP, A_NOT, A_OR, A_OUT, A_OUTSB, A_OUTSD, A_OUTSW, A_PACKSSDW, - A_PACKSSWB, A_PACKUSWB, A_PADDB, A_PADDD, A_PADDSB, A_PADDSIW, A_PADDSW, - A_PADDUSB, A_PADDUSW, A_PADDW, A_PAND, A_PANDN, A_PAVEB, A_PAVGUSB, A_PCMPEQB, - A_PCMPEQD, A_PCMPEQW, A_PCMPGTB, A_PCMPGTD, A_PCMPGTW, A_PDISTIB, A_PF2ID, - A_PFACC, A_PFADD, A_PFCMPEQ, A_PFCMPGE, A_PFCMPGT, A_PFMAX, A_PFMIN, A_PFMUL, - A_PFRCP, A_PFRCPIT1, A_PFRCPIT2, A_PFRSQIT1, A_PFRSQRT, A_PFSUB, A_PFSUBR, - A_PI2FD, A_PMACHRIW, A_PMADDWD, A_PMAGW, A_PMULHRIW, A_PMULHRWA, A_PMULHRWC, - A_PMULHW, A_PMULLW, A_PMVGEZB, A_PMVLZB, A_PMVNZB, A_PMVZB, A_POP, A_POPF, - A_POPFW, A_POPFQ, A_POR, A_PREFETCH, A_PREFETCHW, A_PSLLD, A_PSLLDQ, A_PSLLQ, - A_PSLLW, A_PSRAD, A_PSRAW, A_PSRLD, A_PSRLQ, A_PSRLW, A_PSUBB, A_PSUBD, A_PSUBSB, - A_PSUBSIW, A_PSUBSW, A_PSUBUSB, A_PSUBUSW, A_PSUBW, A_PUNPCKHBW, A_PUNPCKHDQ, - A_PUNPCKHWD, A_PUNPCKLBW, A_PUNPCKLDQ, A_PUNPCKLWD, A_PUSH, A_PUSHF, A_PUSHFW, - A_PUSHFQ, A_PXOR, A_RCL, A_RCR, A_RDSHR, A_RDMSR, A_RDPMC, A_RDTSC, A_REP, - A_REPE, A_REPNE, A_REPNZ, A_REPZ, A_RET, A_RETF, A_RETN, A_RETW, A_RETFW, - A_RETNW, A_RETFD, A_RETQ, A_RETFQ, A_RETNQ, A_ROL, A_ROR, A_RSDC, A_RSLDT, A_RSM, - A_SAHF, A_SAL, A_SAR, A_SBB, A_SCASB, A_SCASD, A_SCASQ, A_SCASW, A_SEGCS, - A_SEGDS, A_SEGES, A_SEGFS, A_SEGGS, A_SEGSS, A_SGDT, A_SHL, A_SHLD, A_SHR, - A_SHRD, A_SIDT, A_SLDT, A_SMI, A_SMINT, A_SMINTOLD, A_SMSW, A_STC, A_STD, A_STI, - A_STOSB, A_STOSD, A_STOSW, A_STR, A_SUB, A_SVDC, A_SVLDT, A_SVTS, A_SYSCALL, - A_SYSENTER, A_SYSEXIT, A_SYSRET, A_TEST, A_UD1, A_UD2, A_UMOV, A_VERR, A_VERW, - A_WAIT, A_WBINVD, A_WRSHR, A_WRMSR, A_XADD, A_XBTS, A_XCHG, A_XLAT, A_XLATB, - A_XOR, A_XSTORE, A_XCRYPTECB, A_XCRYPTCBC, A_XCRYPTCFB, A_XCRYPTOFB, A_CMOVcc, - A_Jcc, A_SETcc, A_MOVS, A_CMPS, A_SCAS, A_LODS, A_STOS, A_INS, A_OUTS, A_ADDPS, - A_ADDSS, A_ANDNPS, A_ANDPS, A_CMPEQPS, A_CMPEQSS, A_CMPLEPS, A_CMPLESS, - A_CMPLTPS, A_CMPLTSS, A_CMPNEQPS, A_CMPNEQSS, A_CMPNLEPS, A_CMPNLESS, - A_CMPNLTPS, A_CMPNLTSS, A_CMPORDPS, A_CMPORDSS, A_CMPUNORDPS, A_CMPUNORDSS, - A_CMPPS, A_CMPSS, A_COMISS, A_CVTPI2PS, A_CVTPS2PI, A_CVTSI2SS, A_CVTSS2SI, - A_CVTTPS2PI, A_CVTTSS2SI, A_DIVPS, A_DIVSS, A_LDMXCSR, A_MAXPS, A_MAXSS, A_MINPS, - A_MINSS, A_MOVAPS, A_MOVHPS, A_MOVLHPS, A_MOVLPS, A_MOVHLPS, A_MOVMSKPS, - A_MOVNTPS, A_MOVSS, A_MOVUPS, A_MULPS, A_MULSS, A_ORPS, A_RCPPS, A_RCPSS, - A_RSQRTPS, A_RSQRTSS, A_SHUFPS, A_SQRTPS, A_SQRTSS, A_STMXCSR, A_SUBPS, A_SUBSS, - A_UCOMISS, A_UNPCKHPS, A_UNPCKLPS, A_XORPS, A_FXRSTOR, A_FXSAVE, A_PREFETCHNTA, - A_PREFETCHT0, A_PREFETCHT1, A_PREFETCHT2, A_SFENCE, A_MASKMOVQ, A_MOVNTQ, - A_PAVGB, A_PAVGW, A_PEXTRW, A_PINSRW, A_PMAXSW, A_PMAXUB, A_PMINSW, A_PMINUB, - A_PMOVMSKB, A_PMULHUW, A_PSADBW, A_PSHUFW, A_PFNACC, A_PFPNACC, A_PI2FW, A_PF2IW, - A_PSWAPD, A_FFREEP, A_MASKMOVDQU, A_CLFLUSH, A_MOVNTDQ, A_MOVNTI, A_MOVNTPD, - A_PAUSE, A_LFENCE, A_MFENCE, A_MOVDQA, A_MOVDQU, A_MOVDQ2Q, A_MOVQ2DQ, A_PADDQ, - A_PMULUDQ, A_PSHUFD, A_PSHUFHW, A_PSHUFLW, A_PSRLDQ, A_PSUBQ, A_PUNPCKHQDQ, - A_PUNPCKLQDQ, A_ADDPD, A_ADDSD, A_ANDNPD, A_ANDPD, A_CMPEQPD, A_CMPEQSD, - A_CMPLEPD, A_CMPLESD, A_CMPLTPD, A_CMPLTSD, A_CMPNEQPD, A_CMPNEQSD, A_CMPNLEPD, - A_CMPNLESD, A_CMPNLTPD, A_CMPNLTSD, A_CMPORDPD, A_CMPORDSD, A_CMPUNORDPD, - A_CMPUNORDSD, A_CMPPD, A_COMISD, A_CVTDQ2PD, A_CVTDQ2PS, A_CVTPD2DQ, A_CVTPD2PI, - A_CVTPD2PS, A_CVTPI2PD, A_CVTPS2DQ, A_CVTPS2PD, A_CVTSD2SI, A_CVTSD2SS, - A_CVTSI2SD, A_CVTSS2SD, A_CVTTPD2PI, A_CVTTPD2DQ, A_CVTTPS2DQ, A_CVTTSD2SI, - A_DIVPD, A_DIVSD, A_MAXPD, A_MAXSD, A_MINPD, A_MINSD, A_MOVAPD, A_MOVHPD, - A_MOVLPD, A_MOVMSKPD, A_MOVUPD, A_MULPD, A_MULSD, A_ORPD, A_SHUFPD, A_SQRTPD, - A_SQRTSD, A_SUBPD, A_SUBSD, A_UCOMISD, A_UNPCKHPD, A_UNPCKLPD, A_XORPD, - A_ADDSUBPD, A_ADDSUBPS, A_HADDPD, A_HADDPS, A_HSUBPD, A_HSUBPS, A_LDDQU, - A_MOVDDUP, A_MOVSHDUP, A_MOVSLDUP, A_VMREAD, A_VMWRITE, A_VMCALL, A_VMLAUNCH, - A_VMRESUME, A_VMXOFF, A_VMXON, A_VMCLEAR, A_VMPTRLD, A_VMPTRST, A_VMRUN, - A_VMMCALL, A_VMLOAD, A_VMSAVE, A_STGI, A_CLGI, A_SKINIT, A_INVLPGA, A_MONTMUL, - A_XSHA1, A_XSHA256, A_DMINT, A_RDM, A_MOVABS, A_MOVSXD, A_CQO, A_CDQE, - A_CMPXCHG16B, A_MOVNTSS, A_MOVNTSD, A_INSERTQ, A_EXTRQ, A_LZCNT, A_PABSB, - A_PABSW, A_PABSD, A_PALIGNR, A_PHADDW, A_PHADDD, A_PHADDSW, A_PHSUBW, A_PHSUBD, - A_PHSUBSW, A_PMADDUBSW, A_PMULHRSW, A_PSHUFB, A_PSIGNB, A_PSIGNW, A_PSIGND, - A_BLENDPS, A_BLENDPD, A_BLENDVPS, A_BLENDVPD, A_DPPS, A_DPPD, A_EXTRACTPS, - A_INSERTPS, A_MOVNTDQA, A_MPSADBW, A_PACKUSDW, A_PBLENDVB, A_PBLENDW, A_PCMPEQQ, - A_PEXTRB, A_PEXTRD, A_PEXTRQ, A_PHMINPOSUW, A_PINSRB, A_PINSRD, A_PINSRQ, A_PMAXSB, - A_PMAXSD, A_PMAXUD, A_PMAXUW, A_PMINSB, A_PMINSD, A_PMINUW, A_PMINUD, A_PMOVSXBW, - A_PMOVSXBD, A_PMOVSXBQ, A_PMOVSXWD, A_PMOVSXWQ, A_PMOVSXDQ, A_PMOVZXBW, A_PMOVZXBD, - A_PMOVZXBQ, A_PMOVZXWD, A_PMOVZXWQ, A_PMOVZXDQ, A_PMULDQ, A_PMULLD, A_PTEST, - A_ROUNDPS, A_ROUNDPD, A_ROUNDSS, A_ROUNDSD, A_CRC32, A_PCMPESTRI, A_PCMPESTRM, - A_PCMPISTRI, A_PCMPISTRM, A_PCMPGTQ, A_POPCNT, A_AESENC, A_AESENCLAST, A_AESDEC, - A_AESDECLAST, A_AESIMC, A_AESKEYGENASSIST, A_RDTSCP, A_STOSQ, A_LODSQ, A_CMPSQ, - A_VADDPD, A_VADDPS, A_VADDSD, A_VADDSS, A_VADDSUBPD, A_VADDSUBPS, A_VAESDEC, - A_VAESDECLAST, A_VAESENC, A_VAESENCLAST, A_VAESIMC, A_VAESKEYGENASSIST, A_VANDNPD, - A_VANDNPS, A_VANDPD, A_VANDPS, A_VBLENDPD, A_VBLENDPS, A_VBLENDVPD, A_VBLENDVPS, - A_VBROADCASTF128, A_VBROADCASTSD, A_VBROADCASTSS, A_VCMPEQPS, A_VCMPLTPS, - A_VCMPLEPS, A_VCMPUNORDPS, A_VCMPNEQPS, A_VCMPNLTPS, A_VCMPNLEPS, A_VCMPORDPS, - A_VCMPEQ_UQPS, A_VCMPNGEPS, A_VCMPNGTPS, A_VCMPFALSEPS, A_VCMPNEQ_OQPS, - A_VCMPGEPS, A_VCMPGTPS, A_VCMPTRUEPS, A_VCMPEQ_OSPS, A_VCMPLT_OQPS, A_VCMPLE_OQPS, - A_VCMPUNORD_SPS, A_VCMPNEQ_USPS, A_VCMPNLT_UQPS, A_VCMPNLE_UQPS, A_VCMPORD_SPS, - A_VCMPEQ_USPS, A_VCMPNGE_UQPS, A_VCMPNGT_UQPS, A_VCMPFALSE_OSPS, A_VCMPNEQ_OSPS, - A_VCMPGE_OQPS, A_VCMPGT_OQPS, A_VCMPTRUE_USPS, A_VCMPEQPD, A_VCMPLTPD, A_VCMPLEPD, - A_VCMPUNORDPD, A_VCMPNEQPD, A_VCMPNLTPD, A_VCMPNLEPD, A_VCMPORDPD, A_VCMPEQ_UQPD, - A_VCMPNGEPD, A_VCMPNGTPD, A_VCMPFALSEPD, A_VCMPNEQ_OQPD, A_VCMPGEPD, A_VCMPGTPD, - A_VCMPTRUEPD, A_VCMPEQ_OSPD, A_VCMPLT_OQPD, A_VCMPLE_OQPD, A_VCMPUNORD_SPD, - A_VCMPNEQ_USPD, A_VCMPNLT_UQPD, A_VCMPNLE_UQPD, A_VCMPORD_SPD, A_VCMPEQ_USPD, - A_VCMPNGE_UQPD, A_VCMPNGT_UQPD, A_VCMPFALSE_OSPD, A_VCMPNEQ_OSPD, A_VCMPGE_OQPD, - A_VCMPGT_OQPD, A_VCMPTRUE_USPD, A_VCMPPD, A_VCMPPS, A_VCMPSD, A_VCMPSS, A_VCOMISD, - A_VCOMISS, A_VCVTDQ2PD, A_VCVTDQ2PS, A_VCVTPD2DQ, A_VCVTPD2PS, A_VCVTPS2DQ, - A_VCVTPS2PD, A_VCVTSD2SI, A_VCVTSD2SS, A_VCVTSI2SD, A_VCVTSI2SS, A_VCVTSS2SD, - A_VCVTSS2SI, A_VCVTTPD2DQ, A_VCVTTPS2DQ, A_VCVTTSD2SI, A_VCVTTSS2SI, A_VDIVPD, - A_VDIVPS, A_VDIVSD, A_VDIVSS, A_VDPPD, A_VDPPS, A_VEXTRACTF128, A_VEXTRACTPS, - A_VHADDPD, A_VHADDPS, A_VHSUBPD, A_VHSUBPS, A_VINSERTF128, A_VINSERTPS, A_VLDDQU, - A_VLDMXCSR, A_VMASKMOVDQU, A_VMASKMOVPD, A_VMASKMOVPS, A_VMAXPD, A_VMAXPS, - A_VMAXSD, A_VMAXSS, A_VMINPD, A_VMINPS, A_VMINSD, A_VMINSS, A_VMOVAPD, A_VMOVAPS, - A_VMOVD, A_VMOVDDUP, A_VMOVDQA, A_VMOVDQU, A_VMOVHLPS, A_VMOVHPD, A_VMOVHPS, - A_VMOVLHPS, A_VMOVLPD, A_VMOVLPS, A_VMOVMSKPD, A_VMOVMSKPS, A_VMOVNTDQ, - A_VMOVNTDQA, A_VMOVNTPD, A_VMOVNTPS, A_VMOVQ, A_VMOVSD, A_VMOVSHDUP, A_VMOVSLDUP, - A_VMOVSS, A_VMOVUPD, A_VMOVUPS, A_VMPSADBW, A_VMULPD, A_VMULPS, A_VMULSD, - A_VMULSS, A_VORPD, A_VORPS, A_VPABSB, A_VPABSD, A_VPABSW, A_VPACKSSDW, - A_VPACKSSWB, A_VPACKUSDW, A_VPACKUSWB, A_VPADDB, A_VPADDD, A_VPADDQ, A_VPADDSB, - A_VPADDSW, A_VPADDUSB, A_VPADDUSW, A_VPADDW, A_VPALIGNR, A_VPAND, A_VPANDN, - A_VPAVGB, A_VPAVGW, A_VPBLENDVB, A_VPBLENDW, A_VPCLMULQDQ, A_VPCMPEQB, A_VPCMPEQD, - A_VPCMPEQQ, A_VPCMPEQW, A_VPCMPESTRI, A_VPCMPESTRM, A_VPCMPGTB, A_VPCMPGTD, - A_VPCMPGTQ, A_VPCMPGTW, A_VPCMPISTRI, A_VPCMPISTRM, A_VPERM2F128, A_VPERMILPD, - A_VPERMILPS, A_VPEXTRB, A_VPEXTRD, A_VPEXTRQ, A_VPEXTRW, A_VPHADDD, A_VPHADDSW, - A_VPHADDW, A_VPHMINPOSUW, A_VPHSUBD, A_VPHSUBSW, A_VPHSUBW, A_VPINSRB, A_VPINSRD, - A_VPINSRQ, A_VPINSRW, A_VPMADDUBSW, A_VPMADDWD, A_VPMAXSB, A_VPMAXSD, A_VPMAXSW, - A_VPMAXUB, A_VPMAXUD, A_VPMAXUW, A_VPMINSB, A_VPMINSD, A_VPMINSW, A_VPMINUB, - A_VPMINUD, A_VPMINUW, A_VPMOVMSKB, A_VPMOVSXBD, A_VPMOVSXBQ, A_VPMOVSXBW, - A_VPMOVSXDQ, A_VPMOVSXWD, A_VPMOVSXWQ, A_VPMOVZXBD, A_VPMOVZXBQ, A_VPMOVZXBW, - A_VPMOVZXDQ, A_VPMOVZXWD, A_VPMOVZXWQ, A_VPMULDQ, A_VPMULHRSW, A_VPMULHUW, - A_VPMULHW, A_VPMULLD, A_VPMULLW, A_VPMULUDQ, A_VPOR, A_VPSADBW, A_VPSHUFB, - A_VPSHUFD, A_VPSHUFHW, A_VPSHUFLW, A_VPSIGNB, A_VPSIGND, A_VPSIGNW, A_VPSLLD, - A_VPSLLDQ, A_VPSLLQ, A_VPSLLW, A_VPSRAD, A_VPSRAW, A_VPSRLD, A_VPSRLDQ, A_VPSRLQ, - A_VPSRLW, A_VPSUBB, A_VPSUBD, A_VPSUBQ, A_VPSUBSB, A_VPSUBSW, A_VPSUBUSB, - A_VPSUBUSW, A_VPSUBW, A_VPTEST, A_VPUNPCKHBW, A_VPUNPCKHDQ, A_VPUNPCKHQDQ, - A_VPUNPCKHWD, A_VPUNPCKLBW, A_VPUNPCKLDQ, A_VPUNPCKLQDQ, A_VPUNPCKLWD, A_VPXOR, - A_VRCPPS, A_VRCPSS, A_VROUNDPD, A_VROUNDPS, A_VROUNDSD, A_VROUNDSS, A_VRSQRTPS, - A_VRSQRTSS, A_VSHUFPD, A_VSHUFPS, A_VSQRTPD, A_VSQRTPS, A_VSQRTSD, A_VSQRTSS, - A_VSTMXCSR, A_VSUBPD, A_VSUBPS, A_VSUBSD, A_VSUBSS, A_VTESTPD, A_VTESTPS, - A_VUCOMISD, A_VUCOMISS, A_VUNPCKHPD, A_VUNPCKHPS, A_VUNPCKLPD, A_VUNPCKLPS, - A_VXORPD, A_VXORPS, A_VZEROALL, A_VZEROUPPER, A_ANDN, A_BEXTR, A_TZCNT, A_BZHI, - A_MULX, A_PDEP, A_PEXT, A_RORX, A_SARX, A_SHLX, A_SHRX, A_VBROADCASTI128, - A_VEXTRACTI128, A_VINSERTI128, A_VPBLENDD, A_VPBROADCASTB, A_VPBROADCASTD, - A_VPBROADCASTQ, A_VPBROADCASTW, A_VPERM2I128, A_VPERMD); - -const - ExtremeRange1Expected: array[0..1023] of Byte = ( - $00, $00, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 0 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } - $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $08, $00, $00, $03, $03, { 176 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, $00, $00, { 320 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } - $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } - $00, $00, $00, $00, $00, $05, $00, $00, $00, $00, $00, $00, $08, $05, $00, $07, { 416 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } - $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $05, $00, $00, $00, $05, { 528 } - $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 608 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, { 672 } - $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, $00, { 688 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } - $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, { 784 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } - $04, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } - $00, $00, $00, $08, $00, $00, $08, $04, $04, $00, $00, $00, $06, $06, $06, $06, { 832 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 928 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, { 976 } - $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, { 992 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 { 1008 } - ); - - ExtremeRange2Expected: array[0..1023] of Byte = ( - $00, $00, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 0 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } - $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $26, $00, $00, $0D, $03, { 176 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $27, $00, $00, $00, $00, $00, $00, { 320 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } - $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } - $00, $00, $00, $00, $00, $12, $00, $00, $00, $00, $00, $00, $08, $05, $00, $22, { 416 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } - $23, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $11, $00, $00, $00, $13, { 528 } - $00, $21, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 608 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $1A, $1B, $00, $00, $00, $00, { 672 } - $00, $00, $00, $00, $00, $00, $1C, $1D, $00, $00, $00, $00, $00, $00, $00, $00, { 688 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } - $00, $00, $00, $00, $00, $00, $00, $14, $15, $00, $00, $00, $00, $00, $00, $00, { 784 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } - $0F, $0E, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } - $00, $00, $00, $24, $00, $00, $25, $04, $10, $00, $00, $00, $18, $19, $1E, $1F, { 832 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 928 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $16, $17, $00, { 976 } - $00, $00, $00, $00, $00, $00, $00, $20, $06, $00, $00, $00, $00, $00, $00, $00, { 992 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 { 1008 } - ); - - ExtremeRange3Expected: array[0..1023] of Byte = ( - $00, $00, $44, $01, $3F, $40, $00, $00, $00, $41, $42, $00, $00, $00, $00, $00, { 0 } - $00, $00, $00, $45, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } - $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $26, $00, $00, $0D, $03, { 176 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $27, $00, $00, $00, $00, $00, $00, { 320 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } - $00, $43, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } - $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } - $00, $00, $00, $00, $00, $12, $00, $00, $00, $00, $00, $00, $08, $05, $00, $22, { 416 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } - $23, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $11, $00, $00, $00, $13, { 528 } - $00, $21, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $33, $34, $00, $00, $00, { 608 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } - $00, $00, $00, $2E, $2F, $30, $31, $32, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } - $00, $00, $00, $00, $00, $00, $00, $00, $2C, $2D, $1A, $1B, $00, $00, $35, $36, { 672 } - $37, $38, $39, $3A, $00, $00, $1C, $1D, $00, $00, $00, $00, $29, $00, $00, $00, { 688 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } - $00, $00, $00, $00, $00, $00, $00, $14, $15, $00, $00, $00, $00, $00, $00, $00, { 784 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } - $0F, $0E, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } - $00, $00, $00, $24, $00, $00, $25, $04, $10, $00, $00, $00, $18, $19, $1E, $1F, { 832 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $3B, $3C, $3D, $3E, $00, $00, $00, { 928 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } - $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $16, $17, $00, { 976 } - $00, $00, $00, $00, $00, $00, $00, $20, $06, $00, $00, $00, $00, $00, $00, $28, { 992 } - $00, $00, $00, $00, $46, $47, $2A, $00, $00, $00, $00, $00, $00, $00, $00, $2B { 1008 } - ); - -{ TTestAncestor } -type - TTestAncestor = class - private - FStartTime: Real; - FEndTime: Real; - FAvgTime: Real; - procedure SetStartTime; - procedure SetEndTime; - protected - procedure DoTestIteration(Iteration: Integer); virtual; abstract; - public - constructor Create; virtual; - destructor Destroy; override; - procedure Run; - function TestTitle: shortstring; virtual; abstract; - function WriteResults: Boolean; virtual; abstract; - property RunTime: Real read FAvgTime; - end; - - TTestClass = class of TTestAncestor; - - TByteTest = class(TTestAncestor) - protected - FResultStorage: array[Byte] of Byte; - end; - - TWordTest = class(TTestAncestor) - protected - FResultStorage: array[Word] of Byte; - end; - - TMappedTest = class(TByteTest) - protected - procedure DoMapping(Index, Input: Integer); virtual; abstract; - end; - - TCompleteByteRange = class(TMappedTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - procedure DoMapping(Index, Input: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TCompleteByteRangeFirstWeighted = class(TCompleteByteRange) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TCompleteByteRangeLastWeighted = class(TCompleteByteRange) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TAlmostFullByteRange = class(TMappedTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - procedure DoMapping(Index, Input: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TAlmostFullByteRangeFirstWeighted = class(TAlmostFullByteRange) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TAlmostFullByteRangeLastWeighted = class(TAlmostFullByteRange) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithDefault = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithDefaultUnlikely = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithDefaultWeighted = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithElse = class(TSingleEntryWithDefault) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - end; - - TSingleEntryWithElseUnlikely = class(TSingleEntryWithDefaultUnlikely) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - end; - - TSingleEntryWithElseWeighted = class(TSingleEntryWithDefaultWeighted) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - end; - - TSingleEntryAtZeroWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryAtMinus1WithDefault = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryAtMinus4WithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWith0To5RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWith0To50RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWith1To5RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWith1To50RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithMinus1To5RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSingleEntryWithMinus1To50RangeWithElse = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TExtremeRange1 = class(TWordTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TExtremeRange2 = class(TWordTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TExtremeRange3 = class(TWordTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TExtremeRange4 = class(TWordTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataTest1 = class(TWordTest) - protected - procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; - end; - - TSparseDataEqual1 = class(TSparseDataTest1) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMOVWeighted1 = class(TSparseDataTest1) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMidpointWeighted1 = class(TSparseDataTest1) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataTest2 = class(TWordTest) - protected - procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; - end; - - TSparseDataEqual2 = class(TSparseDataTest2) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMOVWeighted2 = class(TSparseDataTest2) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMidpointWeighted2 = class(TSparseDataTest2) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataTest3 = class(TWordTest) - protected - procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; - end; - - TSparseDataEqual3 = class(TSparseDataTest3) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMOVWeighted3 = class(TSparseDataTest3) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TSparseDataMidpointWeighted3 = class(TSparseDataTest3) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TLinearListDependsOnInput = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - - TCStyleCascade = class(TByteTest) - protected - procedure DoTestIteration(Iteration: Integer); override; - public - function TestTitle: shortstring; override; - function WriteResults: Boolean; override; - end; - -{ TTestAncestor } -constructor TTestAncestor.Create; - begin - FStartTime := 0; - FEndTime := 0; - FAvgTime := 0; - end; - -destructor TTestAncestor.Destroy; - begin - inherited Destroy; - end; - -procedure TTestAncestor.SetStartTime; - begin - FStartTime := GetRealTime(); - end; - -procedure TTestAncestor.SetEndTime; - begin - FEndTime := GetRealTime(); - if FEndTime < FStartTime then { Happens if the test runs past midnight } - FEndTime := FEndTime + 86400.0; - end; - -procedure TTestAncestor.Run; - var - X: Integer; - begin - SetStartTime; - for X := 0 to ITERATIONS - 1 do - DoTestIteration(X); - - SetEndTime; - - FAvgTime := FEndTime - FStartTime; - end; - -{ TCompleteByteRange } -function TCompleteByteRange.TestTitle: shortstring; - begin - Result := 'Byte domain, entirely covered; equal polling'; - end; - -function TCompleteByteRange.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> AES_S_Box[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(AES_S_Box[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TCompleteByteRange.DoMapping(Index, Input: Integer); - begin - case Input of - { First row of S-Box (except zero) } - $00: FResultStorage[Index] := $63; - $01: FResultStorage[Index] := $7c; - $02: FResultStorage[Index] := $77; - $03: FResultStorage[Index] := $7b; - $04: FResultStorage[Index] := $f2; - $05: FResultStorage[Index] := $6b; - $06: FResultStorage[Index] := $6f; - $07: FResultStorage[Index] := $c5; - $08: FResultStorage[Index] := $30; - $09: FResultStorage[Index] := $01; - $0A: FResultStorage[Index] := $67; - $0B: FResultStorage[Index] := $2b; - $0C: FResultStorage[Index] := $fe; - $0D: FResultStorage[Index] := $d7; - $0E: FResultStorage[Index] := $ab; - $0F: FResultStorage[Index] := $76; - {Last row of S-Box } - $F0: FResultStorage[Index] := $8c; - $F1: FResultStorage[Index] := $a1; - $F2: FResultStorage[Index] := $89; - $F3: FResultStorage[Index] := $0d; - $F4: FResultStorage[Index] := $bf; - $F5: FResultStorage[Index] := $e6; - $F6: FResultStorage[Index] := $42; - $F7: FResultStorage[Index] := $68; - $F8: FResultStorage[Index] := $41; - $F9: FResultStorage[Index] := $99; - $FA: FResultStorage[Index] := $2d; - $FB: FResultStorage[Index] := $0f; - $FC: FResultStorage[Index] := $b0; - $FD: FResultStorage[Index] := $54; - $FE: FResultStorage[Index] := $bb; - $FF: FResultStorage[Index] := $16; - { Everything else } - $10..$EF: FResultStorage[Index] := AES_S_Box[Input]; - end; - end; - -procedure TCompleteByteRange.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - DoMapping(Input, Input); - end; - -{ TCompleteByteRangeFirstWeighted } - -function TCompleteByteRangeFirstWeighted.TestTitle: shortstring; - begin - Result := 'Byte domain, entirely covered; first weighted'; - end; - -function TCompleteByteRangeFirstWeighted.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> FirstWeighted[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(FirstWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TCompleteByteRangeFirstWeighted.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - if Input < $C0 then - DoMapping(Input, 0) - else - DoMapping(Input, Input); - end; - -{ TCompleteByteRangeLastWeighted } - -function TCompleteByteRangeLastWeighted.TestTitle: shortstring; - begin - Result := 'Byte domain, entirely covered; last weighted'; - end; - -function TCompleteByteRangeLastWeighted.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> LastWeighted[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(LastWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TCompleteByteRangeLastWeighted.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - if Input < $C0 then - DoMapping(Input, $FF) - else - DoMapping(Input, Input); - end; - -{ TAlmostFullByteRange } - -function TAlmostFullByteRange.TestTitle: shortstring; - begin - Result := 'Byte domain, almost entirely covered; equal polling'; - end; - -function TAlmostFullByteRange.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> AlmostFullExpected[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(AlmostFullExpected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TAlmostFullByteRange.DoMapping(Index, Input: Integer); - begin - case Input of - { First row of S-Box } - $00: FResultStorage[Index] := $63; - $01: FResultStorage[Index] := $7c; - $02: FResultStorage[Index] := $77; - $03: FResultStorage[Index] := $7b; - $04: FResultStorage[Index] := $f2; - $05: FResultStorage[Index] := $6b; - $06: FResultStorage[Index] := $6f; - $07: FResultStorage[Index] := $c5; - $08: FResultStorage[Index] := $30; - $09: FResultStorage[Index] := $01; - $0A: FResultStorage[Index] := $67; - $0B: FResultStorage[Index] := $2b; - $0C: FResultStorage[Index] := $fe; - $0D: FResultStorage[Index] := $d7; - $0E: FResultStorage[Index] := $ab; - $0F: FResultStorage[Index] := $76; - { Other rows } - $10..$3F: FResultStorage[Index] := AES_S_Box[Input]; - $60..$FF: FResultStorage[Index] := AES_S_Box[Input]; - { Zeroed rows } - else FResultStorage[Index] := $00; - end; - end; - -procedure TAlmostFullByteRange.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - DoMapping(Input, Input); - end; - -{ TAlmostFullByteRangeFirstWeighted } - -function TAlmostFullByteRangeFirstWeighted.TestTitle: shortstring; - begin - Result := 'Byte domain, almost entirely covered; first weighted'; - end; - -function TAlmostFullByteRangeFirstWeighted.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> FirstWeighted[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(FirstWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TAlmostFullByteRangeFirstWeighted.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - if Input < $C0 then - DoMapping(Input, 0) - else - DoMapping(Input, Input); - end; - -{ TAlmostFullByteRangeLastWeighted } - -function TAlmostFullByteRangeLastWeighted.TestTitle: shortstring; - begin - Result := 'Byte domain, almost entirely covered; last weighted'; - end; - -function TAlmostFullByteRangeLastWeighted.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> LastWeighted[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(LastWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TAlmostFullByteRangeLastWeighted.DoTestIteration(Iteration: Integer); - var - Input: Byte; - begin - Input := Iteration and $FF; - if Input < $C0 then - DoMapping(Input, $FF) - else - DoMapping(Input, Input); - end; - -{ TSingleEntryWithDefault } -function TSingleEntryWithDefault.TestTitle: shortstring; - begin - Result := 'Single entry with default value; 1/256 match chance'; - end; - -function TSingleEntryWithDefault.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> IIf(X = 71, 1, 0) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(X = 71, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWithDefault.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - FResultStorage[Index] := 0; - case Index of - 71: FResultStorage[Index] := 1; - end; - end; - -{ TSingleEntryWithDefaultUnlikely } - -function TSingleEntryWithDefaultUnlikely.TestTitle: shortstring; - begin - Result := 'Single entry with default value; 75% match chance'; - end; - -function TSingleEntryWithDefaultUnlikely.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> IIf(((X and $2) shr 1) or (X and $1) = 1, 1, 0) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(((X and $2) shr 1) or (X and $1) = 1, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWithDefaultUnlikely.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - FResultStorage[Index] := 0; - case ((Index and $2) shr 1) or (Index and $1) of - 1: FResultStorage[Index] := 1; - end; - end; - -{ TSingleEntryWithDefaultWeighted } - -function TSingleEntryWithDefaultWeighted.TestTitle: shortstring; - begin - Result := 'Single entry with default value; 25% match chance'; - end; - -function TSingleEntryWithDefaultWeighted.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - - for X := 0 to 255 do - if FResultStorage[X] <> IIf(((X and $2) shr 1) and (X and $1) = 1, 1, 0) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(((X and $2) shr 1) and (X and $1) = 1, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWithDefaultWeighted.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - FResultStorage[Index] := 0; - case ((Index and $2) shr 1) and (Index and $1) of - 1: FResultStorage[Index] := 1; - end; - end; - -{ TSingleEntryWithElse } -function TSingleEntryWithElse.TestTitle: shortstring; - begin - Result := 'Single entry with else block; 1/256 match chance'; - end; - -procedure TSingleEntryWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 71: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWithElseUnlikely } -function TSingleEntryWithElseUnlikely.TestTitle: shortstring; - begin - Result := 'Single entry with else block; 75% match chance'; - end; - -procedure TSingleEntryWithElseUnlikely.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case ((Index and $2) shr 1) or (Index and $1) of - 1: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWithElseWeighted } - -function TSingleEntryWithElseWeighted.TestTitle: shortstring; - begin - Result := 'Single entry with else block; 25% match chance'; - end; - -procedure TSingleEntryWithElseWeighted.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case ((Index and $2) shr 1) and (Index and $1) of - 1: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryAtZeroWithElse } - -function TSingleEntryAtZeroWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "0:" and else block'; - end; - -function TSingleEntryAtZeroWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - if FResultStorage[0] <> 1 then - begin - WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryAtZeroWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 0: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryAtMinus1WithDefault } - -function TSingleEntryAtMinus1WithDefault.TestTitle: shortstring; - begin - Result := 'Single entry of "-1:" with default value'; - end; - -function TSingleEntryAtMinus1WithDefault.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to $FE do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[255] <> 1 then - begin - WriteLn('FAIL - Index 255; expected $01 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryAtMinus1WithDefault.DoTestIteration(Iteration: Integer); - var - Index: ShortInt; - begin - Index := ShortInt(Iteration and $FF); - FResultStorage[Byte(Index)] := 0; - case Index of - -1: FResultStorage[255] := 1; - end; - end; - -{ TSingleEntryAtMinus4WithElse } - -function TSingleEntryAtMinus4WithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "-4:" and else block'; - end; - -function TSingleEntryAtMinus4WithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - for X := 0 to 251 do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[252] <> 1 then - begin - WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[252], 2)); - Result := False; - Exit; - end; - - for X := 253 to 255 do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryAtMinus4WithElse.DoTestIteration(Iteration: Integer); - var - Index: ShortInt; - begin - Index := ShortInt(Iteration and $FF); - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Byte(Index)] := $FF; - case Index of - -4: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWith0To5RangeWithElse } - -function TSingleEntryWith0To5RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "0..5" and else block'; - end; - -function TSingleEntryWith0To5RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to 5 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 6 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWith0To5RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 0..5: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWith0To50RangeWithElse } - -function TSingleEntryWith0To50RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "0..50" and else block'; - end; - -function TSingleEntryWith0To50RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to 50 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 51 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWith0To50RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 0..50: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWith1To5RangeWithElse } - -function TSingleEntryWith1To5RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "1..5" and else block'; - end; - -function TSingleEntryWith1To5RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - if FResultStorage[0] <> 0 then - begin - WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to 5 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 6 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWith1To5RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 1..5: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWith1To50RangeWithElse } - -function TSingleEntryWith1To50RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "1..50" and else block'; - end; - -function TSingleEntryWith1To50RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - if FResultStorage[0] <> 0 then - begin - WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to 50 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 51 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWith1To50RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 1..50: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - - -{ TSingleEntryWithMinus1To5RangeWithElse } - -function TSingleEntryWithMinus1To5RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "-1..5" and else block'; - end; - -function TSingleEntryWithMinus1To5RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - for X := 0 to 5 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 6 to $FE do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[$FF] <> 1 then - begin - WriteLn('FAIL - Index 255; expected $00 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWithMinus1To5RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: ShortInt; - begin - Index := ShortInt(Iteration and $FF); - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Byte(Index)] := $FF; - case Index of - -1..5: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TSingleEntryWithMinus1To50RangeWithElse } - -function TSingleEntryWithMinus1To50RangeWithElse.TestTitle: shortstring; - begin - Result := 'Single entry of "-1..50" and else block'; - end; - -function TSingleEntryWithMinus1To50RangeWithElse.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - for X := 0 to 50 do - if FResultStorage[X] <> 1 then - begin - WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 51 to $FE do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[$FF] <> 1 then - begin - WriteLn('FAIL - Index 255; expected $00 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - end; - -procedure TSingleEntryWithMinus1To50RangeWithElse.DoTestIteration(Iteration: Integer); - var - Index: ShortInt; - begin - Index := ShortInt(Iteration and $FF); - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Byte(Index)] := $FF; - case Index of - -1..50: FResultStorage[Index] := 1; - else FResultStorage[Index] := 0; - end; - end; - -{ TExtremeRange1 } - -function TExtremeRange1.TestTitle: shortstring; - begin - Result := 'Two labels, one with extreme spread, equal polling'; - end; - -function TExtremeRange1.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - if FResultStorage[0] <> 1 then - begin - WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to $FFFE do - if FResultStorage[X] <> 2 then - begin - WriteLn('FAIL - Index ', X, '; expected $02 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[65535] <> 0 then - begin - WriteLn('FAIL - Index 65535; expected $02 got $', hexstr(FResultStorage[65535], 2)); - Result := False; - Exit; - end; - end; - -procedure TExtremeRange1.DoTestIteration(Iteration: Integer); - var - Index: Word; - begin - Index := Iteration and $FFFF; - FResultStorage[Index] := 0; { Covers $FFFF } - case Index of - 0: - FResultStorage[Index] := 1; - 1..$FFFE: - FResultStorage[Index] := 2; - end; - end; - -{ TExtremeRange2 } - -function TExtremeRange2.TestTitle: shortstring; - begin - Result := 'Two labels, one with extreme spread, 50% else chance'; - end; - -function TExtremeRange2.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to $FFFF do - if FResultStorage[X] <> (X and $1) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $1, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TExtremeRange2.DoTestIteration(Iteration: Integer); - var - Index, Input: Word; - begin - Index := (Iteration and $FFFF); - Input := (Iteration and $1) - 1; - FResultStorage[Index] := 0; { Covers $FFFF } - case Input of - 0..$FFFD: - FResultStorage[Index] := 1; - $FFFE: - FResultStorage[Index] := 2; - end; - end; - -{ TExtremeRange3 } - -function TExtremeRange3.TestTitle: shortstring; - begin - Result := 'Two labels, sparse values, equal polling across range'; - end; - -function TExtremeRange3.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - if FResultStorage[0] <> 1 then - begin - WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to $FFFE do - if FResultStorage[X] <> 2 then - begin - WriteLn('FAIL - Index ', X, '; expected $02 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[65535] <> 0 then - begin - WriteLn('FAIL - Index 65535; expected $02 got $', hexstr(FResultStorage[65535], 2)); - Result := False; - Exit; - end; - end; - -procedure TExtremeRange3.DoTestIteration(Iteration: Integer); - var - Index: Word; - begin - Index := Iteration and $FFFF; - FResultStorage[Index] := 2; { Covers 1..$FFFE } - case Index of - 0: - FResultStorage[Index] := 1; - $FFFF: - FResultStorage[Index] := 0; - end; - end; - -{ TExtremeRange4 } - -function TExtremeRange4.TestTitle: shortstring; - begin - Result := 'Two labels, sparse values, always triggered'; - end; - -function TExtremeRange4.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to $FFFF do - if FResultStorage[X] <> (X and $1) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $1, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TExtremeRange4.DoTestIteration(Iteration: Integer); - var - Index, Input: Word; - begin - Index := (Iteration and $FFFF); - Input := (Iteration and $1) - 1; - FResultStorage[Index] := 2; { Covers 1..$FFFE } - case Input of - 0: - FResultStorage[Index] := 1; - $FFFF: - FResultStorage[Index] := 0; - end; - end; - -{ TSparseDataTest1 } - -procedure TSparseDataTest1.DoCaseBlock(Index: Integer; Input: TInstructionSet); - begin - case Input of - A_AND: - FResultStorage[Index] := 1; - A_MOV: - FResultStorage[Index] := 2; - A_MOVSX, - A_MOVZX: - FResultStorage[Index] := 3; - A_VMOVAPS, - A_VMOVAPD, - A_VMOVUPS, - A_VMOVUPD: - FResultStorage[Index] := 4; - A_MOVAPD, - A_MOVAPS, - A_MOVUPD, - A_MOVUPS: - FResultStorage[Index] := 5; - A_VDIVSD, - A_VDIVSS, - A_VSUBSD, - A_VSUBSS, - A_VMULSD, - A_VMULSS, - A_VADDSD, - A_VADDSS, - A_VANDPD, - A_VANDPS, - A_VORPD, - A_VORPS, - A_VXORPD, - A_VXORPS: - FResultStorage[Index] := 6; - A_MULSD, - A_MULSS, - A_ADDSD, - A_ADDSS: - FResultStorage[Index] := 7; - A_VMOVSD, - A_VMOVSS, - A_MOVSD, - A_MOVSS: - FResultStorage[Index] := 8; - A_LEA: - FResultStorage[Index] := 9; - A_SUB: - FResultStorage[Index] := 10; - A_SHL,A_SAL: - FResultStorage[Index] := 11; - A_SETcc: - FResultStorage[Index] := 12; - else - FResultStorage[Index] := 0; - end; - end; - -{ TSparseDataEqual1 } - -function TSparseDataEqual1.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 12 sparse labels, equal polling'; - end; - -function TSparseDataEqual1.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to 1023 do - if FResultStorage[X] <> ExtremeRange1Expected[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange1Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSparseDataEqual1.DoTestIteration(Iteration: Integer); - var - X: SmallInt; - begin - X := Iteration and 1023; - DoCaseBlock(X, TInstructionSet(X - 512)) - end; - -{ TSparseDataMOVWeightedl } - -function TSparseDataMOVWeighted1.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 12 sparse labels, 75% particular match'; - end; - -function TSparseDataMOVWeighted1.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange1Expected[X], 2); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMOVWeighted1.DoTestIteration(Iteration: Integer); - var - X: SmallInt; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); - DoCaseBlock(X, P); - end; - -{ TSparseDataMidpointWeighted1 } - -function TSparseDataMidpointWeighted1.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 12 sparse labels, 75% midpoint match'; - end; - -function TSparseDataMidpointWeighted1.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange1Expected[X], 6); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMidpointWeighted1.DoTestIteration(Iteration: Integer); - var - X: Word; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); - DoCaseBlock(X, P); - end; - -{ TSparseDataTest2 } - -procedure TSparseDataTest2.DoCaseBlock(Index: Integer; Input: TInstructionSet); - begin - case Input of - A_AND: - FResultStorage[Index] := 1; - A_MOV: - FResultStorage[Index] := 2; - A_MOVSX: - FResultStorage[Index] := 13; - A_MOVZX: - FResultStorage[Index] := 3; - A_VMOVAPS: - FResultStorage[Index] := 14; - A_VMOVAPD: - FResultStorage[Index] := 15; - A_VMOVUPS: - FResultStorage[Index] := 16; - A_VMOVUPD: - FResultStorage[Index] := 4; - A_MOVAPD: - FResultStorage[Index] := 17; - A_MOVAPS: - FResultStorage[Index] := 18; - A_MOVUPD: - FResultStorage[Index] := 19; - A_MOVUPS: - FResultStorage[Index] := 5; - A_VDIVSD: - FResultStorage[Index] := 20; - A_VDIVSS: - FResultStorage[Index] := 21; - A_VSUBSD: - FResultStorage[Index] := 22; - A_VSUBSS: - FResultStorage[Index] := 23; - A_VMULSD: - FResultStorage[Index] := 24; - A_VMULSS: - FResultStorage[Index] := 25; - A_VADDSD: - FResultStorage[Index] := 26; - A_VADDSS: - FResultStorage[Index] := 27; - A_VANDPD: - FResultStorage[Index] := 28; - A_VANDPS: - FResultStorage[Index] := 29; - A_VORPD: - FResultStorage[Index] := 30; - A_VORPS: - FResultStorage[Index] := 31; - A_VXORPD: - FResultStorage[Index] := 32; - A_VXORPS: - FResultStorage[Index] := 6; - A_MULSD: - FResultStorage[Index] := 33; - A_MULSS: - FResultStorage[Index] := 34; - A_ADDSD: - FResultStorage[Index] := 35; - A_ADDSS: - FResultStorage[Index] := 7; - A_VMOVSD: - FResultStorage[Index] := 36; - A_VMOVSS: - FResultStorage[Index] := 37; - A_MOVSD: - FResultStorage[Index] := 38; - A_MOVSS: - FResultStorage[Index] := 8; - A_LEA: - FResultStorage[Index] := 9; - A_SUB: - FResultStorage[Index] := 10; - A_SHL: - FResultStorage[Index] := 39; - A_SAL: - FResultStorage[Index] := 11; - A_SETcc: - FResultStorage[Index] := 12; - else - FResultStorage[Index] := 0; - end; - end; - -{ TSparseDataEqual2 } - -function TSparseDataEqual2.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 39 sparse labels, equal polling'; - end; - -function TSparseDataEqual2.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to 1023 do - if FResultStorage[X] <> ExtremeRange2Expected[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange2Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSparseDataEqual2.DoTestIteration(Iteration: Integer); - var - X: SmallInt; - begin - X := Iteration and 1023; - DoCaseBlock(X, TInstructionSet(X - 512)) - end; - -{ TSparseDataMOVWeighted2 } - -function TSparseDataMOVWeighted2.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 39 sparse labels, 75% particular match'; - end; - -function TSparseDataMOVWeighted2.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange2Expected[X], 2); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMOVWeighted2.DoTestIteration(Iteration: Integer); - var - X: SmallInt; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); - DoCaseBlock(X, P); - end; - -{ TSparseDataMidpointWeighted2 } - -function TSparseDataMidpointWeighted2.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 39 sparse labels, 75% midpoint match'; - end; - -function TSparseDataMidpointWeighted2.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange2Expected[X], 26); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMidpointWeighted2.DoTestIteration(Iteration: Integer); - var - X: SmallInt; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); - DoCaseBlock(X, P); - end; - -{ TSparseDataTest3 } - -procedure TSparseDataTest3.DoCaseBlock(Index: Integer; Input: TInstructionSet); - begin - case Input of - A_AND: - FResultStorage[Index] := 1; - A_MOV: - FResultStorage[Index] := 2; - A_MOVSX: - FResultStorage[Index] := 13; - A_MOVZX: - FResultStorage[Index] := 3; - A_VMOVAPS: - FResultStorage[Index] := 14; - A_VMOVAPD: - FResultStorage[Index] := 15; - A_VMOVUPS: - FResultStorage[Index] := 16; - A_VMOVUPD: - FResultStorage[Index] := 4; - A_MOVAPD: - FResultStorage[Index] := 17; - A_MOVAPS: - FResultStorage[Index] := 18; - A_MOVUPD: - FResultStorage[Index] := 19; - A_MOVUPS: - FResultStorage[Index] := 5; - A_VDIVSD: - FResultStorage[Index] := 20; - A_VDIVSS: - FResultStorage[Index] := 21; - A_VSUBSD: - FResultStorage[Index] := 22; - A_VSUBSS: - FResultStorage[Index] := 23; - A_VMULSD: - FResultStorage[Index] := 24; - A_VMULSS: - FResultStorage[Index] := 25; - A_VADDSD: - FResultStorage[Index] := 26; - A_VADDSS: - FResultStorage[Index] := 27; - A_VANDPD: - FResultStorage[Index] := 28; - A_VANDPS: - FResultStorage[Index] := 29; - A_VORPD: - FResultStorage[Index] := 30; - A_VORPS: - FResultStorage[Index] := 31; - A_VXORPD: - FResultStorage[Index] := 32; - A_VXORPS: - FResultStorage[Index] := 6; - A_MULSD: - FResultStorage[Index] := 33; - A_MULSS: - FResultStorage[Index] := 34; - A_ADDSD: - FResultStorage[Index] := 35; - A_ADDSS: - FResultStorage[Index] := 7; - A_VMOVSD: - FResultStorage[Index] := 36; - A_VMOVSS: - FResultStorage[Index] := 37; - A_MOVSD: - FResultStorage[Index] := 38; - A_MOVSS: - FResultStorage[Index] := 8; - A_LEA: - FResultStorage[Index] := 9; - A_SUB: - FResultStorage[Index] := 10; - A_SHL: - FResultStorage[Index] := 39; - A_SAL: - FResultStorage[Index] := 11; - A_SETcc: - FResultStorage[Index] := 12; - A_MULX: - FResultStorage[Index] := 40; - A_VBROADCASTF128: - FResultStorage[Index] := 41; - A_VBROADCASTI128: - FResultStorage[Index] := 42; - A_VPERMD: - FResultStorage[Index] := 43; - A_VADDPD: - FResultStorage[Index] := 44; - A_VADDPS: - FResultStorage[Index] := 45; - A_ROUNDPS: - FResultStorage[Index] := 46; - A_ROUNDPD: - FResultStorage[Index] := 47; - A_ROUNDSS: - FResultStorage[Index] := 48; - A_ROUNDSD: - FResultStorage[Index] := 49; - A_CRC32: - FResultStorage[Index] := 50; - A_DPPS: - FResultStorage[Index] := 51; - A_DPPD: - FResultStorage[Index] := 52; - A_VAESDEC: - FResultStorage[Index] := 53; - A_VAESDECLAST: - FResultStorage[Index] := 54; - A_VAESENC: - FResultStorage[Index] := 55; - A_VAESENCLAST: - FResultStorage[Index] := 56; - A_VAESIMC: - FResultStorage[Index] := 57; - A_VAESKEYGENASSIST: - FResultStorage[Index] := 58; - A_VPSHUFB: - FResultStorage[Index] := 59; - A_VPSHUFD: - FResultStorage[Index] := 60; - A_VPSHUFHW: - FResultStorage[Index] := 61; - A_VPSHUFLW: - FResultStorage[Index] := 62; - A_BSF: - FResultStorage[Index] := 63; - A_BSR: - FResultStorage[Index] := 64; - A_BTR: - FResultStorage[Index] := 65; - A_BTS: - FResultStorage[Index] := 66; - A_XOR: - FResultStorage[Index] := 67; - A_ADD: - FResultStorage[Index] := 68; - A_CMP: - FResultStorage[Index] := 69; - A_SHLX: - FResultStorage[Index] := 70; - A_SHRX: - FResultStorage[Index] := 71; - else - FResultStorage[Index] := 0; - end; - end; - -{ TSparseDataEqual3 } - -function TSparseDataEqual3.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 71 sparse labels, equal polling'; - end; - -function TSparseDataEqual3.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - - for X := 0 to 1023 do - if FResultStorage[X] <> ExtremeRange3Expected[X] then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange3Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TSparseDataEqual3.DoTestIteration(Iteration: Integer); - var - X: SmallInt; - begin - X := Iteration and 1023; - DoCaseBlock(X, TInstructionSet(X - 512)) - end; - -{ TSparseDataMOVWeightedl } - -function TSparseDataMOVWeighted3.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 71 sparse labels, 75% particular match'; - end; - -function TSparseDataMOVWeighted3.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange3Expected[X], 2); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMOVWeighted3.DoTestIteration(Iteration: Integer); - var - X: SmallInt; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); - DoCaseBlock(X, P); - end; - -{ TSparseDataMidpointWeighted3 } - -function TSparseDataMidpointWeighted3.TestTitle: shortstring; - begin - Result := 'Domain of 1024, 71 sparse labels, 75% midpoint match'; - end; - -function TSparseDataMidpointWeighted3.WriteResults: Boolean; - var - X, Expected: Word; - begin - Result := True; - - for X := 0 to 1023 do - begin - Expected := IIf((X and $3) = 0, ExtremeRange3Expected[X], 26); - if FResultStorage[X] <> Expected then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - end; - -procedure TSparseDataMidpointWeighted3.DoTestIteration(Iteration: Integer); - var - X: SmallInt; P: TInstructionSet; - begin - X := Iteration and 1023; - P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); - DoCaseBlock(X, P); - end; - - -{ TLinearListDependsOnInput } - -function TLinearListDependsOnInput.TestTitle: shortstring; - begin - Result := 'Linear list depends on input'; - end; - -function TLinearListDependsOnInput.WriteResults: Boolean; - var - X: Word; - begin - Result := True; - if FResultStorage[0] <> 0 then - begin - WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); - Result := False; - Exit; - end; - - for X := 1 to 7 do - if FResultStorage[X] <> (X and $3) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $3, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 8 to 11 do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - if FResultStorage[12] <> $10 then - begin - WriteLn('FAIL - Index 12; expected $10 got $', hexstr(FResultStorage[12], 2)); - Result := False; - Exit; - end; - - for X := 13 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TLinearListDependsOnInput.DoTestIteration(Iteration: Integer); - var - Index: Byte; - begin - Index := Iteration and $FF; - { This helps catch errors where all branches, including else, are skipped } - FResultStorage[Index] := $FF; - case Index of - 1..3: FResultStorage[Index] := Index; - 4..7: FResultStorage[Index] := Index - 4; - 12: FResultStorage[Index] := $10; - else FResultStorage[Index] := 0; - end; - end; - - -{ TCStyleCascade } - -function TCStyleCascade.TestTitle: shortstring; - begin - Result := 'C-style cascade using ''goto'''; - end; - -function TCStyleCascade.WriteResults: Boolean; - var - X: Byte; - begin - Result := True; - for X := 0 to 5 do - if FResultStorage[X] <> ((1 shl X) - 1) then - begin - WriteLn('FAIL - Index ', X, '; expected $', hexstr((1 shl X) - 1, 2), ' got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - - for X := 6 to $FF do - if FResultStorage[X] <> 0 then - begin - WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); - Result := False; - Exit; - end; - end; - -procedure TCStyleCascade.DoTestIteration(Iteration: Integer); - var - X, Tmp: Byte; - label - Set1, Set2, Set3, Set4, Default; - begin - X := Iteration and $FF; - Tmp := 0; - case X of - $1: goto Set1; - $2: goto Set2; - $3: goto Set3; - $4: goto Set4; - $5: Tmp := 16; - else - goto Default; - end; - Set4: - Tmp := Tmp or $8; - Set3: - Tmp := Tmp or $4; - Set2: - Tmp := Tmp or $2; - Set1: - Tmp := Tmp or $1; - Default: - FResultStorage[X] := Tmp; - end; - - -{ Main function } -const - { TCompleteByteRange and descendants - - Entirely-covered jump tree - - 33 labels, no else block; full coverage (all 256 byte values covered) - - Root: values are polled with equal probability - - FirstWeighted: first branch is polled 3 times as often - - LastWeighted: last branch is polled 3 times as often - TAlmostFullByteRange - - Almost full jump tree - 18 labels, else block covers 32 values; 224 byte values covered - - Root: values are polled with equal probability - - FirstWeighted: first branch is polled 3 times as often - - LastWeighted: last branch is polled 3 times as often - } - - TestClasses: array[0..35] of TTestClass = ( - TCompleteByteRange, - TCompleteByteRangeFirstWeighted, - TCompleteByteRangeLastWeighted, - TAlmostFullByteRange, - TAlmostFullByteRangeFirstWeighted, - TAlmostFullByteRangeLastWeighted, - TSingleEntryWithDefault, - TSingleEntryWithDefaultUnlikely, - TSingleEntryWithDefaultWeighted, - TSingleEntryWithElse, - TSingleEntryWithElseUnlikely, - TSingleEntryWithElseWeighted, - TSingleEntryAtZeroWithElse, - TSingleEntryAtMinus1WithDefault, - TSingleEntryAtMinus4WithElse, - TSingleEntryWith0To5RangeWithElse, - TSingleEntryWith0To50RangeWithElse, - TSingleEntryWith1To5RangeWithElse, - TSingleEntryWith1To50RangeWithElse, - TSingleEntryWithMinus1To5RangeWithElse, - TSingleEntryWithMinus1To50RangeWithElse, - TExtremeRange1, - TExtremeRange2, - TExtremeRange3, - TExtremeRange4, - TSparseDataEqual1, - TSparseDataMOVWeighted1, - TSparseDataMidpointWeighted1, - TSparseDataEqual2, - TSparseDataMOVWeighted2, - TSparseDataMidpointWeighted2, - TSparseDataEqual3, - TSparseDataMOVWeighted3, - TSparseDataMidpointWeighted3, - TLinearListDependsOnInput, - TCStyleCascade - ); - -var - CurrentObject: TTestAncestor; - Failed: Boolean; - X: Integer; - SummedUpAverageDuration, AverageDuration : Double; -begin - SummedUpAverageDuration := 0.0; - Failed := False; - WriteLn('Case node compilation and timing test'); - WriteLn('-------------------------------------'); - for X := low(TestClasses) to High(TestClasses) do - begin - try - CurrentObject := TestClasses[X].Create; - try - Write(CurrentObject.TestTitle:56, ' - '); - CurrentObject.Run; - - if CurrentObject.WriteResults then - begin - AverageDuration := ((CurrentObject.RunTime * 1000000000.0) / ITERATIONS); - WriteLn('Pass - average iteration duration: ', AverageDuration:1:3, ' ns'); - SummedUpAverageDuration := SummedUpAverageDuration + AverageDuration; - end - else - { Final average isn't processed if a test failed, so there's no need - to calculate and add the average duration to it } - Failed := True; - - finally - CurrentObject.Free; - end; - except on E: Exception do - begin - WriteLn('Exception "', E.ClassName, '" raised while running test object of class "', TestClasses[X].ClassName, '"'); - Failed := True; - end; - end; - end; - - if Failed then - Halt(1); - - WriteLn(#10'ok'); - WriteLn('- Sum of average durations: ', SummedUpAverageDuration:1:3, ' ns'); - WriteLn('- Overall average duration: ', (SummedUpAverageDuration / Length(TestClasses)):1:3, ' ns'); -end. +{$goto on} +program bcase; + +{$mode objfpc}{$H+} + +uses + SysUtils; + +{ Utility functions } +function GetRealTime(const st: TSystemTime): Real; + begin + Result := st.Hour*3600.0 + st.Minute*60.0 + st.Second + st.MilliSecond/1000.0; + end; + +{$push} +{$warn 5057 off} +function GetRealTime : Real; + var + st:TSystemTime; + begin + GetLocalTime(st); + result:=GetRealTime(st); + end; +{$pop} + +function IIf(Condition: Boolean; TrueRes, FalseRes: Integer): Integer; inline; + begin + if Condition then + Result := TrueRes + else + Result := FalseRes; + end; + +const + ITERATIONS = 33554432; + + AES_S_Box: array[Byte] of Byte = ( + $63, $7c, $77, $7b, $f2, $6b, $6f, $c5, $30, $01, $67, $2b, $fe, $d7, $ab, $76, + $ca, $82, $c9, $7d, $fa, $59, $47, $f0, $ad, $d4, $a2, $af, $9c, $a4, $72, $c0, + $b7, $fd, $93, $26, $36, $3f, $f7, $cc, $34, $a5, $e5, $f1, $71, $d8, $31, $15, + $04, $c7, $23, $c3, $18, $96, $05, $9a, $07, $12, $80, $e2, $eb, $27, $b2, $75, + $09, $83, $2c, $1a, $1b, $6e, $5a, $a0, $52, $3b, $d6, $b3, $29, $e3, $2f, $84, + $53, $d1, $00, $ed, $20, $fc, $b1, $5b, $6a, $cb, $be, $39, $4a, $4c, $58, $cf, + $d0, $ef, $aa, $fb, $43, $4d, $33, $85, $45, $f9, $02, $7f, $50, $3c, $9f, $a8, + $51, $a3, $40, $8f, $92, $9d, $38, $f5, $bc, $b6, $da, $21, $10, $ff, $f3, $d2, + $cd, $0c, $13, $ec, $5f, $97, $44, $17, $c4, $a7, $7e, $3d, $64, $5d, $19, $73, + $60, $81, $4f, $dc, $22, $2a, $90, $88, $46, $ee, $b8, $14, $de, $5e, $0b, $db, + $e0, $32, $3a, $0a, $49, $06, $24, $5c, $c2, $d3, $ac, $62, $91, $95, $e4, $79, + $e7, $c8, $37, $6d, $8d, $d5, $4e, $a9, $6c, $56, $f4, $ea, $65, $7a, $ae, $08, + $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, + $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, + $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, + $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 + ); + + FirstWeighted: array[0..255] of Byte = ( + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, $63, + $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, + $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, + $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, + $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 + ); + + LastWeighted: array[0..255] of Byte = ( + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, $16, + $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, + $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, + $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, + $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 + ); + + AlmostFullExpected: array[0..255] of Byte = ( + $63, $7c, $77, $7b, $f2, $6b, $6f, $c5, $30, $01, $67, $2b, $fe, $d7, $ab, $76, + $ca, $82, $c9, $7d, $fa, $59, $47, $f0, $ad, $d4, $a2, $af, $9c, $a4, $72, $c0, + $b7, $fd, $93, $26, $36, $3f, $f7, $cc, $34, $a5, $e5, $f1, $71, $d8, $31, $15, + $04, $c7, $23, $c3, $18, $96, $05, $9a, $07, $12, $80, $e2, $eb, $27, $b2, $75, + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, + $d0, $ef, $aa, $fb, $43, $4d, $33, $85, $45, $f9, $02, $7f, $50, $3c, $9f, $a8, + $51, $a3, $40, $8f, $92, $9d, $38, $f5, $bc, $b6, $da, $21, $10, $ff, $f3, $d2, + $cd, $0c, $13, $ec, $5f, $97, $44, $17, $c4, $a7, $7e, $3d, $64, $5d, $19, $73, + $60, $81, $4f, $dc, $22, $2a, $90, $88, $46, $ee, $b8, $14, $de, $5e, $0b, $db, + $e0, $32, $3a, $0a, $49, $06, $24, $5c, $c2, $d3, $ac, $62, $91, $95, $e4, $79, + $e7, $c8, $37, $6d, $8d, $d5, $4e, $a9, $6c, $56, $f4, $ea, $65, $7a, $ae, $08, + $ba, $78, $25, $2e, $1c, $a6, $b4, $c6, $e8, $dd, $74, $1f, $4b, $bd, $8b, $8a, + $70, $3e, $b5, $66, $48, $03, $f6, $0e, $61, $35, $57, $b9, $86, $c1, $1d, $9e, + $e1, $f8, $98, $11, $69, $d9, $8e, $94, $9b, $1e, $87, $e9, $ce, $55, $28, $df, + $8c, $a1, $89, $0d, $bf, $e6, $42, $68, $41, $99, $2d, $0f, $b0, $54, $bb, $16 + ); + +type + TInstructionSet = ( { Truncated to 1024 entries } + A_NONE = -512, A_ADC, A_ADD, A_AND, A_BSF, A_BSR, A_BSWAP, A_BT, A_BTC, A_BTR, A_BTS, + A_CALL, A_CBW, A_CDQ, A_CLC, A_CLD, A_CLI, A_CLTS, A_CMC, A_CMP, A_CMPSB, + A_CMPSD, A_CMPSW, A_CMPXCHG, A_CMPXCHG486, A_CMPXCHG8B, A_CPUID, A_CWD, A_CWDE, + A_DEC, A_DIV, A_EMMS, A_ENTER, A_F2XM1, A_FABS, A_FADD, A_FADDP, A_FBLD, A_FBSTP, + A_FCHS, A_FCLEX,A_FCMOVB, A_FCMOVBE, A_FCMOVE, A_FCMOVNB, A_FCMOVNBE, A_FCMOVNE, + A_FCMOVNU, A_FCMOVU, A_FCOM, A_FCOMI, A_FCOMIP, A_FCOMP, A_FCOMPP, A_FCOS, + A_FDECSTP, A_FDISI, A_FDIV, A_FDIVP, A_FDIVR, A_FDIVRP, A_FEMMS, A_FENI, A_FFREE, + A_FIADD, A_FICOM, A_FICOMP, A_FIDIV, A_FIDIVR, A_FILD, A_FIMUL, A_FINCSTP, + A_FINIT, A_FIST, A_FISTP, A_FISTTP, A_FISUB, A_FISUBR, A_FLD, A_FLD1, A_FLDCW, + A_FLDENV, A_FLDL2E, A_FLDL2T, A_FLDLG2, A_FLDLN2, A_FLDPI, A_FLDZ, A_FMUL, + A_FMULP, A_FNCLEX, A_FNDISI, A_FNENI, A_FNINIT, A_FNOP, A_FNSAVE, A_FNSTCW, + A_FNSTENV, A_FNSTSW, A_FPATAN, A_FPREM, A_FPREM1, A_FPTAN, A_FRNDINT, A_FRSTOR, + A_FSAVE, A_FSCALE, A_FSETPM, A_FSIN, A_FSINCOS, A_FSQRT, A_FST, A_FSTCW, + A_FSTENV, A_FSTP, A_FSTSW, A_FSUB, A_FSUBP, A_FSUBR, A_FSUBRP, A_FTST, A_FUCOM, + A_FUCOMI, A_FUCOMIP, A_FUCOMP, A_FUCOMPP, A_FWAIT, A_FXAM, A_FXCH, A_FXTRACT, + A_FYL2X, A_FYL2XP1, A_HLT, A_IBTS, A_ICEBP, A_IDIV, A_IMUL, A_IN, A_INC, A_INSB, + A_INSD, A_INSW, A_INT, A_INT01, A_INT1, A_INT03, A_INT3, A_INVD, A_INVLPG, + A_IRET, A_IRETD, A_IRETW, A_IRETQ, A_JECXZ, A_JRCXZ, A_JMP, A_LAHF, A_LAR, + A_LCALL, A_LEA, A_LEAVE, A_LFS, A_LGDT, A_LGS, A_LIDT, A_LJMP, A_LLDT, A_LMSW, + A_LOADALL, A_LOADALL286, A_LOCK, A_LODSB, A_LODSD, A_LODSW, A_LOOP, A_LOOPE, + A_LOOPNE, A_LOOPNZ, A_LOOPZ, A_LSL, A_LSS, A_LTR, A_MONITOR, A_MOV, A_MOVD, + A_MOVQ, A_MOVSB, A_MOVSD, A_MOVSQ, A_MOVSW, A_MOVSX, A_MOVZX, A_MUL, A_MWAIT, + A_NEG, A_NOP, A_NOT, A_OR, A_OUT, A_OUTSB, A_OUTSD, A_OUTSW, A_PACKSSDW, + A_PACKSSWB, A_PACKUSWB, A_PADDB, A_PADDD, A_PADDSB, A_PADDSIW, A_PADDSW, + A_PADDUSB, A_PADDUSW, A_PADDW, A_PAND, A_PANDN, A_PAVEB, A_PAVGUSB, A_PCMPEQB, + A_PCMPEQD, A_PCMPEQW, A_PCMPGTB, A_PCMPGTD, A_PCMPGTW, A_PDISTIB, A_PF2ID, + A_PFACC, A_PFADD, A_PFCMPEQ, A_PFCMPGE, A_PFCMPGT, A_PFMAX, A_PFMIN, A_PFMUL, + A_PFRCP, A_PFRCPIT1, A_PFRCPIT2, A_PFRSQIT1, A_PFRSQRT, A_PFSUB, A_PFSUBR, + A_PI2FD, A_PMACHRIW, A_PMADDWD, A_PMAGW, A_PMULHRIW, A_PMULHRWA, A_PMULHRWC, + A_PMULHW, A_PMULLW, A_PMVGEZB, A_PMVLZB, A_PMVNZB, A_PMVZB, A_POP, A_POPF, + A_POPFW, A_POPFQ, A_POR, A_PREFETCH, A_PREFETCHW, A_PSLLD, A_PSLLDQ, A_PSLLQ, + A_PSLLW, A_PSRAD, A_PSRAW, A_PSRLD, A_PSRLQ, A_PSRLW, A_PSUBB, A_PSUBD, A_PSUBSB, + A_PSUBSIW, A_PSUBSW, A_PSUBUSB, A_PSUBUSW, A_PSUBW, A_PUNPCKHBW, A_PUNPCKHDQ, + A_PUNPCKHWD, A_PUNPCKLBW, A_PUNPCKLDQ, A_PUNPCKLWD, A_PUSH, A_PUSHF, A_PUSHFW, + A_PUSHFQ, A_PXOR, A_RCL, A_RCR, A_RDSHR, A_RDMSR, A_RDPMC, A_RDTSC, A_REP, + A_REPE, A_REPNE, A_REPNZ, A_REPZ, A_RET, A_RETF, A_RETN, A_RETW, A_RETFW, + A_RETNW, A_RETFD, A_RETQ, A_RETFQ, A_RETNQ, A_ROL, A_ROR, A_RSDC, A_RSLDT, A_RSM, + A_SAHF, A_SAL, A_SAR, A_SBB, A_SCASB, A_SCASD, A_SCASQ, A_SCASW, A_SEGCS, + A_SEGDS, A_SEGES, A_SEGFS, A_SEGGS, A_SEGSS, A_SGDT, A_SHL, A_SHLD, A_SHR, + A_SHRD, A_SIDT, A_SLDT, A_SMI, A_SMINT, A_SMINTOLD, A_SMSW, A_STC, A_STD, A_STI, + A_STOSB, A_STOSD, A_STOSW, A_STR, A_SUB, A_SVDC, A_SVLDT, A_SVTS, A_SYSCALL, + A_SYSENTER, A_SYSEXIT, A_SYSRET, A_TEST, A_UD1, A_UD2, A_UMOV, A_VERR, A_VERW, + A_WAIT, A_WBINVD, A_WRSHR, A_WRMSR, A_XADD, A_XBTS, A_XCHG, A_XLAT, A_XLATB, + A_XOR, A_XSTORE, A_XCRYPTECB, A_XCRYPTCBC, A_XCRYPTCFB, A_XCRYPTOFB, A_CMOVcc, + A_Jcc, A_SETcc, A_MOVS, A_CMPS, A_SCAS, A_LODS, A_STOS, A_INS, A_OUTS, A_ADDPS, + A_ADDSS, A_ANDNPS, A_ANDPS, A_CMPEQPS, A_CMPEQSS, A_CMPLEPS, A_CMPLESS, + A_CMPLTPS, A_CMPLTSS, A_CMPNEQPS, A_CMPNEQSS, A_CMPNLEPS, A_CMPNLESS, + A_CMPNLTPS, A_CMPNLTSS, A_CMPORDPS, A_CMPORDSS, A_CMPUNORDPS, A_CMPUNORDSS, + A_CMPPS, A_CMPSS, A_COMISS, A_CVTPI2PS, A_CVTPS2PI, A_CVTSI2SS, A_CVTSS2SI, + A_CVTTPS2PI, A_CVTTSS2SI, A_DIVPS, A_DIVSS, A_LDMXCSR, A_MAXPS, A_MAXSS, A_MINPS, + A_MINSS, A_MOVAPS, A_MOVHPS, A_MOVLHPS, A_MOVLPS, A_MOVHLPS, A_MOVMSKPS, + A_MOVNTPS, A_MOVSS, A_MOVUPS, A_MULPS, A_MULSS, A_ORPS, A_RCPPS, A_RCPSS, + A_RSQRTPS, A_RSQRTSS, A_SHUFPS, A_SQRTPS, A_SQRTSS, A_STMXCSR, A_SUBPS, A_SUBSS, + A_UCOMISS, A_UNPCKHPS, A_UNPCKLPS, A_XORPS, A_FXRSTOR, A_FXSAVE, A_PREFETCHNTA, + A_PREFETCHT0, A_PREFETCHT1, A_PREFETCHT2, A_SFENCE, A_MASKMOVQ, A_MOVNTQ, + A_PAVGB, A_PAVGW, A_PEXTRW, A_PINSRW, A_PMAXSW, A_PMAXUB, A_PMINSW, A_PMINUB, + A_PMOVMSKB, A_PMULHUW, A_PSADBW, A_PSHUFW, A_PFNACC, A_PFPNACC, A_PI2FW, A_PF2IW, + A_PSWAPD, A_FFREEP, A_MASKMOVDQU, A_CLFLUSH, A_MOVNTDQ, A_MOVNTI, A_MOVNTPD, + A_PAUSE, A_LFENCE, A_MFENCE, A_MOVDQA, A_MOVDQU, A_MOVDQ2Q, A_MOVQ2DQ, A_PADDQ, + A_PMULUDQ, A_PSHUFD, A_PSHUFHW, A_PSHUFLW, A_PSRLDQ, A_PSUBQ, A_PUNPCKHQDQ, + A_PUNPCKLQDQ, A_ADDPD, A_ADDSD, A_ANDNPD, A_ANDPD, A_CMPEQPD, A_CMPEQSD, + A_CMPLEPD, A_CMPLESD, A_CMPLTPD, A_CMPLTSD, A_CMPNEQPD, A_CMPNEQSD, A_CMPNLEPD, + A_CMPNLESD, A_CMPNLTPD, A_CMPNLTSD, A_CMPORDPD, A_CMPORDSD, A_CMPUNORDPD, + A_CMPUNORDSD, A_CMPPD, A_COMISD, A_CVTDQ2PD, A_CVTDQ2PS, A_CVTPD2DQ, A_CVTPD2PI, + A_CVTPD2PS, A_CVTPI2PD, A_CVTPS2DQ, A_CVTPS2PD, A_CVTSD2SI, A_CVTSD2SS, + A_CVTSI2SD, A_CVTSS2SD, A_CVTTPD2PI, A_CVTTPD2DQ, A_CVTTPS2DQ, A_CVTTSD2SI, + A_DIVPD, A_DIVSD, A_MAXPD, A_MAXSD, A_MINPD, A_MINSD, A_MOVAPD, A_MOVHPD, + A_MOVLPD, A_MOVMSKPD, A_MOVUPD, A_MULPD, A_MULSD, A_ORPD, A_SHUFPD, A_SQRTPD, + A_SQRTSD, A_SUBPD, A_SUBSD, A_UCOMISD, A_UNPCKHPD, A_UNPCKLPD, A_XORPD, + A_ADDSUBPD, A_ADDSUBPS, A_HADDPD, A_HADDPS, A_HSUBPD, A_HSUBPS, A_LDDQU, + A_MOVDDUP, A_MOVSHDUP, A_MOVSLDUP, A_VMREAD, A_VMWRITE, A_VMCALL, A_VMLAUNCH, + A_VMRESUME, A_VMXOFF, A_VMXON, A_VMCLEAR, A_VMPTRLD, A_VMPTRST, A_VMRUN, + A_VMMCALL, A_VMLOAD, A_VMSAVE, A_STGI, A_CLGI, A_SKINIT, A_INVLPGA, A_MONTMUL, + A_XSHA1, A_XSHA256, A_DMINT, A_RDM, A_MOVABS, A_MOVSXD, A_CQO, A_CDQE, + A_CMPXCHG16B, A_MOVNTSS, A_MOVNTSD, A_INSERTQ, A_EXTRQ, A_LZCNT, A_PABSB, + A_PABSW, A_PABSD, A_PALIGNR, A_PHADDW, A_PHADDD, A_PHADDSW, A_PHSUBW, A_PHSUBD, + A_PHSUBSW, A_PMADDUBSW, A_PMULHRSW, A_PSHUFB, A_PSIGNB, A_PSIGNW, A_PSIGND, + A_BLENDPS, A_BLENDPD, A_BLENDVPS, A_BLENDVPD, A_DPPS, A_DPPD, A_EXTRACTPS, + A_INSERTPS, A_MOVNTDQA, A_MPSADBW, A_PACKUSDW, A_PBLENDVB, A_PBLENDW, A_PCMPEQQ, + A_PEXTRB, A_PEXTRD, A_PEXTRQ, A_PHMINPOSUW, A_PINSRB, A_PINSRD, A_PINSRQ, A_PMAXSB, + A_PMAXSD, A_PMAXUD, A_PMAXUW, A_PMINSB, A_PMINSD, A_PMINUW, A_PMINUD, A_PMOVSXBW, + A_PMOVSXBD, A_PMOVSXBQ, A_PMOVSXWD, A_PMOVSXWQ, A_PMOVSXDQ, A_PMOVZXBW, A_PMOVZXBD, + A_PMOVZXBQ, A_PMOVZXWD, A_PMOVZXWQ, A_PMOVZXDQ, A_PMULDQ, A_PMULLD, A_PTEST, + A_ROUNDPS, A_ROUNDPD, A_ROUNDSS, A_ROUNDSD, A_CRC32, A_PCMPESTRI, A_PCMPESTRM, + A_PCMPISTRI, A_PCMPISTRM, A_PCMPGTQ, A_POPCNT, A_AESENC, A_AESENCLAST, A_AESDEC, + A_AESDECLAST, A_AESIMC, A_AESKEYGENASSIST, A_RDTSCP, A_STOSQ, A_LODSQ, A_CMPSQ, + A_VADDPD, A_VADDPS, A_VADDSD, A_VADDSS, A_VADDSUBPD, A_VADDSUBPS, A_VAESDEC, + A_VAESDECLAST, A_VAESENC, A_VAESENCLAST, A_VAESIMC, A_VAESKEYGENASSIST, A_VANDNPD, + A_VANDNPS, A_VANDPD, A_VANDPS, A_VBLENDPD, A_VBLENDPS, A_VBLENDVPD, A_VBLENDVPS, + A_VBROADCASTF128, A_VBROADCASTSD, A_VBROADCASTSS, A_VCMPEQPS, A_VCMPLTPS, + A_VCMPLEPS, A_VCMPUNORDPS, A_VCMPNEQPS, A_VCMPNLTPS, A_VCMPNLEPS, A_VCMPORDPS, + A_VCMPEQ_UQPS, A_VCMPNGEPS, A_VCMPNGTPS, A_VCMPFALSEPS, A_VCMPNEQ_OQPS, + A_VCMPGEPS, A_VCMPGTPS, A_VCMPTRUEPS, A_VCMPEQ_OSPS, A_VCMPLT_OQPS, A_VCMPLE_OQPS, + A_VCMPUNORD_SPS, A_VCMPNEQ_USPS, A_VCMPNLT_UQPS, A_VCMPNLE_UQPS, A_VCMPORD_SPS, + A_VCMPEQ_USPS, A_VCMPNGE_UQPS, A_VCMPNGT_UQPS, A_VCMPFALSE_OSPS, A_VCMPNEQ_OSPS, + A_VCMPGE_OQPS, A_VCMPGT_OQPS, A_VCMPTRUE_USPS, A_VCMPEQPD, A_VCMPLTPD, A_VCMPLEPD, + A_VCMPUNORDPD, A_VCMPNEQPD, A_VCMPNLTPD, A_VCMPNLEPD, A_VCMPORDPD, A_VCMPEQ_UQPD, + A_VCMPNGEPD, A_VCMPNGTPD, A_VCMPFALSEPD, A_VCMPNEQ_OQPD, A_VCMPGEPD, A_VCMPGTPD, + A_VCMPTRUEPD, A_VCMPEQ_OSPD, A_VCMPLT_OQPD, A_VCMPLE_OQPD, A_VCMPUNORD_SPD, + A_VCMPNEQ_USPD, A_VCMPNLT_UQPD, A_VCMPNLE_UQPD, A_VCMPORD_SPD, A_VCMPEQ_USPD, + A_VCMPNGE_UQPD, A_VCMPNGT_UQPD, A_VCMPFALSE_OSPD, A_VCMPNEQ_OSPD, A_VCMPGE_OQPD, + A_VCMPGT_OQPD, A_VCMPTRUE_USPD, A_VCMPPD, A_VCMPPS, A_VCMPSD, A_VCMPSS, A_VCOMISD, + A_VCOMISS, A_VCVTDQ2PD, A_VCVTDQ2PS, A_VCVTPD2DQ, A_VCVTPD2PS, A_VCVTPS2DQ, + A_VCVTPS2PD, A_VCVTSD2SI, A_VCVTSD2SS, A_VCVTSI2SD, A_VCVTSI2SS, A_VCVTSS2SD, + A_VCVTSS2SI, A_VCVTTPD2DQ, A_VCVTTPS2DQ, A_VCVTTSD2SI, A_VCVTTSS2SI, A_VDIVPD, + A_VDIVPS, A_VDIVSD, A_VDIVSS, A_VDPPD, A_VDPPS, A_VEXTRACTF128, A_VEXTRACTPS, + A_VHADDPD, A_VHADDPS, A_VHSUBPD, A_VHSUBPS, A_VINSERTF128, A_VINSERTPS, A_VLDDQU, + A_VLDMXCSR, A_VMASKMOVDQU, A_VMASKMOVPD, A_VMASKMOVPS, A_VMAXPD, A_VMAXPS, + A_VMAXSD, A_VMAXSS, A_VMINPD, A_VMINPS, A_VMINSD, A_VMINSS, A_VMOVAPD, A_VMOVAPS, + A_VMOVD, A_VMOVDDUP, A_VMOVDQA, A_VMOVDQU, A_VMOVHLPS, A_VMOVHPD, A_VMOVHPS, + A_VMOVLHPS, A_VMOVLPD, A_VMOVLPS, A_VMOVMSKPD, A_VMOVMSKPS, A_VMOVNTDQ, + A_VMOVNTDQA, A_VMOVNTPD, A_VMOVNTPS, A_VMOVQ, A_VMOVSD, A_VMOVSHDUP, A_VMOVSLDUP, + A_VMOVSS, A_VMOVUPD, A_VMOVUPS, A_VMPSADBW, A_VMULPD, A_VMULPS, A_VMULSD, + A_VMULSS, A_VORPD, A_VORPS, A_VPABSB, A_VPABSD, A_VPABSW, A_VPACKSSDW, + A_VPACKSSWB, A_VPACKUSDW, A_VPACKUSWB, A_VPADDB, A_VPADDD, A_VPADDQ, A_VPADDSB, + A_VPADDSW, A_VPADDUSB, A_VPADDUSW, A_VPADDW, A_VPALIGNR, A_VPAND, A_VPANDN, + A_VPAVGB, A_VPAVGW, A_VPBLENDVB, A_VPBLENDW, A_VPCLMULQDQ, A_VPCMPEQB, A_VPCMPEQD, + A_VPCMPEQQ, A_VPCMPEQW, A_VPCMPESTRI, A_VPCMPESTRM, A_VPCMPGTB, A_VPCMPGTD, + A_VPCMPGTQ, A_VPCMPGTW, A_VPCMPISTRI, A_VPCMPISTRM, A_VPERM2F128, A_VPERMILPD, + A_VPERMILPS, A_VPEXTRB, A_VPEXTRD, A_VPEXTRQ, A_VPEXTRW, A_VPHADDD, A_VPHADDSW, + A_VPHADDW, A_VPHMINPOSUW, A_VPHSUBD, A_VPHSUBSW, A_VPHSUBW, A_VPINSRB, A_VPINSRD, + A_VPINSRQ, A_VPINSRW, A_VPMADDUBSW, A_VPMADDWD, A_VPMAXSB, A_VPMAXSD, A_VPMAXSW, + A_VPMAXUB, A_VPMAXUD, A_VPMAXUW, A_VPMINSB, A_VPMINSD, A_VPMINSW, A_VPMINUB, + A_VPMINUD, A_VPMINUW, A_VPMOVMSKB, A_VPMOVSXBD, A_VPMOVSXBQ, A_VPMOVSXBW, + A_VPMOVSXDQ, A_VPMOVSXWD, A_VPMOVSXWQ, A_VPMOVZXBD, A_VPMOVZXBQ, A_VPMOVZXBW, + A_VPMOVZXDQ, A_VPMOVZXWD, A_VPMOVZXWQ, A_VPMULDQ, A_VPMULHRSW, A_VPMULHUW, + A_VPMULHW, A_VPMULLD, A_VPMULLW, A_VPMULUDQ, A_VPOR, A_VPSADBW, A_VPSHUFB, + A_VPSHUFD, A_VPSHUFHW, A_VPSHUFLW, A_VPSIGNB, A_VPSIGND, A_VPSIGNW, A_VPSLLD, + A_VPSLLDQ, A_VPSLLQ, A_VPSLLW, A_VPSRAD, A_VPSRAW, A_VPSRLD, A_VPSRLDQ, A_VPSRLQ, + A_VPSRLW, A_VPSUBB, A_VPSUBD, A_VPSUBQ, A_VPSUBSB, A_VPSUBSW, A_VPSUBUSB, + A_VPSUBUSW, A_VPSUBW, A_VPTEST, A_VPUNPCKHBW, A_VPUNPCKHDQ, A_VPUNPCKHQDQ, + A_VPUNPCKHWD, A_VPUNPCKLBW, A_VPUNPCKLDQ, A_VPUNPCKLQDQ, A_VPUNPCKLWD, A_VPXOR, + A_VRCPPS, A_VRCPSS, A_VROUNDPD, A_VROUNDPS, A_VROUNDSD, A_VROUNDSS, A_VRSQRTPS, + A_VRSQRTSS, A_VSHUFPD, A_VSHUFPS, A_VSQRTPD, A_VSQRTPS, A_VSQRTSD, A_VSQRTSS, + A_VSTMXCSR, A_VSUBPD, A_VSUBPS, A_VSUBSD, A_VSUBSS, A_VTESTPD, A_VTESTPS, + A_VUCOMISD, A_VUCOMISS, A_VUNPCKHPD, A_VUNPCKHPS, A_VUNPCKLPD, A_VUNPCKLPS, + A_VXORPD, A_VXORPS, A_VZEROALL, A_VZEROUPPER, A_ANDN, A_BEXTR, A_TZCNT, A_BZHI, + A_MULX, A_PDEP, A_PEXT, A_RORX, A_SARX, A_SHLX, A_SHRX, A_VBROADCASTI128, + A_VEXTRACTI128, A_VINSERTI128, A_VPBLENDD, A_VPBROADCASTB, A_VPBROADCASTD, + A_VPBROADCASTQ, A_VPBROADCASTW, A_VPERM2I128, A_VPERMD); + +const + ExtremeRange1Expected: array[0..1023] of Byte = ( + $00, $00, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 0 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } + $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $08, $00, $00, $03, $03, { 176 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, $00, $00, { 320 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } + $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } + $00, $00, $00, $00, $00, $05, $00, $00, $00, $00, $00, $00, $08, $05, $00, $07, { 416 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } + $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $05, $00, $00, $00, $05, { 528 } + $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 608 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, { 672 } + $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, $00, { 688 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } + $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, { 784 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } + $04, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } + $00, $00, $00, $08, $00, $00, $08, $04, $04, $00, $00, $00, $06, $06, $06, $06, { 832 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 928 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, { 976 } + $00, $00, $00, $00, $00, $00, $00, $06, $06, $00, $00, $00, $00, $00, $00, $00, { 992 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 { 1008 } + ); + + ExtremeRange2Expected: array[0..1023] of Byte = ( + $00, $00, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 0 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } + $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $26, $00, $00, $0D, $03, { 176 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $27, $00, $00, $00, $00, $00, $00, { 320 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } + $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } + $00, $00, $00, $00, $00, $12, $00, $00, $00, $00, $00, $00, $08, $05, $00, $22, { 416 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } + $23, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $11, $00, $00, $00, $13, { 528 } + $00, $21, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 608 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $1A, $1B, $00, $00, $00, $00, { 672 } + $00, $00, $00, $00, $00, $00, $1C, $1D, $00, $00, $00, $00, $00, $00, $00, $00, { 688 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } + $00, $00, $00, $00, $00, $00, $00, $14, $15, $00, $00, $00, $00, $00, $00, $00, { 784 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } + $0F, $0E, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } + $00, $00, $00, $24, $00, $00, $25, $04, $10, $00, $00, $00, $18, $19, $1E, $1F, { 832 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 928 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $16, $17, $00, { 976 } + $00, $00, $00, $00, $00, $00, $00, $20, $06, $00, $00, $00, $00, $00, $00, $00, { 992 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 { 1008 } + ); + + ExtremeRange3Expected: array[0..1023] of Byte = ( + $00, $00, $44, $01, $3F, $40, $00, $00, $00, $41, $42, $00, $00, $00, $00, $00, { 0 } + $00, $00, $00, $45, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 16 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 32 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 48 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 64 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 80 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 96 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 112 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 128 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $09, { 144 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 160 } + $00, $00, $00, $00, $00, $00, $00, $02, $00, $00, $00, $26, $00, $00, $0D, $03, { 176 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 192 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 208 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 224 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 240 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 256 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 272 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 288 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0B, $00, $00, $00, $00, { 304 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $27, $00, $00, $00, $00, $00, $00, { 320 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $0A, $00, $00, $00, $00, $00, { 336 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 352 } + $00, $43, $00, $00, $00, $00, $00, $00, $00, $0C, $00, $00, $00, $00, $00, $00, { 368 } + $00, $00, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 384 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 400 } + $00, $00, $00, $00, $00, $12, $00, $00, $00, $00, $00, $00, $08, $05, $00, $22, { 416 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 432 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 448 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 464 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 480 } + $23, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 496 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 512 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $11, $00, $00, $00, $13, { 528 } + $00, $21, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 544 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 560 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 576 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 592 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $33, $34, $00, $00, $00, { 608 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 624 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 640 } + $00, $00, $00, $2E, $2F, $30, $31, $32, $00, $00, $00, $00, $00, $00, $00, $00, { 656 } + $00, $00, $00, $00, $00, $00, $00, $00, $2C, $2D, $1A, $1B, $00, $00, $35, $36, { 672 } + $37, $38, $39, $3A, $00, $00, $1C, $1D, $00, $00, $00, $00, $29, $00, $00, $00, { 688 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 704 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 720 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 736 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 752 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 768 } + $00, $00, $00, $00, $00, $00, $00, $14, $15, $00, $00, $00, $00, $00, $00, $00, { 784 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 800 } + $0F, $0E, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 816 } + $00, $00, $00, $24, $00, $00, $25, $04, $10, $00, $00, $00, $18, $19, $1E, $1F, { 832 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 848 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 864 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 880 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 896 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 912 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $3B, $3C, $3D, $3E, $00, $00, $00, { 928 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 944 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, { 960 } + $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $16, $17, $00, { 976 } + $00, $00, $00, $00, $00, $00, $00, $20, $06, $00, $00, $00, $00, $00, $00, $28, { 992 } + $00, $00, $00, $00, $46, $47, $2A, $00, $00, $00, $00, $00, $00, $00, $00, $2B { 1008 } + ); + +{ TTestAncestor } +type + TTestAncestor = class + private + FStartTime: Real; + FEndTime: Real; + FAvgTime: Real; + procedure SetStartTime; + procedure SetEndTime; + protected + procedure DoTestIteration(Iteration: Integer); virtual; abstract; + public + constructor Create; virtual; + destructor Destroy; override; + procedure Run; + function TestTitle: shortstring; virtual; abstract; + function WriteResults: Boolean; virtual; abstract; + property RunTime: Real read FAvgTime; + end; + + TTestClass = class of TTestAncestor; + + TByteTest = class(TTestAncestor) + protected + FResultStorage: array[Byte] of Byte; + end; + + TWordTest = class(TTestAncestor) + protected + FResultStorage: array[Word] of Byte; + end; + + TMappedTest = class(TByteTest) + protected + procedure DoMapping(Index, Input: Integer); virtual; abstract; + end; + + TCompleteByteRange = class(TMappedTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + procedure DoMapping(Index, Input: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TCompleteByteRangeFirstWeighted = class(TCompleteByteRange) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TCompleteByteRangeLastWeighted = class(TCompleteByteRange) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TAlmostFullByteRange = class(TMappedTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + procedure DoMapping(Index, Input: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TAlmostFullByteRangeFirstWeighted = class(TAlmostFullByteRange) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TAlmostFullByteRangeLastWeighted = class(TAlmostFullByteRange) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithDefault = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithDefaultUnlikely = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithDefaultWeighted = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithElse = class(TSingleEntryWithDefault) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + end; + + TSingleEntryWithElseUnlikely = class(TSingleEntryWithDefaultUnlikely) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + end; + + TSingleEntryWithElseWeighted = class(TSingleEntryWithDefaultWeighted) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + end; + + TSingleEntryAtZeroWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryAtMinus1WithDefault = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryAtMinus4WithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWith0To5RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWith0To50RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWith1To5RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWith1To50RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithMinus1To5RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSingleEntryWithMinus1To50RangeWithElse = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TExtremeRange1 = class(TWordTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TExtremeRange2 = class(TWordTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TExtremeRange3 = class(TWordTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TExtremeRange4 = class(TWordTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataTest1 = class(TWordTest) + protected + procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; + end; + + TSparseDataEqual1 = class(TSparseDataTest1) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMOVWeighted1 = class(TSparseDataTest1) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMidpointWeighted1 = class(TSparseDataTest1) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataTest2 = class(TWordTest) + protected + procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; + end; + + TSparseDataEqual2 = class(TSparseDataTest2) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMOVWeighted2 = class(TSparseDataTest2) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMidpointWeighted2 = class(TSparseDataTest2) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataTest3 = class(TWordTest) + protected + procedure DoCaseBlock(Index: Integer; Input: TInstructionSet); inline; + end; + + TSparseDataEqual3 = class(TSparseDataTest3) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMOVWeighted3 = class(TSparseDataTest3) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TSparseDataMidpointWeighted3 = class(TSparseDataTest3) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TLinearListDependsOnInput = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + + TCStyleCascade = class(TByteTest) + protected + procedure DoTestIteration(Iteration: Integer); override; + public + function TestTitle: shortstring; override; + function WriteResults: Boolean; override; + end; + +{ TTestAncestor } +constructor TTestAncestor.Create; + begin + FStartTime := 0; + FEndTime := 0; + FAvgTime := 0; + end; + +destructor TTestAncestor.Destroy; + begin + inherited Destroy; + end; + +procedure TTestAncestor.SetStartTime; + begin + FStartTime := GetRealTime(); + end; + +procedure TTestAncestor.SetEndTime; + begin + FEndTime := GetRealTime(); + if FEndTime < FStartTime then { Happens if the test runs past midnight } + FEndTime := FEndTime + 86400.0; + end; + +procedure TTestAncestor.Run; + var + X: Integer; + begin + SetStartTime; + for X := 0 to ITERATIONS - 1 do + DoTestIteration(X); + + SetEndTime; + + FAvgTime := FEndTime - FStartTime; + end; + +{ TCompleteByteRange } +function TCompleteByteRange.TestTitle: shortstring; + begin + Result := 'Byte domain, entirely covered; equal polling'; + end; + +function TCompleteByteRange.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> AES_S_Box[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(AES_S_Box[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TCompleteByteRange.DoMapping(Index, Input: Integer); + begin + case Input of + { First row of S-Box (except zero) } + $00: FResultStorage[Index] := $63; + $01: FResultStorage[Index] := $7c; + $02: FResultStorage[Index] := $77; + $03: FResultStorage[Index] := $7b; + $04: FResultStorage[Index] := $f2; + $05: FResultStorage[Index] := $6b; + $06: FResultStorage[Index] := $6f; + $07: FResultStorage[Index] := $c5; + $08: FResultStorage[Index] := $30; + $09: FResultStorage[Index] := $01; + $0A: FResultStorage[Index] := $67; + $0B: FResultStorage[Index] := $2b; + $0C: FResultStorage[Index] := $fe; + $0D: FResultStorage[Index] := $d7; + $0E: FResultStorage[Index] := $ab; + $0F: FResultStorage[Index] := $76; + {Last row of S-Box } + $F0: FResultStorage[Index] := $8c; + $F1: FResultStorage[Index] := $a1; + $F2: FResultStorage[Index] := $89; + $F3: FResultStorage[Index] := $0d; + $F4: FResultStorage[Index] := $bf; + $F5: FResultStorage[Index] := $e6; + $F6: FResultStorage[Index] := $42; + $F7: FResultStorage[Index] := $68; + $F8: FResultStorage[Index] := $41; + $F9: FResultStorage[Index] := $99; + $FA: FResultStorage[Index] := $2d; + $FB: FResultStorage[Index] := $0f; + $FC: FResultStorage[Index] := $b0; + $FD: FResultStorage[Index] := $54; + $FE: FResultStorage[Index] := $bb; + $FF: FResultStorage[Index] := $16; + { Everything else } + $10..$EF: FResultStorage[Index] := AES_S_Box[Input]; + end; + end; + +procedure TCompleteByteRange.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + DoMapping(Input, Input); + end; + +{ TCompleteByteRangeFirstWeighted } + +function TCompleteByteRangeFirstWeighted.TestTitle: shortstring; + begin + Result := 'Byte domain, entirely covered; first weighted'; + end; + +function TCompleteByteRangeFirstWeighted.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> FirstWeighted[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(FirstWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TCompleteByteRangeFirstWeighted.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + if Input < $C0 then + DoMapping(Input, 0) + else + DoMapping(Input, Input); + end; + +{ TCompleteByteRangeLastWeighted } + +function TCompleteByteRangeLastWeighted.TestTitle: shortstring; + begin + Result := 'Byte domain, entirely covered; last weighted'; + end; + +function TCompleteByteRangeLastWeighted.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> LastWeighted[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(LastWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TCompleteByteRangeLastWeighted.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + if Input < $C0 then + DoMapping(Input, $FF) + else + DoMapping(Input, Input); + end; + +{ TAlmostFullByteRange } + +function TAlmostFullByteRange.TestTitle: shortstring; + begin + Result := 'Byte domain, almost entirely covered; equal polling'; + end; + +function TAlmostFullByteRange.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> AlmostFullExpected[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(AlmostFullExpected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TAlmostFullByteRange.DoMapping(Index, Input: Integer); + begin + case Input of + { First row of S-Box } + $00: FResultStorage[Index] := $63; + $01: FResultStorage[Index] := $7c; + $02: FResultStorage[Index] := $77; + $03: FResultStorage[Index] := $7b; + $04: FResultStorage[Index] := $f2; + $05: FResultStorage[Index] := $6b; + $06: FResultStorage[Index] := $6f; + $07: FResultStorage[Index] := $c5; + $08: FResultStorage[Index] := $30; + $09: FResultStorage[Index] := $01; + $0A: FResultStorage[Index] := $67; + $0B: FResultStorage[Index] := $2b; + $0C: FResultStorage[Index] := $fe; + $0D: FResultStorage[Index] := $d7; + $0E: FResultStorage[Index] := $ab; + $0F: FResultStorage[Index] := $76; + { Other rows } + $10..$3F: FResultStorage[Index] := AES_S_Box[Input]; + $60..$FF: FResultStorage[Index] := AES_S_Box[Input]; + { Zeroed rows } + else FResultStorage[Index] := $00; + end; + end; + +procedure TAlmostFullByteRange.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + DoMapping(Input, Input); + end; + +{ TAlmostFullByteRangeFirstWeighted } + +function TAlmostFullByteRangeFirstWeighted.TestTitle: shortstring; + begin + Result := 'Byte domain, almost entirely covered; first weighted'; + end; + +function TAlmostFullByteRangeFirstWeighted.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> FirstWeighted[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(FirstWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TAlmostFullByteRangeFirstWeighted.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + if Input < $C0 then + DoMapping(Input, 0) + else + DoMapping(Input, Input); + end; + +{ TAlmostFullByteRangeLastWeighted } + +function TAlmostFullByteRangeLastWeighted.TestTitle: shortstring; + begin + Result := 'Byte domain, almost entirely covered; last weighted'; + end; + +function TAlmostFullByteRangeLastWeighted.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> LastWeighted[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(LastWeighted[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TAlmostFullByteRangeLastWeighted.DoTestIteration(Iteration: Integer); + var + Input: Byte; + begin + Input := Iteration and $FF; + if Input < $C0 then + DoMapping(Input, $FF) + else + DoMapping(Input, Input); + end; + +{ TSingleEntryWithDefault } +function TSingleEntryWithDefault.TestTitle: shortstring; + begin + Result := 'Single entry with default value; 1/256 match chance'; + end; + +function TSingleEntryWithDefault.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> IIf(X = 71, 1, 0) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(X = 71, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWithDefault.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + FResultStorage[Index] := 0; + case Index of + 71: FResultStorage[Index] := 1; + end; + end; + +{ TSingleEntryWithDefaultUnlikely } + +function TSingleEntryWithDefaultUnlikely.TestTitle: shortstring; + begin + Result := 'Single entry with default value; 75% match chance'; + end; + +function TSingleEntryWithDefaultUnlikely.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> IIf(((X and $2) shr 1) or (X and $1) = 1, 1, 0) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(((X and $2) shr 1) or (X and $1) = 1, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWithDefaultUnlikely.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + FResultStorage[Index] := 0; + case ((Index and $2) shr 1) or (Index and $1) of + 1: FResultStorage[Index] := 1; + end; + end; + +{ TSingleEntryWithDefaultWeighted } + +function TSingleEntryWithDefaultWeighted.TestTitle: shortstring; + begin + Result := 'Single entry with default value; 25% match chance'; + end; + +function TSingleEntryWithDefaultWeighted.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + + for X := 0 to 255 do + if FResultStorage[X] <> IIf(((X and $2) shr 1) and (X and $1) = 1, 1, 0) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(IIf(((X and $2) shr 1) and (X and $1) = 1, 1, 0), 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWithDefaultWeighted.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + FResultStorage[Index] := 0; + case ((Index and $2) shr 1) and (Index and $1) of + 1: FResultStorage[Index] := 1; + end; + end; + +{ TSingleEntryWithElse } +function TSingleEntryWithElse.TestTitle: shortstring; + begin + Result := 'Single entry with else block; 1/256 match chance'; + end; + +procedure TSingleEntryWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 71: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryWithElseUnlikely } +function TSingleEntryWithElseUnlikely.TestTitle: shortstring; + begin + Result := 'Single entry with else block; 75% match chance'; + end; + +procedure TSingleEntryWithElseUnlikely.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case ((Index and $2) shr 1) or (Index and $1) of + 1: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryWithElseWeighted } + +function TSingleEntryWithElseWeighted.TestTitle: shortstring; + begin + Result := 'Single entry with else block; 25% match chance'; + end; + +procedure TSingleEntryWithElseWeighted.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case ((Index and $2) shr 1) and (Index and $1) of + 1: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryAtZeroWithElse } + +function TSingleEntryAtZeroWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "0:" and else block'; + end; + +function TSingleEntryAtZeroWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + if FResultStorage[0] <> 1 then + begin + WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryAtZeroWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 0: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryAtMinus1WithDefault } + +function TSingleEntryAtMinus1WithDefault.TestTitle: shortstring; + begin + Result := 'Single entry of "-1:" with default value'; + end; + +function TSingleEntryAtMinus1WithDefault.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to $FE do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[255] <> 1 then + begin + WriteLn('FAIL - Index 255; expected $01 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryAtMinus1WithDefault.DoTestIteration(Iteration: Integer); + var + Index: ShortInt; + begin + Index := ShortInt(Iteration and $FF); + FResultStorage[Byte(Index)] := 0; + case Index of + -1: FResultStorage[255] := 1; + end; + end; + +{ TSingleEntryAtMinus4WithElse } + +function TSingleEntryAtMinus4WithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "-4:" and else block'; + end; + +function TSingleEntryAtMinus4WithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + for X := 0 to 251 do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[252] <> 1 then + begin + WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[252], 2)); + Result := False; + Exit; + end; + + for X := 253 to 255 do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryAtMinus4WithElse.DoTestIteration(Iteration: Integer); + var + Index: ShortInt; + begin + Index := ShortInt(Iteration and $FF); + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Byte(Index)] := $FF; + case Index of + -4: FResultStorage[Byte(Index)] := 1; + else FResultStorage[Byte(Index)] := 0; + end; + end; + +{ TSingleEntryWith0To5RangeWithElse } + +function TSingleEntryWith0To5RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "0..5" and else block'; + end; + +function TSingleEntryWith0To5RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to 5 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 6 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWith0To5RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 0..5: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryWith0To50RangeWithElse } + +function TSingleEntryWith0To50RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "0..50" and else block'; + end; + +function TSingleEntryWith0To50RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to 50 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 51 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWith0To50RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 0..50: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryWith1To5RangeWithElse } + +function TSingleEntryWith1To5RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "1..5" and else block'; + end; + +function TSingleEntryWith1To5RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + if FResultStorage[0] <> 0 then + begin + WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to 5 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 6 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWith1To5RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 1..5: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + +{ TSingleEntryWith1To50RangeWithElse } + +function TSingleEntryWith1To50RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "1..50" and else block'; + end; + +function TSingleEntryWith1To50RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + if FResultStorage[0] <> 0 then + begin + WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to 50 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 51 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWith1To50RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 1..50: FResultStorage[Index] := 1; + else FResultStorage[Index] := 0; + end; + end; + + +{ TSingleEntryWithMinus1To5RangeWithElse } + +function TSingleEntryWithMinus1To5RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "-1..5" and else block'; + end; + +function TSingleEntryWithMinus1To5RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + for X := 0 to 5 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 6 to $FE do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[$FF] <> 1 then + begin + WriteLn('FAIL - Index 255; expected $00 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWithMinus1To5RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: ShortInt; + begin + Index := ShortInt(Iteration and $FF); + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Byte(Index)] := $FF; + case Index of + -1..5: FResultStorage[Byte(Index)] := 1; + else FResultStorage[Byte(Index)] := 0; + end; + end; + +{ TSingleEntryWithMinus1To50RangeWithElse } + +function TSingleEntryWithMinus1To50RangeWithElse.TestTitle: shortstring; + begin + Result := 'Single entry of "-1..50" and else block'; + end; + +function TSingleEntryWithMinus1To50RangeWithElse.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + for X := 0 to 50 do + if FResultStorage[X] <> 1 then + begin + WriteLn('FAIL - Index ', X, '; expected $01 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 51 to $FE do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[$FF] <> 1 then + begin + WriteLn('FAIL - Index 255; expected $00 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + end; + +procedure TSingleEntryWithMinus1To50RangeWithElse.DoTestIteration(Iteration: Integer); + var + Index: ShortInt; + begin + Index := ShortInt(Iteration and $FF); + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Byte(Index)] := $FF; + case Index of + -1..50: FResultStorage[Byte(Index)] := 1; + else FResultStorage[Byte(Index)] := 0; + end; + end; + +{ TExtremeRange1 } + +function TExtremeRange1.TestTitle: shortstring; + begin + Result := 'Two labels, one with extreme spread, equal polling'; + end; + +function TExtremeRange1.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + if FResultStorage[0] <> 1 then + begin + WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to $FFFE do + if FResultStorage[X] <> 2 then + begin + WriteLn('FAIL - Index ', X, '; expected $02 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[65535] <> 0 then + begin + WriteLn('FAIL - Index 65535; expected $02 got $', hexstr(FResultStorage[65535], 2)); + Result := False; + Exit; + end; + end; + +procedure TExtremeRange1.DoTestIteration(Iteration: Integer); + var + Index: Word; + begin + Index := Iteration and $FFFF; + FResultStorage[Index] := 0; { Covers $FFFF } + case Index of + 0: + FResultStorage[Index] := 1; + 1..$FFFE: + FResultStorage[Index] := 2; + end; + end; + +{ TExtremeRange2 } + +function TExtremeRange2.TestTitle: shortstring; + begin + Result := 'Two labels, one with extreme spread, 50% else chance'; + end; + +function TExtremeRange2.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to $FFFF do + if FResultStorage[X] <> (X and $1) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $1, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TExtremeRange2.DoTestIteration(Iteration: Integer); + var + Index, Input: Word; + begin +{$push} +{$r-} + Index := (Iteration and $FFFF); + Input := (Iteration and $1) - 1; +{$pop} + FResultStorage[Index] := 0; { Covers $FFFF } + case Input of + 0..$FFFD: + FResultStorage[Index] := 1; + $FFFE: + FResultStorage[Index] := 2; + end; + end; + +{ TExtremeRange3 } + +function TExtremeRange3.TestTitle: shortstring; + begin + Result := 'Two labels, sparse values, equal polling across range'; + end; + +function TExtremeRange3.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + if FResultStorage[0] <> 1 then + begin + WriteLn('FAIL - Index 0; expected $01 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to $FFFE do + if FResultStorage[X] <> 2 then + begin + WriteLn('FAIL - Index ', X, '; expected $02 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[65535] <> 0 then + begin + WriteLn('FAIL - Index 65535; expected $02 got $', hexstr(FResultStorage[65535], 2)); + Result := False; + Exit; + end; + end; + +procedure TExtremeRange3.DoTestIteration(Iteration: Integer); + var + Index: Word; + begin + Index := Iteration and $FFFF; + FResultStorage[Index] := 2; { Covers 1..$FFFE } + case Index of + 0: + FResultStorage[Index] := 1; + $FFFF: + FResultStorage[Index] := 0; + end; + end; + +{ TExtremeRange4 } + +function TExtremeRange4.TestTitle: shortstring; + begin + Result := 'Two labels, sparse values, always triggered'; + end; + +function TExtremeRange4.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to $FFFF do + if FResultStorage[X] <> (X and $1) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $1, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TExtremeRange4.DoTestIteration(Iteration: Integer); + var + Index, Input: Word; + begin +{$push} +{$r-} + Index := (Iteration and $FFFF); + Input := (Iteration and $1) - 1; +{$pop} + FResultStorage[Index] := 2; { Covers 1..$FFFE } + case Input of + 0: + FResultStorage[Index] := 1; + $FFFF: + FResultStorage[Index] := 0; + end; + end; + +{ TSparseDataTest1 } + +procedure TSparseDataTest1.DoCaseBlock(Index: Integer; Input: TInstructionSet); + begin + case Input of + A_AND: + FResultStorage[Index] := 1; + A_MOV: + FResultStorage[Index] := 2; + A_MOVSX, + A_MOVZX: + FResultStorage[Index] := 3; + A_VMOVAPS, + A_VMOVAPD, + A_VMOVUPS, + A_VMOVUPD: + FResultStorage[Index] := 4; + A_MOVAPD, + A_MOVAPS, + A_MOVUPD, + A_MOVUPS: + FResultStorage[Index] := 5; + A_VDIVSD, + A_VDIVSS, + A_VSUBSD, + A_VSUBSS, + A_VMULSD, + A_VMULSS, + A_VADDSD, + A_VADDSS, + A_VANDPD, + A_VANDPS, + A_VORPD, + A_VORPS, + A_VXORPD, + A_VXORPS: + FResultStorage[Index] := 6; + A_MULSD, + A_MULSS, + A_ADDSD, + A_ADDSS: + FResultStorage[Index] := 7; + A_VMOVSD, + A_VMOVSS, + A_MOVSD, + A_MOVSS: + FResultStorage[Index] := 8; + A_LEA: + FResultStorage[Index] := 9; + A_SUB: + FResultStorage[Index] := 10; + A_SHL,A_SAL: + FResultStorage[Index] := 11; + A_SETcc: + FResultStorage[Index] := 12; + else + FResultStorage[Index] := 0; + end; + end; + +{ TSparseDataEqual1 } + +function TSparseDataEqual1.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 12 sparse labels, equal polling'; + end; + +function TSparseDataEqual1.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to 1023 do + if FResultStorage[X] <> ExtremeRange1Expected[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange1Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSparseDataEqual1.DoTestIteration(Iteration: Integer); + var + X: SmallInt; + begin + X := Iteration and 1023; + DoCaseBlock(X, TInstructionSet(X - 512)) + end; + +{ TSparseDataMOVWeightedl } + +function TSparseDataMOVWeighted1.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 12 sparse labels, 75% particular match'; + end; + +function TSparseDataMOVWeighted1.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange1Expected[X], 2); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMOVWeighted1.DoTestIteration(Iteration: Integer); + var + X: SmallInt; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); + DoCaseBlock(X, P); + end; + +{ TSparseDataMidpointWeighted1 } + +function TSparseDataMidpointWeighted1.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 12 sparse labels, 75% midpoint match'; + end; + +function TSparseDataMidpointWeighted1.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange1Expected[X], 6); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMidpointWeighted1.DoTestIteration(Iteration: Integer); + var + X: Word; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); + DoCaseBlock(X, P); + end; + +{ TSparseDataTest2 } + +procedure TSparseDataTest2.DoCaseBlock(Index: Integer; Input: TInstructionSet); + begin + case Input of + A_AND: + FResultStorage[Index] := 1; + A_MOV: + FResultStorage[Index] := 2; + A_MOVSX: + FResultStorage[Index] := 13; + A_MOVZX: + FResultStorage[Index] := 3; + A_VMOVAPS: + FResultStorage[Index] := 14; + A_VMOVAPD: + FResultStorage[Index] := 15; + A_VMOVUPS: + FResultStorage[Index] := 16; + A_VMOVUPD: + FResultStorage[Index] := 4; + A_MOVAPD: + FResultStorage[Index] := 17; + A_MOVAPS: + FResultStorage[Index] := 18; + A_MOVUPD: + FResultStorage[Index] := 19; + A_MOVUPS: + FResultStorage[Index] := 5; + A_VDIVSD: + FResultStorage[Index] := 20; + A_VDIVSS: + FResultStorage[Index] := 21; + A_VSUBSD: + FResultStorage[Index] := 22; + A_VSUBSS: + FResultStorage[Index] := 23; + A_VMULSD: + FResultStorage[Index] := 24; + A_VMULSS: + FResultStorage[Index] := 25; + A_VADDSD: + FResultStorage[Index] := 26; + A_VADDSS: + FResultStorage[Index] := 27; + A_VANDPD: + FResultStorage[Index] := 28; + A_VANDPS: + FResultStorage[Index] := 29; + A_VORPD: + FResultStorage[Index] := 30; + A_VORPS: + FResultStorage[Index] := 31; + A_VXORPD: + FResultStorage[Index] := 32; + A_VXORPS: + FResultStorage[Index] := 6; + A_MULSD: + FResultStorage[Index] := 33; + A_MULSS: + FResultStorage[Index] := 34; + A_ADDSD: + FResultStorage[Index] := 35; + A_ADDSS: + FResultStorage[Index] := 7; + A_VMOVSD: + FResultStorage[Index] := 36; + A_VMOVSS: + FResultStorage[Index] := 37; + A_MOVSD: + FResultStorage[Index] := 38; + A_MOVSS: + FResultStorage[Index] := 8; + A_LEA: + FResultStorage[Index] := 9; + A_SUB: + FResultStorage[Index] := 10; + A_SHL: + FResultStorage[Index] := 39; + A_SAL: + FResultStorage[Index] := 11; + A_SETcc: + FResultStorage[Index] := 12; + else + FResultStorage[Index] := 0; + end; + end; + +{ TSparseDataEqual2 } + +function TSparseDataEqual2.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 39 sparse labels, equal polling'; + end; + +function TSparseDataEqual2.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to 1023 do + if FResultStorage[X] <> ExtremeRange2Expected[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange2Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSparseDataEqual2.DoTestIteration(Iteration: Integer); + var + X: SmallInt; + begin + X := Iteration and 1023; + DoCaseBlock(X, TInstructionSet(X - 512)) + end; + +{ TSparseDataMOVWeighted2 } + +function TSparseDataMOVWeighted2.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 39 sparse labels, 75% particular match'; + end; + +function TSparseDataMOVWeighted2.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange2Expected[X], 2); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMOVWeighted2.DoTestIteration(Iteration: Integer); + var + X: SmallInt; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); + DoCaseBlock(X, P); + end; + +{ TSparseDataMidpointWeighted2 } + +function TSparseDataMidpointWeighted2.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 39 sparse labels, 75% midpoint match'; + end; + +function TSparseDataMidpointWeighted2.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange2Expected[X], 26); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMidpointWeighted2.DoTestIteration(Iteration: Integer); + var + X: SmallInt; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); + DoCaseBlock(X, P); + end; + +{ TSparseDataTest3 } + +procedure TSparseDataTest3.DoCaseBlock(Index: Integer; Input: TInstructionSet); + begin + case Input of + A_AND: + FResultStorage[Index] := 1; + A_MOV: + FResultStorage[Index] := 2; + A_MOVSX: + FResultStorage[Index] := 13; + A_MOVZX: + FResultStorage[Index] := 3; + A_VMOVAPS: + FResultStorage[Index] := 14; + A_VMOVAPD: + FResultStorage[Index] := 15; + A_VMOVUPS: + FResultStorage[Index] := 16; + A_VMOVUPD: + FResultStorage[Index] := 4; + A_MOVAPD: + FResultStorage[Index] := 17; + A_MOVAPS: + FResultStorage[Index] := 18; + A_MOVUPD: + FResultStorage[Index] := 19; + A_MOVUPS: + FResultStorage[Index] := 5; + A_VDIVSD: + FResultStorage[Index] := 20; + A_VDIVSS: + FResultStorage[Index] := 21; + A_VSUBSD: + FResultStorage[Index] := 22; + A_VSUBSS: + FResultStorage[Index] := 23; + A_VMULSD: + FResultStorage[Index] := 24; + A_VMULSS: + FResultStorage[Index] := 25; + A_VADDSD: + FResultStorage[Index] := 26; + A_VADDSS: + FResultStorage[Index] := 27; + A_VANDPD: + FResultStorage[Index] := 28; + A_VANDPS: + FResultStorage[Index] := 29; + A_VORPD: + FResultStorage[Index] := 30; + A_VORPS: + FResultStorage[Index] := 31; + A_VXORPD: + FResultStorage[Index] := 32; + A_VXORPS: + FResultStorage[Index] := 6; + A_MULSD: + FResultStorage[Index] := 33; + A_MULSS: + FResultStorage[Index] := 34; + A_ADDSD: + FResultStorage[Index] := 35; + A_ADDSS: + FResultStorage[Index] := 7; + A_VMOVSD: + FResultStorage[Index] := 36; + A_VMOVSS: + FResultStorage[Index] := 37; + A_MOVSD: + FResultStorage[Index] := 38; + A_MOVSS: + FResultStorage[Index] := 8; + A_LEA: + FResultStorage[Index] := 9; + A_SUB: + FResultStorage[Index] := 10; + A_SHL: + FResultStorage[Index] := 39; + A_SAL: + FResultStorage[Index] := 11; + A_SETcc: + FResultStorage[Index] := 12; + A_MULX: + FResultStorage[Index] := 40; + A_VBROADCASTF128: + FResultStorage[Index] := 41; + A_VBROADCASTI128: + FResultStorage[Index] := 42; + A_VPERMD: + FResultStorage[Index] := 43; + A_VADDPD: + FResultStorage[Index] := 44; + A_VADDPS: + FResultStorage[Index] := 45; + A_ROUNDPS: + FResultStorage[Index] := 46; + A_ROUNDPD: + FResultStorage[Index] := 47; + A_ROUNDSS: + FResultStorage[Index] := 48; + A_ROUNDSD: + FResultStorage[Index] := 49; + A_CRC32: + FResultStorage[Index] := 50; + A_DPPS: + FResultStorage[Index] := 51; + A_DPPD: + FResultStorage[Index] := 52; + A_VAESDEC: + FResultStorage[Index] := 53; + A_VAESDECLAST: + FResultStorage[Index] := 54; + A_VAESENC: + FResultStorage[Index] := 55; + A_VAESENCLAST: + FResultStorage[Index] := 56; + A_VAESIMC: + FResultStorage[Index] := 57; + A_VAESKEYGENASSIST: + FResultStorage[Index] := 58; + A_VPSHUFB: + FResultStorage[Index] := 59; + A_VPSHUFD: + FResultStorage[Index] := 60; + A_VPSHUFHW: + FResultStorage[Index] := 61; + A_VPSHUFLW: + FResultStorage[Index] := 62; + A_BSF: + FResultStorage[Index] := 63; + A_BSR: + FResultStorage[Index] := 64; + A_BTR: + FResultStorage[Index] := 65; + A_BTS: + FResultStorage[Index] := 66; + A_XOR: + FResultStorage[Index] := 67; + A_ADD: + FResultStorage[Index] := 68; + A_CMP: + FResultStorage[Index] := 69; + A_SHLX: + FResultStorage[Index] := 70; + A_SHRX: + FResultStorage[Index] := 71; + else + FResultStorage[Index] := 0; + end; + end; + +{ TSparseDataEqual3 } + +function TSparseDataEqual3.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 71 sparse labels, equal polling'; + end; + +function TSparseDataEqual3.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + + for X := 0 to 1023 do + if FResultStorage[X] <> ExtremeRange3Expected[X] then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(ExtremeRange3Expected[X], 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TSparseDataEqual3.DoTestIteration(Iteration: Integer); + var + X: SmallInt; + begin + X := Iteration and 1023; + DoCaseBlock(X, TInstructionSet(X - 512)) + end; + +{ TSparseDataMOVWeightedl } + +function TSparseDataMOVWeighted3.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 71 sparse labels, 75% particular match'; + end; + +function TSparseDataMOVWeighted3.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange3Expected[X], 2); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMOVWeighted3.DoTestIteration(Iteration: Integer); + var + X: SmallInt; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_MOV))); + DoCaseBlock(X, P); + end; + +{ TSparseDataMidpointWeighted3 } + +function TSparseDataMidpointWeighted3.TestTitle: shortstring; + begin + Result := 'Domain of 1024, 71 sparse labels, 75% midpoint match'; + end; + +function TSparseDataMidpointWeighted3.WriteResults: Boolean; + var + X, Expected: Word; + begin + Result := True; + + for X := 0 to 1023 do + begin + Expected := IIf((X and $3) = 0, ExtremeRange3Expected[X], 26); + if FResultStorage[X] <> Expected then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(Expected, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + end; + +procedure TSparseDataMidpointWeighted3.DoTestIteration(Iteration: Integer); + var + X: SmallInt; P: TInstructionSet; + begin + X := Iteration and 1023; + P := TInstructionSet(IIf((X and $3) = 0, X - 512, Ord(A_VADDSD))); + DoCaseBlock(X, P); + end; + + +{ TLinearListDependsOnInput } + +function TLinearListDependsOnInput.TestTitle: shortstring; + begin + Result := 'Linear list depends on input'; + end; + +function TLinearListDependsOnInput.WriteResults: Boolean; + var + X: Word; + begin + Result := True; + if FResultStorage[0] <> 0 then + begin + WriteLn('FAIL - Index 0; expected $00 got $', hexstr(FResultStorage[0], 2)); + Result := False; + Exit; + end; + + for X := 1 to 7 do + if FResultStorage[X] <> (X and $3) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr(X and $3, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 8 to 11 do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + if FResultStorage[12] <> $10 then + begin + WriteLn('FAIL - Index 12; expected $10 got $', hexstr(FResultStorage[12], 2)); + Result := False; + Exit; + end; + + for X := 13 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TLinearListDependsOnInput.DoTestIteration(Iteration: Integer); + var + Index: Byte; + begin + Index := Iteration and $FF; + { This helps catch errors where all branches, including else, are skipped } + FResultStorage[Index] := $FF; + case Index of + 1..3: FResultStorage[Index] := Index; + 4..7: FResultStorage[Index] := Index - 4; + 12: FResultStorage[Index] := $10; + else FResultStorage[Index] := 0; + end; + end; + + +{ TCStyleCascade } + +function TCStyleCascade.TestTitle: shortstring; + begin + Result := 'C-style cascade using ''goto'''; + end; + +function TCStyleCascade.WriteResults: Boolean; + var + X: Byte; + begin + Result := True; + for X := 0 to 5 do + if FResultStorage[X] <> ((1 shl X) - 1) then + begin + WriteLn('FAIL - Index ', X, '; expected $', hexstr((1 shl X) - 1, 2), ' got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + + for X := 6 to $FF do + if FResultStorage[X] <> 0 then + begin + WriteLn('FAIL - Index ', X, '; expected $00 got $', hexstr(FResultStorage[X], 2)); + Result := False; + Exit; + end; + end; + +procedure TCStyleCascade.DoTestIteration(Iteration: Integer); + var + X, Tmp: Byte; + label + Set1, Set2, Set3, Set4, Default; + begin + X := Iteration and $FF; + Tmp := 0; + case X of + $1: goto Set1; + $2: goto Set2; + $3: goto Set3; + $4: goto Set4; + $5: Tmp := 16; + else + goto Default; + end; + Set4: + Tmp := Tmp or $8; + Set3: + Tmp := Tmp or $4; + Set2: + Tmp := Tmp or $2; + Set1: + Tmp := Tmp or $1; + Default: + FResultStorage[X] := Tmp; + end; + + +{ Main function } +const + { TCompleteByteRange and descendants + - Entirely-covered jump tree + - 33 labels, no else block; full coverage (all 256 byte values covered) + - Root: values are polled with equal probability + - FirstWeighted: first branch is polled 3 times as often + - LastWeighted: last branch is polled 3 times as often + TAlmostFullByteRange + - Almost full jump tree - 18 labels, else block covers 32 values; 224 byte values covered + - Root: values are polled with equal probability + - FirstWeighted: first branch is polled 3 times as often + - LastWeighted: last branch is polled 3 times as often + } + + TestClasses: array[0..35] of TTestClass = ( + TCompleteByteRange, + TCompleteByteRangeFirstWeighted, + TCompleteByteRangeLastWeighted, + TAlmostFullByteRange, + TAlmostFullByteRangeFirstWeighted, + TAlmostFullByteRangeLastWeighted, + TSingleEntryWithDefault, + TSingleEntryWithDefaultUnlikely, + TSingleEntryWithDefaultWeighted, + TSingleEntryWithElse, + TSingleEntryWithElseUnlikely, + TSingleEntryWithElseWeighted, + TSingleEntryAtZeroWithElse, + TSingleEntryAtMinus1WithDefault, + TSingleEntryAtMinus4WithElse, + TSingleEntryWith0To5RangeWithElse, + TSingleEntryWith0To50RangeWithElse, + TSingleEntryWith1To5RangeWithElse, + TSingleEntryWith1To50RangeWithElse, + TSingleEntryWithMinus1To5RangeWithElse, + TSingleEntryWithMinus1To50RangeWithElse, + TExtremeRange1, + TExtremeRange2, + TExtremeRange3, + TExtremeRange4, + TSparseDataEqual1, + TSparseDataMOVWeighted1, + TSparseDataMidpointWeighted1, + TSparseDataEqual2, + TSparseDataMOVWeighted2, + TSparseDataMidpointWeighted2, + TSparseDataEqual3, + TSparseDataMOVWeighted3, + TSparseDataMidpointWeighted3, + TLinearListDependsOnInput, + TCStyleCascade + ); + +var + CurrentObject: TTestAncestor; + Failed: Boolean; + X: Integer; + SummedUpAverageDuration, AverageDuration : Double; +begin + SummedUpAverageDuration := 0.0; + Failed := False; + WriteLn('Case node compilation and timing test'); + WriteLn('-------------------------------------'); + for X := low(TestClasses) to High(TestClasses) do + begin + try + CurrentObject := TestClasses[X].Create; + try + Write(CurrentObject.TestTitle:56, ' - '); + CurrentObject.Run; + + if CurrentObject.WriteResults then + begin + AverageDuration := ((CurrentObject.RunTime * 1000000000.0) / ITERATIONS); + WriteLn('Pass - average iteration duration: ', AverageDuration:1:3, ' ns'); + SummedUpAverageDuration := SummedUpAverageDuration + AverageDuration; + end + else + { Final average isn't processed if a test failed, so there's no need + to calculate and add the average duration to it } + Failed := True; + + finally + CurrentObject.Free; + end; + except on E: Exception do + begin + WriteLn('Exception "', E.ClassName, '" raised while running test object of class "', TestClasses[X].ClassName, '"'); + Failed := True; + end; + end; + end; + + if Failed then + Halt(1); + + WriteLn(#10'ok'); + WriteLn('- Sum of average durations: ', SummedUpAverageDuration:1:3, ' ns'); + WriteLn('- Overall average duration: ', (SummedUpAverageDuration / Length(TestClasses)):1:3, ' ns'); +end. From 8fbd6dedbba2c559931e84e422d8cfc6ed3e2eae Mon Sep 17 00:00:00 2001 From: Pierre Muller Date: Mon, 23 Aug 2021 13:46:52 +0200 Subject: [PATCH 092/116] Add some more patterns to .gitignore --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 673a3ec326..863abd9ebd 100644 --- a/.gitignore +++ b/.gitignore @@ -32,6 +32,7 @@ fpcmade.* build-stamp.* log.* faillist.* +link*.res longlog.* bin backup @@ -57,6 +58,8 @@ a.out /compiler/utils/mkx86inl /packages/fpmake /packages/fpmkunit/units_bs +/rtl/Package.fpc +/rtl/units-* /utils/fpmake units /tests/createlst From 69883e04f151909c3469671a4ae21f1dfb0d31df Mon Sep 17 00:00:00 2001 From: Bernd Kreuss Date: Mon, 23 Aug 2021 15:25:12 +0200 Subject: [PATCH 093/116] gdeque: remove unused variable --- packages/fcl-stl/src/gdeque.pp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/packages/fcl-stl/src/gdeque.pp b/packages/fcl-stl/src/gdeque.pp index 9a91f3f483..54f90667e3 100644 --- a/packages/fcl-stl/src/gdeque.pp +++ b/packages/fcl-stl/src/gdeque.pp @@ -236,7 +236,7 @@ const cSizeSmall = 1*1024*1024; cSizeBig = 256*1024*1024; var - i,OldEnd, + OldEnd, DataSize,CurLast,EmptyElems,Elems:SizeUInt; begin OldEnd:=FCapacity; From 26f4d957a0e50653dfac5a7e594d30154146fe89 Mon Sep 17 00:00:00 2001 From: florian Date: Mon, 23 Aug 2021 23:46:45 +0200 Subject: [PATCH 094/116] * moved fwait --- rtl/x86_64/math.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/x86_64/math.inc b/rtl/x86_64/math.inc index fe8b8c975f..0e721206fc 100644 --- a/rtl/x86_64/math.inc +++ b/rtl/x86_64/math.inc @@ -301,8 +301,8 @@ const fld %st frndint fsubrp %st,%st(1) - fldcw oldcw fwait + fldcw oldcw end; {$endif FPC_SYSTEM_HAS_FRAC} From 0bc827e9e26e8dcd65d0adaa23ccf0ffe6bbe2a6 Mon Sep 17 00:00:00 2001 From: Pierre Muller Date: Tue, 24 Aug 2021 13:04:50 +0000 Subject: [PATCH 095/116] Add test for bug report 38973 (already fixed in trunk/main) --- tests/webtbs/tw38973.pp | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/webtbs/tw38973.pp diff --git a/tests/webtbs/tw38973.pp b/tests/webtbs/tw38973.pp new file mode 100644 index 0000000000..7ccd9e1c08 --- /dev/null +++ b/tests/webtbs/tw38973.pp @@ -0,0 +1,12 @@ +{%OPT=-O2} +{$mode objfpc} +var + b : LongBOOL; + pb : ^LongBOOL; +begin + b:=true; + pb:=nil; + if Assigned(pb) and pb^ then + Exit; + b:=false; +end. From 968d00fedf64ee56f23796069752cac3207d48e5 Mon Sep 17 00:00:00 2001 From: ccrause Date: Tue, 24 Aug 2021 17:01:50 +0000 Subject: [PATCH 096/116] + Add support for -Adefault. * Move help message for option -sT to the correct group of messages. * Use shorter message to indicate switch to external asm. * Adapted -sX messages because -sT doesn't force external assembler writer. --- compiler/msg/errore.msg | 10 +- compiler/msgidx.inc | 2 +- compiler/msgtxt.inc | 389 ++++++++++++++++++++-------------------- compiler/options.pas | 9 +- compiler/systems.inc | 1 + compiler/systems.pas | 2 +- 6 files changed, 213 insertions(+), 200 deletions(-) diff --git a/compiler/msg/errore.msg b/compiler/msg/errore.msg index c2c015a1b6..5ac021ba1f 100644 --- a/compiler/msg/errore.msg +++ b/compiler/msg/errore.msg @@ -3863,7 +3863,7 @@ F*0*_Only options valid for the default or selected platform are listed. **0*_Put + after a boolean switch option to enable it, - to disable it. **1@_Read compiler options from in addition to the default fpc.cfg # Assembler related options -**1a_The compiler does not delete the generated assembler file +**1a_The compiler does not delete the generated assembler file, automatically switches to external assembler writer **2a5_Don't generate Big Obj COFF files for GNU Binutils older than 2.25 (Windows, NativeNT) **2al_List sourcecode lines in assembler file **2an_List node info in assembler file (-dEXTDEBUG compiler) @@ -4118,7 +4118,6 @@ F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipsel,powerpc, **2SI_Set interface style to **3SIcom_COM compatible interface (default) **3SIcorba_CORBA compatible interface -**2sT_Generate script only to link on target **2Sm_Support macros like C (global) **2So_Same as -Mtp **2Sr_Transparent file names in ISO mode @@ -4127,9 +4126,10 @@ F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipsel,powerpc, **2Sx_Enable exception keywords (default in Delphi/ObjFPC modes) **2Sy_@ returns a typed pointer, same as $T+ **1s_Do not call assembler and linker -**2sh_Generate script to link on host -**2st_Generate script to assemble and link on target -**2sr_Skip register allocation phase (use with -alr) +**2sh_Generate script to link on host, automatically switches to external assembler writer +**2sT_Generate script only to link on target +**2st_Generate script to assemble and link on target, automatically switches to external assembler writer +**2sr_Skip register allocation phase (use with -alr), automatically switches to external assembler writer **1T_Target operating system: # i386 targets 3*2Tandroid_Android diff --git a/compiler/msgidx.inc b/compiler/msgidx.inc index 6d93a673e6..655f194e0f 100644 --- a/compiler/msgidx.inc +++ b/compiler/msgidx.inc @@ -1141,7 +1141,7 @@ const option_info=11024; option_help_pages=11025; - MsgTxtSize = 87955; + MsgTxtSize = 88167; MsgIdxMax : array[1..20] of longint=( 28,107,361,131,99,63,147,37,223,68, diff --git a/compiler/msgtxt.inc b/compiler/msgtxt.inc index b109b953bf..e4446c9432 100644 --- a/compiler/msgtxt.inc +++ b/compiler/msgtxt.inc @@ -1,8 +1,8 @@ const msgtxt_codepage=20127; {$ifdef Delphi} -const msgtxt : array[0..000366] of string[240]=( +const msgtxt : array[0..000367] of string[240]=( {$else Delphi} -const msgtxt : array[0..000366,1..240] of char=( +const msgtxt : array[0..000367,1..240] of char=( {$endif Delphi} '01000_T_Compiler: $1'#000+ '01001_D_Compiler OS: $1'#000+ @@ -1460,346 +1460,350 @@ const msgtxt : array[0..000366,1..240] of char=( 'it.'#010+ '**1@_Read compiler options from in addition to the default fpc.'+ 'cfg'#010+ - '**1a_The compiler does not delete the generated assembler file'#010+ - '**2a5_Don'#039't generate Big Obj COFF files for GNU Binutils older ','t'+ - 'han 2.25 (Windows, NativeNT)'#010+ + '**1a_The compiler does not delete the generated assembler file, automa'+ + 'tically switches to external assembler writer'#010+ + '**2a5_Don'#039,'t generate Big Obj COFF files for GNU Binutils older th'+ + 'an 2.25 (Windows, NativeNT)'#010+ '**2al_List sourcecode lines in assembler file'#010+ '**2an_List node info in assembler file (-dEXTDEBUG compiler)'#010+ - '**2ao_Add an extra option to external assembler call (ignored for inte'+ - 'rnal)'#010+ - '*L2ap_Use pipes instead of ','creating temporary assembler files'#010+ + '**2ao_Add an extra option to external assembler ca','ll (ignored for in'+ + 'ternal)'#010+ + '*L2ap_Use pipes instead of creating temporary assembler files'#010+ '**2ar_List register allocation/release info in assembler file'#010+ '**2at_List temp allocation/release info in assembler file'#010+ '**1A_Output format:'#010+ - '**2Adefault_Use default assembler'#010+ - '3*2Aas_Assemble using GNU AS',#010+ + '**2Adefau','lt_Use default assembler'#010+ + '3*2Aas_Assemble using GNU AS'#010+ '3*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ '3*2Amacho_Mach-O (Darwin, Intel 32 bit) using internal writer'#010+ '8*2Anasm_Assemble using Nasm'#010+ '8*2Anasmobj_Assemble using Nasm'#010+ - '3*2Anasm_Assemble using Nasm'#010+ - '3*2Anasmcoff_COFF (Go32v2) file usin','g Nasm'#010+ + '3*2Anasm_Ass','emble using Nasm'#010+ + '3*2Anasmcoff_COFF (Go32v2) file using Nasm'#010+ '3*2Anasmelf_ELF32 (Linux) file using Nasm'#010+ '3*2Anasmwin32_Win32 object file using Nasm'#010+ '3*2Anasmwdosx_Win32/WDOSX object file using Nasm'#010+ - '3*2Anasmdarwin_macho32 object file using Nasm (experimental)'#010+ - '3*2Awasm_Obj file using Wasm (Watcom)'#010, + '3*2Anasmdarwin_macho32 object file using Nasm ','(experimental)'#010+ + '3*2Awasm_Obj file using Wasm (Watcom)'#010+ '3*2Anasmobj_Obj file using Nasm'#010+ '3*2Amasm_Obj file using Masm (Microsoft)'#010+ '3*2Atasm_Obj file using Tasm (Borland)'#010+ '3*2Aelf_ELF (Linux) using internal writer'#010+ - '3*2Acoff_COFF (Go32v2) using internal writer'#010+ - '3*2Apecoff_PE-COFF (Win32) using internal',' writer'#010+ + '3*2Acoff_COFF (Go32v2) using inte','rnal writer'#010+ + '3*2Apecoff_PE-COFF (Win32) using internal writer'#010+ '3*2Ayasm_Assemble using Yasm (experimental)'#010+ '4*2Aas_Assemble using GNU AS'#010+ '4*2Agas_Assemble using GNU GAS'#010+ '4*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ - '4*2Amasm_Win64 object file using ml64 (Microsoft)'#010+ - '4*2Apecoff_PE-COFF (Win64) ','using internal writer'#010+ + '4*2Amasm_Win64 object fi','le using ml64 (Microsoft)'#010+ + '4*2Apecoff_PE-COFF (Win64) using internal writer'#010+ '4*2Aelf_ELF (Linux-64bit) using internal writer'#010+ '4*2Ayasm_Assemble using Yasm (experimental)'#010+ '4*2Anasm_Assemble using Nasm (experimental)'#010+ - '4*2Anasmwin64_Assemble Win64 object file using Nasm (experimental)'#010+ - '4*2Anasmelf_Ass','emble Linux-64bit object file using Nasm (experimenta'+ - 'l)'#010+ + '4*2Anasmwin64_Assemble Win64 ','object file using Nasm (experimental)'#010+ + '4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental)'+ + #010+ '4*2Anasmdarwin_Assemble darwin macho64 object file using Nasm (experim'+ 'ental)'#010+ '6*2Aas_Unix o-file using GNU AS'#010+ - '6*2Agas_GNU Motorola assembler'#010+ + '6*2Agas_GNU Motorola a','ssembler'#010+ '6*2Amit_MIT Syntax (old GAS)'#010+ - '6*2Amot_Standar','d Motorola assembler'#010+ + '6*2Amot_Standard Motorola assembler'#010+ '6*2Avasm_Use vasm to assemble'#010+ 'A*2Aas_Assemble using GNU AS'#010+ 'A*2Aas-darwin_Assemble using GNU AS for Darwin targets'#010+ 'A*2Aclang_Assemble using clang'#010+ - 'A*2Aelf_Assemble using internal ELF writer'#010+ + 'A*2Aelf_Assemble usin','g internal ELF writer'#010+ 'a*2Aas_Assemble using GNU AS'#010+ - 'a*','2Aclang_Assemble using clang for darwin/ios targets'#010+ + 'a*2Aclang_Assemble using clang for darwin/ios targets'#010+ 'a*2Aas-clang_Assemble using clang for other targets '#010+ 'P*2Aas_Assemble using GNU AS'#010+ 'S*2Aas_Assemble using GNU AS'#010+ - 's*2Aas_Assemble using GNU AS'#010+ + 's*2Aas_Assemble using GN','U AS'#010+ 'v*2Aas_Assemble using GNU AS'#010+ - 'W*2Abinaryen_Assemb','le using GNU AS for wasm32 (wasm-as)'#010+ + 'W*2Abinaryen_Assemble using GNU AS for wasm32 (wasm-as)'#010+ 'W*2Allvm-mc_Assemble using llvm-mc'#010+ 'W*2Awabt_Assemble using wasa'#010+ 'x*2Aas_Assemble using GNU AS'#010+ 'Z*2Asdcc-sdasz80_Assemble using SDCC-SDASZ80'#010+ - 'Z*2Az80asm_Assemble using z80asm'#010+ + 'Z*2Az80asm_A','ssemble using z80asm'#010+ 'Z*2Avasm_Assemble using Vasm'#010+ - '**1','b_Generate browser info'#010+ + '**1b_Generate browser info'#010+ '**2bl_Generate local symbol info'#010+ '**1B_Build all modules'#010+ '**1C_Code generation options:'#010+ '**2C3_Turn on ieee error checking for constants'#010+ - '**2Ca_Select ABI; see fpc -i or fpc -ia for possible values'#010+ - '**2Cb_Generate c','ode for a big-endian variant of the target architect'+ - 'ure'#010+ + '**2Ca_Select ABI; see f','pc -i or fpc -ia for possible values'#010+ + '**2Cb_Generate code for a big-endian variant of the target architectur'+ + 'e'#010+ '**2Cc_Set default calling convention to '#010+ '**2CD_Create also dynamic library (not supported)'#010+ - '**2Ce_Compilation with emulated floating point opcodes'#010+ - '**2CE_Generate FPU code which ca','n raise exceptions'#010+ + '**2Ce_Compilation with emulated fl','oating point opcodes'#010+ + '**2CE_Generate FPU code which can raise exceptions'#010+ '**2Cf_Select fpu instruction set to use; see fpc -i or fpc -if for '+ 'possible values'#010+ '**2CF_Minimal floating point constant precision (default, 32, 64)'#010+ - '**2Cg_Generate PIC code'#010+ - '**2Ch[,m]_ bytes min heap size (betw','een 1023 and 67107840) and'+ - ' optionally [m] max heap size'#010+ + '**2Cg_Generat','e PIC code'#010+ + '**2Ch[,m]_ bytes min heap size (between 1023 and 67107840) and o'+ + 'ptionally [m] max heap size'#010+ '**2Ci_IO-checking'#010+ 'A*2CI_Select instruction set on ARM: ARM or THUMB'#010+ 'L*2Cl_LLVM code generation options'#010+ - 'L*3Clflto_Enable Link-time optimisation (needed both when compiling un'+ - 'its a','nd programs/libraries)'#010+ + 'L*3Clflto_Enable Link-','time optimisation (needed both when compiling '+ + 'units and programs/libraries)'#010+ 'L*3Clfltonosystem_Disable LTO for the system unit (needed with at leas'+ 't Xcode 10.2 and earlier due to linker bugs)'#010+ - 'L*3Clv_LLVM target version: Xcode-10.1, 7.0, 8.0, .., 10.0'#010+ + 'L*3Clv_LLVM target version: Xcode-10.1, 7.0, 8','.0, .., 10.0'#010+ '**2Cn_Omit linking stage'#010+ - 'P*2CN_Generate ','nil-pointer checks (AIX-only)'#010+ + 'P*2CN_Generate nil-pointer checks (AIX-only)'#010+ '**2Co_Check overflow of integer operations'#010+ '**2CO_Check for possible overflow of integer operations'#010+ - '**2Cp_Select instruction set; see fpc -i or fpc -ic for possible va'+ - 'lues'#010+ + '**2Cp_Select instruction set; see fpc -i or fpc -ic for',' possible '+ + 'values'#010+ '**2CP=_ packing settings'#010+ - '**3CP','PACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, '+ - '4 and 8'#010+ + '**3CPPACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, 4 '+ + 'and 8'#010+ '**3CPPACKENUM=_ enum packing: 0, 1, 2 and 4 or DEFAULT or NORMA'+ 'L'#010+ - '**3CPPACKRECORD=_ record packing: 0 or DEFAULT or NORMAL, 1, 2,'+ - ' 4, 8, 16 and 32'#010+ - '**2Cr_Rang','e checking'#010+ + '**3CPPACKRECORD=_ record packing: 0 o','r DEFAULT or NORMAL, 1, '+ + '2, 4, 8, 16 and 32'#010+ + '**2Cr_Range checking'#010+ '**2CR_Verify object method call validity'#010+ '**2Cs_Set stack checking size to '#010+ '**2Ct_Stack checking (for testing only, see manual)'#010+ - '8*2CT_Target-specific code generation options'#010+ - '3*2CT_Target-specific code generation option','s'#010+ + '8*2CT_Target-specific code generation op','tions'#010+ + '3*2CT_Target-specific code generation options'#010+ '4*2CT_Target-specific code generation options'#010+ 'p*2CT_Target-specific code generation options'#010+ 'P*2CT_Target-specific code generation options'#010+ - 'J*2CT_Target-specific code generation options'#010+ - 'A*2CT_Target-specific code generation o','ptions'#010+ + 'J*2CT_Target-specific code generati','on options'#010+ + 'A*2CT_Target-specific code generation options'#010+ 'p*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ ' (AIX)'#010+ 'P*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ ' (AIX)'#010+ - 'J*3CTautogetterprefix=X_ Automatically create getters for properties '+ - 'with pref','ix X (empty string disables)'#010+ + 'J*3CTautogetterprefix=X_ ','Automatically create getters for propertie'+ + 's with prefix X (empty string disables)'#010+ 'J*3CTautosetterprefix=X_ Automatically create setters for properties '+ 'with prefix X (empty string disables)'#010+ - '8*3CTcld_ Emit a CLD instruction before using the x86 '+ - 'string instructions'#010+ - '3*3CTcld_ ',' Emit a CLD instruction before using the x8'+ + '8*3CTcld_ Emit a CLD instruction b','efore using the x8'+ '6 string instructions'#010+ + '3*3CTcld_ Emit a CLD instruction before using the x86 '+ + 'string instructions'#010+ '4*3CTcld_ Emit a CLD instruction before using the x86 '+ 'string instructions'#010+ - '8*3CTfarprocspushoddbp_ Increment BP before pushing it in the pr'+ - 'olo','gue of far functions'#010+ + '8*3CTfarprocspushodd','bp_ Increment BP before pushing it in the '+ + 'prologue of far functions'#010+ 'J*3CTcompactintarrayinit_ Generate smaller (but potentially slower) co'+ 'de for initializing integer array constants'#010+ - 'J*3CTenumfieldinit_ Initialize enumeration fields in constructor'+ - 's to enumtype(0), after calling inh','erited constructors'#010+ + 'J*3CTenumfieldinit_ Initialize enumeration fie','lds in construct'+ + 'ors to enumtype(0), after calling inherited constructors'#010+ 'J*3CTinitlocals_ Initialize local variables that trigger a JV'+ 'M bytecode verification error if used uninitialized (slows down code)'#010+ - 'J*3CTlowercaseprocstart_ Lowercase the first character of procedure/f'+ - 'unction/me','thod names'#010+ + 'J*3CTlowercaseprocstart_ L','owercase the first character of procedure'+ + '/function/method names'#010+ 'A*3CTthumbinterworking_ Generate Thumb interworking-safe code if possi'+ 'ble'#010+ 'J*2Cv_Var/out parameter copy-out checking'#010+ 'A*2CV_Set section threadvar model to '#010+ - '**2CX_Create also smartlinked library'#010+ - '**1d_Defines the symbol '#010, + '**2CX_Create als','o smartlinked library'#010+ + '**1d_Defines the symbol '#010+ '**1D_Generate a DEF file'#010+ '**2DD_Set the date string returned by %DATE% to x, it is not checke'+ 'd for being a valid date string'#010+ '**2Dd_Set description to '#010+ - '**2DT_Set the time string returned by %TIME% to x, it is not checke'+ - 'd for being',' a valid time string'#010+ + '**2DT_Set the time string',' returned by %TIME% to x, it is not chec'+ + 'ked for being a valid time string'#010+ '**2Dv_Set DLL version to '#010+ '*O2Dw_PM application'#010+ '**1e_Set path to executable'#010+ '**1E_Same as -Cn'#010+ '**1fPIC_Same as -Cg'#010+ '**1F_Set file names and paths:'#010+ - '**2Fa[,y]_(for a program) load units and [y] before uses ','is p'+ + '**2Fa[,y',']_(for a program) load units and [y] before uses is p'+ 'arsed'#010+ '**2Fc_Set input codepage to '#010+ '**2FC_Set RC compiler binary name to '#010+ '**2Fd_Disable the compiler'#039's internal directory cache'#010+ - '**2FD_Set the directory where to search for compiler utilities'#010+ - '**2Fe_Redirect error output ','to '#010+ + '**2FD_Set the directory where to search f','or compiler utilities'#010+ + '**2Fe_Redirect error output to '#010+ '**2FE_Set exe/unit output path to '#010+ '**2Ff_Add to framework path (Darwin only), or set IDF path to <'+ 'x> (Xtensa-FreeRTOS)'#010+ - '**2FF_Use fpcres as RC to RES compiler instead of windres or gorc'#010+ + '**2FF_Use fpcres as RC to RES compiler instead o','f windres or gorc'#010+ '**2Fi_Add to include path'#010+ - '**','2Fl_Add to library path'#010+ + '**2Fl_Add to library path'#010+ '**2FL_Use as dynamic linker'#010+ '**2Fm_Load unicode conversion table from .txt in the compiler di'+ 'r'#010+ - '**2FM_Set the directory where to search for unicode binary files'#010+ - '**2FN_Add to list of defaul','t unit scopes (namespaces)'#010+ + '**2FM_Set the directory where to search for un','icode binary files'#010+ + '**2FN_Add to list of default unit scopes (namespaces)'#010+ '**2Fo_Add to object path'#010+ '**2Fr_Load error message file '#010+ '**2FR_Set resource (.res) linker to '#010+ '**2Fu_Add to unit path'#010+ - '**2FU_Set unit output path to , overrides -FE'#010+ - '**2FW_Store gene','rated whole-program optimization feedback in '#010+ + '**2FU_Set unit ','output path to , overrides -FE'#010+ + '**2FW_Store generated whole-program optimization feedback in '#010+ '**2Fw_Load previously stored whole-program optimization feedback fr'+ 'om '#010+ '*g1g_Generate debug information (default format for target)'#010+ - '*g2gc_Generate checks for pointers (experimental, only',' available on '+ + '*','g2gc_Generate checks for pointers (experimental, only available on '+ 'some targets, might generate false positive)'#010+ '*g2gh_Use heaptrace unit (for memory leak/corruption debugging)'#010+ '*g2gl_Use line info unit (show more info with backtraces)'#010+ - '*g2gm_Generate Microsoft CodeView debug information (experi','mental)'#010+ + '*g2gm_','Generate Microsoft CodeView debug information (experimental)'#010+ '*g2go_Set debug information options'#010+ '*g3godwarfsets_ Enable DWARF '#039'set'#039' type debug information (bre'+ 'aks gdb < 6.5)'#010+ - '*g3gostabsabsincludes_ Store absolute/full include file paths in Stabs'+ - #010+ - '*g3godwarfmethodclassprefix_ Prefix method na','mes in DWARF with class'+ - ' name'#010+ + '*g3gostabsabsincludes_ Store absolute/full include file paths i','n Sta'+ + 'bs'#010+ + '*g3godwarfmethodclassprefix_ Prefix method names in DWARF with class n'+ + 'ame'#010+ '*g3godwarfcpp_ Simulate C++ debug information in DWARF'#010+ '*g3godwarfomflinnum_ Generate line number information in OMF LINNUM re'+ - 'cords in MS LINK format in addition to the DWARF debug information (Op'+ - 'en Watcom Debugg','er/Linker compatibility)'#010+ + 'cords in MS LINK format in additi','on to the DWARF debug information ('+ + 'Open Watcom Debugger/Linker compatibility)'#010+ '*g2gp_Preserve case in stabs symbol names'#010+ '*g2gs_Generate Stabs debug information'#010+ '*g2gt_Trash local variables (to detect uninitialized uses; multiple '#039+ - 't'#039' changes the trashing value)'#010+ - '*g2gv_Generates programs traceable',' with Valgrind'#010+ + 't'#039' changes t','he trashing value)'#010+ + '*g2gv_Generates programs traceable with Valgrind'#010+ '*g2gw_Generate DWARFv2 debug information (same as -gw2)'#010+ '*g2gw2_Generate DWARFv2 debug information'#010+ '*g2gw3_Generate DWARFv3 debug information'#010+ - '*g2gw4_Generate DWARFv4 debug information (experimental)'#010+ + '*g2gw4_Generate DWARFv4 debug in','formation (experimental)'#010+ '**1i_Information'#010+ - '**2iD_Retur','n compiler date'#010+ + '**2iD_Return compiler date'#010+ '**2iSO_Return compiler OS'#010+ '**2iSP_Return compiler host processor'#010+ '**2iTO_Return target OS'#010+ '**2iTP_Return target processor'#010+ '**2iV_Return short compiler version'#010+ - '**2iW_Return full compiler version'#010+ - '**2ia_Return list of supported ABI',' targets'#010+ + '**2iW_Return ful','l compiler version'#010+ + '**2ia_Return list of supported ABI targets'#010+ '**2ib_Return the used code generation backend type'#010+ '**2ic_Return list of supported CPU instruction sets'#010+ '**2if_Return list of supported FPU instruction sets'#010+ - '**2ii_Return list of supported inline assembler modes'#010+ - '**2im_Return list of s','upported modeswitches'#010+ + '**2ii_Return list of su','pported inline assembler modes'#010+ + '**2im_Return list of supported modeswitches'#010+ '**2io_Return list of supported optimizations'#010+ '**2ir_Return list of recognized compiler and RTL features'#010+ '**2it_Return list of supported targets'#010+ - '**2iu_Return list of supported microcontroller types'#010+ - '**2iw_Return list of su','pported whole program optimizations'#010+ + '**2iu_Return list of su','pported microcontroller types'#010+ + '**2iw_Return list of supported whole program optimizations'#010+ '**1I_Add to include path'#010+ '**1k_Pass to the linker'#010+ '**1l_Write logo'#010+ '**1M_Set language mode to / enable modeswitch (see option -'+ - 'im)'#010+ + 'im',')'#010+ '**2Mfpc_Free Pascal dialect (default)'#010+ - '**2Mobjfpc_FP','C mode with Object Pascal support'#010+ + '**2Mobjfpc_FPC mode with Object Pascal support'#010+ '**2Mdelphi_Delphi 7 compatibility mode'#010+ '**2Mtp_TP/BP 7.0 compatibility mode'#010+ '**2Mmacpas_Macintosh Pascal dialects compatibility mode'#010+ - '**2Miso_ISO 7185 mode'#010+ + '**2Miso_ISO 7185 mode'#010, '**2Mextendedpascal_ISO 10206 mode'#010+ - '**2Mdelphiunicode_D','elphi 2009 and later compatibility mode'#010+ + '**2Mdelphiunicode_Delphi 2009 and later compatibility mode'#010+ '**2*_Each mode (as listed above) enables its default set of modeswitch'+ 'es.'#010+ '**2*_Other modeswitches are disabled and need to be enabled one by ano'+ - 'ther.'#010+ + 'the','r.'#010+ '**1M-_Disable modeswitch (see option -im)'#010+ - '*','*1n_Do not read the default config files'#010+ + '**1n_Do not read the default config files'#010+ '**1o_Change the name of the executable produced to '#010+ '**1O_Optimizations:'#010+ '**2O-_Disable optimizations'#010+ - '**2O1_Level 1 optimizations (quick and debugger friendly)'#010+ - '**2O2_Level 2 optimizations (-O1',' + quick optimizations)'#010+ + '**2O1_Level 1 optimizations (quick an','d debugger friendly)'#010+ + '**2O2_Level 2 optimizations (-O1 + quick optimizations)'#010+ '**2O3_Level 3 optimizations (-O2 + slow optimizations)'#010+ '**2O4_Level 4 optimizations (-O3 + optimizations which might have unex'+ 'pected side effects)'#010+ - '**2Oa=_Set alignment'#010+ - '**2Oo[NO]_Enable or disable optimization','s; see fpc -i or fpc -io '+ - 'for possible values'#010+ + '**2Oa=_Set ','alignment'#010+ + '**2Oo[NO]_Enable or disable optimizations; see fpc -i or fpc -io fo'+ + 'r possible values'#010+ '**2Op_Set target cpu for optimizing; see fpc -i or fpc -ic for poss'+ 'ible values'#010+ - '**2OW_Generate whole-program optimization feedback for optimization'+ - ' ; see fpc -i or fpc -iw for possible va','lues'#010+ + '**2OW_Generate whole-program optimization feedback for op','timizati'+ + 'on ; see fpc -i or fpc -iw for possible values'#010+ '**2Ow_Perform whole-program optimization ; see fpc -i or fpc -iw'+ ' for possible values'#010+ '**2Os_Optimize for size rather than speed'#010+ - '**1pg_Generate profile code for gprof (defines FPC_PROFILE)'#010+ - 'F*1P_Target CPU / compiler related opti','ons:'#010+ + '**1pg_Generate profile code for gprof (defines FP','C_PROFILE)'#010+ + 'F*1P_Target CPU / compiler related options:'#010+ 'F*2PB_Show default compiler binary'#010+ 'F*2PP_Show default target cpu'#010+ 'F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipse'+ 'l,powerpc,powerpc64,sparc,x86_64)'#010+ - '**1R_Assembler reading style:'#010+ - '**2Rdefault_Use default assembler',' for target'#010+ + '**1R_Assem','bler reading style:'#010+ + '**2Rdefault_Use default assembler for target'#010+ '3*2Ratt_Read AT&T style assembler'#010+ '3*2Rintel_Read Intel style assembler'#010+ '4*2Ratt_Read AT&T style assembler'#010+ '4*2Rintel_Read Intel style assembler'#010+ - '8*2Ratt_Read AT&T style assembler'#010+ + '8*2Ratt_Read AT&T style assembler',#010+ '8*2Rintel_Read Intel style assembler'#010+ - '6*2RMOT_Read Mo','torola style assembler'#010+ + '6*2RMOT_Read Motorola style assembler'#010+ '**1S_Syntax options:'#010+ '**2S2_Same as -Mobjfpc'#010+ '**2Sc_Support operators like C (*=,+=,/= and -=)'#010+ '**2Sa_Turn on assertions'#010+ '**2Sd_Same as -Mdelphi'#010+ - '**2Se_Error options. is a combination of the following:'#010+ - '**3*_ :',' Compiler halts after the errors (default is 1)'#010+ + '**2Se_Error optio','ns. is a combination of the following:'#010+ + '**3*_ : Compiler halts after the errors (default is 1)'#010+ '**3*_w : Compiler also halts after warnings'#010+ '**3*_n : Compiler also halts after notes'#010+ '**3*_h : Compiler also halts after hints'#010+ - '**2Sf_Enable certain features in compiler and RTL; see fpc -i ','or fpc'+ + '**2Sf_Ena','ble certain features in compiler and RTL; see fpc -i or fpc'+ ' -ir for possible values)'#010+ '**2Sg_Enable LABEL and GOTO (default in -Mtp and -Mdelphi)'#010+ '**2Sh_Use reference counted strings (ansistring by default) instead of'+ ' shortstrings'#010+ - '**2Si_Turn on inlining of procedures/functions declared as "inlin','e"'#010+ + '**2Si_Turn o','n inlining of procedures/functions declared as "inline"'#010+ '**2Sj_Allows typed constants to be writeable (default in all modes)'#010+ '**2Sk_Load fpcylix unit'#010+ '**2SI_Set interface style to '#010+ '**3SIcom_COM compatible interface (default)'#010+ - '**3SIcorba_CORBA compatible interface'#010+ - '**2sT_Generate script only ','to link on target'#010+ + '**3SIcorba_C','ORBA compatible interface'#010+ '**2Sm_Support macros like C (global)'#010+ '**2So_Same as -Mtp'#010+ '**2Sr_Transparent file names in ISO mode'#010+ '**2Ss_Constructor name must be init (destructor must be done)'#010+ - '**2Sv_Support vector processing (use CPU vector extensions if a','vaila'+ + '**2Sv_Support vector processing (use CPU vector extensi','ons if availa'+ 'ble)'#010+ '**2Sx_Enable exception keywords (default in Delphi/ObjFPC modes)'#010+ '**2Sy_@ returns a typed pointer, same as $T+'#010+ '**1s_Do not call assembler and linker'#010+ - '**2sh_Generate script to link on host'#010+ - '**2st_Generate script to assemble a','nd link on target'#010+ - '**2sr_Skip register allocation phase (use with -alr)'#010+ + '**2sh_Generate script to link on host, automatically switches to ','ext'+ + 'ernal assembler writer'#010+ + '**2sT_Generate script only to link on target'#010+ + '**2st_Generate script to assemble and link on target, automatically sw'+ + 'itches to external assembler writer'#010+ + '**2sr_Skip register allocation phase (use with -alr), automatic','ally '+ + 'switches to external assembler writer'#010+ '**1T_Target operating system:'#010+ '3*2Tandroid_Android'#010+ '3*2Taros_AROS'#010+ '3*2Tbeos_BeOS'#010+ '3*2Tdarwin_Darwin/Mac OS X'#010+ '3*2Tembedded_Embedded'#010+ - '3*2Temx_OS/2 via EMX (including EMX/RSX',' extender)'#010+ - '3*2Tfreebsd_FreeBSD'#010+ + '3*2Temx_OS/2 via EMX (including EMX/RSX extender)'#010+ + '3*2Tfreebsd_FreeB','SD'#010+ '3*2Tgo32v2_Version 2 of DJ Delorie DOS extender'#010+ '3*2Thaiku_Haiku'#010+ '3*2Tiphonesim_iPhoneSimulator from iOS SDK 3.2+ (older versions: -Tdar'+ 'win)'#010+ '3*2Tlinux_Linux'#010+ '3*2Tnativent_Native NT API (experimental)'#010+ - '3*2Tnetbsd_N','etBSD'#010+ - '3*2Tnetware_Novell Netware Module (clib)'#010+ + '3*2Tnetbsd_NetBSD'#010+ + '3*2Tnetware_Novell Net','ware Module (clib)'#010+ '3*2Tnetwlibc_Novell Netware Module (libc)'#010+ '3*2Topenbsd_OpenBSD'#010+ '3*2Tos2_OS/2 / eComStation'#010+ '3*2Tsymbian_Symbian OS'#010+ '3*2Tsolaris_Solaris'#010+ '3*2Twatcom_Watcom compatible DOS extender'#010+ - '3*2Twdosx_WDOSX DOS',' extender'#010+ - '3*2Twin32_Windows 32 Bit'#010+ + '3*2Twdosx_WDOSX DOS extender'#010+ + '3*2Twin32_Windows ','32 Bit'#010+ '3*2Twince_Windows CE'#010+ '4*2Tandroid_Android'#010+ '4*2Taros_AROS'#010+ @@ -1809,9 +1813,9 @@ const msgtxt : array[0..000366,1..240] of char=( '4*2Tfreebsd_FreeBSD'#010+ '4*2Thaiku_Haiku'#010+ '4*2Tiphonesim_iPhoneSimulator'#010+ - '4*2Tlin','ux_Linux'#010+ + '4*2Tlinux_Linux'#010+ '4*2Tnetbsd_NetBSD'#010+ - '4*2Topenbsd_OpenBSD'#010+ + '4','*2Topenbsd_OpenBSD'#010+ '4*2Tsolaris_Solaris'#010+ '4*2Twin64_Win64 (64 bit Windows systems)'#010+ '6*2Tamiga_Commodore Amiga'#010+ @@ -1819,9 +1823,9 @@ const msgtxt : array[0..000366,1..240] of char=( '6*2Tembedded_Embedded'#010+ '6*2Tlinux_Linux'#010+ '6*2Tnetbsd_NetBSD'#010+ - '6*2Tmacosclassic_Classic',' Mac OS'#010+ + '6*2Tmacosclassic_Classic Mac OS'#010+ '6*2Tpalmos_PalmOS'#010+ - '6*2Tsinclairql_Sinclair QL'#010+ + '6*','2Tsinclairql_Sinclair QL'#010+ '8*2Tembedded_Embedded'#010+ '8*2Tmsdos_MS-DOS (and compatible)'#010+ '8*2Twin16_Windows 16 Bit'#010+ @@ -1830,9 +1834,9 @@ const msgtxt : array[0..000366,1..240] of char=( 'A*2Tembedded_Embedded'#010+ 'A*2Tfreertos_FreeRTOS'#010+ 'A*2Tgba_Game Boy Advance'#010+ - 'A*2','Tios_iOS'#010+ + 'A*2Tios_iOS'#010+ 'A*2Tlinux_Linux'#010+ - 'A*2Tnds_Nintendo DS'#010+ + 'A*2','Tnds_Nintendo DS'#010+ 'A*2Tnetbsd_NetBSD'#010+ 'A*2Tpalmos_PalmOS'#010+ 'A*2Tsymbian_Symbian'#010+ @@ -1843,8 +1847,8 @@ const msgtxt : array[0..000366,1..240] of char=( 'a*2Tios_iOS'#010+ 'a*2Tlinux_Linux'#010+ 'a*2Twin64_Windows 64'#010+ - 'J*','2Tandroid_Android'#010+ - 'J*2Tjava_Java'#010+ + 'J*2Tandroid_Android'#010+ + 'J*2Tjava_J','ava'#010+ 'm*2Tandroid_Android'#010+ 'm*2Tembedded_Embedded'#010+ 'm*2Tlinux_Linux'#010+ @@ -1855,8 +1859,8 @@ const msgtxt : array[0..000366,1..240] of char=( 'P*2Tdarwin_Darwin/Mac OS X'#010+ 'P*2Tembedded_Embedded'#010+ 'P*2Tlinux_Linux'#010+ - 'P*2Tmacosclassic_','Classic Mac OS'#010+ - 'P*2Tmorphos_MorphOS'#010+ + 'P*2Tmacosclassic_Classic Mac OS'#010+ + 'P*2Tmorphos_M','orphOS'#010+ 'P*2Tnetbsd_NetBSD'#010+ 'P*2Twii_Wii'#010+ 'p*2Taix_AIX'#010+ @@ -1868,8 +1872,8 @@ const msgtxt : array[0..000366,1..240] of char=( 'r*2Tlinux_Linux'#010+ 'r*2Tembedded_Embedded'#010+ 'S*2Tlinux_Linux'#010+ - 'S*2Tso','laris_Solaris'#010+ - 's*2Tlinux_Linux'#010+ + 'S*2Tsolaris_Solaris'#010+ + 's*2Tlinux_Linu','x'#010+ 'V*2Tembedded_Embedded'#010+ 'x*2Tembedded_Embedded'#010+ 'x*2Tfreertos_FreeRTOS'#010+ @@ -1878,157 +1882,158 @@ const msgtxt : array[0..000366,1..240] of char=( 'Z*2Tzxspectrum_ZX Spectrum'#010+ 'Z*2Tmsxdos_MSX-DOS'#010+ 'W*2Tembedded_Embedded'#010+ - 'W*2Twasi_The WebAssembly System Interf','ace (WASI)'#010+ - '**1u_Undefines the symbol '#010+ + 'W*2Twasi_The WebAssembly System Interface (WASI)'#010+ + '**1u_Undefines',' the symbol '#010+ '**1U_Unit options:'#010+ '**2Un_Do not check where the unit name matches the file name'#010+ '**2Ur_Generate release unit files (never automatically recompiled)'#010+ '**2Us_Compile a system unit'#010+ - '**1v_Be verbose. <','x> is a combination of the following letters:'#010+ + '**1v_Be verbose. is a combination of the f','ollowing letters:'#010+ '**2*_e : Show errors (default) 0 : Show nothing (except errors)'#010+ '**2*_w : Show warnings u : Show unit info'#010+ '**2*_n : Show notes t : Show tried/used files'#010+ - '**2*_','h : Show hints c : Show conditionals'#010+ + '**2*_h : Show hints ',' c : Show conditionals'#010+ '**2*_i : Show general info d : Show debug info'#010+ '**2*_l : Show linenumbers r : Rhide/GCC compatibility mode'#010+ - '**2*_s : Show time stamps q : Show message numbe','rs'#010+ - '**2*_a : Show everything x : Show info about invoked tools'+ - #010+ + '**2*_s : Show time stamps q : Show message numbers'#010+ + '**2*_a : Show everything ',' x : Show info about invoked too'+ + 'ls'#010+ '**2*_b : Write file names messages p : Write tree.log with parse tre'+ 'e'#010+ '**2*_ with full path v : Write fpcdebug.txt with'#010+ - '**2*_z : Write output to stde','rr lots of debugging info'#010+ + '**2*_z : Write output to stderr lots of debuggin','g info'#010+ '**2*_m, : Do not show messages numbered and '#010+ 'F*1V_Append '#039'-'#039' to the used compiler binary name (e.g. f'+ 'or version)'#010+ '**1W_Target-specific options (targets)'#010+ - '3*2WA_Specify native type appli','cation (Windows)'#010+ - '4*2WA_Specify native type application (Windows)'#010+ + '3*2WA_Specify native type application (Windows)'#010+ + '4*2WA_Speci','fy native type application (Windows)'#010+ 'A*2WA_Specify native type application (Windows)'#010+ '3*2Wb_Create a bundle instead of a library (Darwin)'#010+ 'P*2Wb_Create a bundle instead of a library (Darwin)'#010+ - 'p*2Wb_Create a bundle i','nstead of a library (Darwin)'#010+ + 'p*2Wb_Create a bundle instead of a library (Darwin)',#010+ 'a*2Wb_Create a bundle instead of a library (Darwin)'#010+ 'A*2Wb_Create a bundle instead of a library (Darwin)'#010+ '4*2Wb_Create a bundle instead of a library (Darwin)'#010+ '3*2WB_Create a relocatable image (Windows, Symbian)'#010+ - '3*2','WB_Set image base to (Windows, Symbian)'#010+ + '3*2WB_Set image base to ','(Windows, Symbian)'#010+ '4*2WB_Create a relocatable image (Windows)'#010+ '4*2WB_Set image base to (Windows)'#010+ 'A*2WB_Create a relocatable image (Windows, Symbian)'#010+ 'A*2WB_Set image base to (Windows, Symbian)'#010+ - 'Z*2WB_Set image base to (ZX Spectrum)'#010+ + 'Z*2WB_Set image base to (ZX ','Spectrum)'#010+ '3*2WC_Specify console type application (EMX, OS/2, Windows)'#010+ '4*2WC_Specify console type application (Windows)'#010+ 'A*2WC_Specify console type application (Windows)'#010+ - 'P*2WC_Specify console type application (Clas','sic Mac OS)'#010+ - '3*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ + 'P*2WC_Specify console type application (Classic Mac OS)'#010+ + '3*2WD_Use DEFFIL','E to export functions of DLL or EXE (Windows)'#010+ '4*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ 'A*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ '3*2We_Use external resources (Darwin)'#010+ - '4*2W','e_Use external resources (Darwin)'#010+ + '4*2We_Use external resources (Da','rwin)'#010+ 'a*2We_Use external resources (Darwin)'#010+ 'A*2We_Use external resources (Darwin)'#010+ 'P*2We_Use external resources (Darwin)'#010+ 'p*2We_Use external resources (Darwin)'#010+ - '3*2WF_Specify full-screen type application (EMX, OS/2)',#010+ - '3*2WG_Specify graphic type application (EMX, OS/2, Windows)'#010+ + '3*2WF_Specify full-screen type application (EMX, OS/2)'#010+ + '3*2WG_Specify graphic type ','application (EMX, OS/2, Windows)'#010+ '4*2WG_Specify graphic type application (Windows)'#010+ 'A*2WG_Specify graphic type application (Windows)'#010+ 'P*2WG_Specify graphic type application (Classic Mac OS)'#010+ - '3*2Wi_Use internal resour','ces (Darwin)'#010+ - '4*2Wi_Use internal resources (Darwin)'#010+ + '3*2Wi_Use internal resources (Darwin)'#010+ + '4*2Wi_Use inter','nal resources (Darwin)'#010+ 'a*2Wi_Use internal resources (Darwin)'#010+ 'A*2Wi_Use internal resources (Darwin)'#010+ 'P*2Wi_Use internal resources (Darwin)'#010+ 'p*2Wi_Use internal resources (Darwin)'#010+ - '3*2WI_Turn on/off the usage of import',' sections (Windows)'#010+ - '4*2WI_Turn on/off the usage of import sections (Windows)'#010+ + '3*2WI_Turn on/off the usage of import sections (Windows)'#010+ + '4*2WI_Tu','rn on/off the usage of import sections (Windows)'#010+ 'A*2WI_Turn on/off the usage of import sections (Windows)'#010+ '8*2Wh_Use huge code for units (ignored for models with CODE in a uniqu'+ 'e segment)'#010+ - '8*2Wm_Set memory model',#010+ - '8*3WmTiny_Tiny memory model'#010+ + '8*2Wm_Set memory model'#010+ + '8*3WmTiny_Tiny memory model',#010+ '8*3WmSmall_Small memory model (default)'#010+ '8*3WmMedium_Medium memory model'#010+ '8*3WmCompact_Compact memory model'#010+ '8*3WmLarge_Large memory model'#010+ '8*3WmHuge_Huge memory model'#010+ - '3*2WM_Minimum Mac OS X deployment version: 1','0.4, 10.5.1, ... (Dar'+ - 'win)'#010+ - '4*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ + '3*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ + '4*','2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Dar'+ + 'win)'#010+ 'p*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ - 'P*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Dar','w'+ - 'in)'#010+ - '3*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ + 'P*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ + 'n)'#010+ + '3*2WN_Do not generate r','elocation code, needed for debugging (Windows'+ + ')'#010+ '4*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ 'A*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ - 'A*2Wp_Specify the cont','roller type; see fpc -i or fpc -iu for poss'+ + 'A*2Wp_Specify the controller type; see fpc -i or f','pc -iu for poss'+ 'ible values'#010+ 'm*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ 'R*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ - 'V*2Wp_Specify the cont','roller type; see fpc -i or fpc -iu for poss'+ + 'V*2Wp_Specify the controller type; see fpc -i or f','pc -iu for poss'+ 'ible values'#010+ 'x*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ '3*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (iphonesim)'#010+ - '4*2WP_Minimum iOS deployment vers','ion: 8.0, 8.0.2, ... (iphonesim)'+ + '4*2WP_Minimum iOS deployment version: 8.0, 8.0.2, ... (iphone','sim)'+ #010+ 'a*2WP_Minimum iOS deployment version: 7.0, 7.1.2, ... (Darwin)'#010+ 'A*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (Darwin)'#010+ '3*2WR_Generate relocation code (Windows)'#010+ - '4*2WR_Generate relocation code (Wi','ndows)'#010+ - 'A*2WR_Generate relocation code (Windows)'#010+ + '4*2WR_Generate relocation code (Windows)'#010+ + 'A*2WR_Generate reloca','tion code (Windows)'#010+ '8*2Wt_Set the target executable format'#010+ '8*3Wtexe_Create a DOS .EXE file (default)'#010+ '8*3Wtcom_Create a DOS .COM file (requires tiny memory model)'#010+ - 'P*2WT_Specify MPW tool type application (Classi','c Mac OS)'#010+ - '6*2WQ_Set executable metadata format (Sinclair QL)'#010+ + 'P*2WT_Specify MPW tool type application (Classic Mac OS)'#010+ + '6*2WQ_Set execu','table metadata format (Sinclair QL)'#010+ '6*3WQqhdr_Set metadata to QDOS File Header style (default)'#010+ '6*3WQxtcc_Set metadata to XTcc style'#010+ '**2WX_Enable executable stack (Linux)'#010+ '**1X_Executable options:'#010+ - '**2X9_Generate li','nkerscript for GNU Binutils ld older than version 2'+ + '**2X9_Generate linkerscript for GNU Binutils ','ld older than version 2'+ '.19.1 (Linux)'#010+ '**2Xa_Generate code which allows to use more than 2 GB static data on '+ '64 Bit targets (Linux)'#010+ '**2Xc_Pass --shared/-dynamic to the linker (BeOS, Darwin, FreeBSD, Lin'+ 'ux)'#010+ - '**2Xd_Do',' not search default library path (sometimes required for cro'+ + '**2Xd_Do not search default library ','path (sometimes required for cro'+ 'ss-compiling when not using -XR)'#010+ '**2Xe_Use external linker'#010+ '**2Xf_Substitute pthread library name for linking (BSD)'#010+ - '**2Xg_Create debuginfo in a separate file and add a debuglink sec','tio'+ - 'n to executable'#010+ - '**2XD_Try to link units dynamically (defines FPC_LINK_DYNAMIC)'#010+ + '**2Xg_Create debuginfo in a separate file and add a debuglink section '+ + 'to executable'#010+ + '**2XD_Try',' to link units dynamically (defines FPC_LINK_DYNAMIC)'#010+ '**2Xi_Use internal linker'#010+ 'L*2XlS_LLVM utilties suffix (e.g. -7 in case clang is called clang-'+ '7)'#010+ '**2XLA_Define library substitutions for linking'#010+ - '**2XLO','_Define order of library linking'#010+ + '**2XLO_Define order of library lin','king'#010+ '**2XLD_Exclude default order of standard libraries'#010+ '**2Xm_Generate link map'#010+ '**2XM_Set the name of the '#039'main'#039' program routine (default i'+ 's '#039'main'#039')'#010+ - '**2Xn_Use target system native linker instead of GNU ld (Sol','aris, AI'+ - 'X)'#010+ - 'F*2Xp_First search for the compiler binary in the directory '#010+ + '**2Xn_Use target system native linker instead of GNU ld (Solaris, AIX)'+ + #010+ + 'F*2Xp_First se','arch for the compiler binary in the directory '#010+ '**2XP_Prepend the binutils names with the prefix '#010+ '**2Xr_Set the linker'#039's rlink-path to (needed for cross comp'+ - 'ile, see the ld manual for more informat','ion) (BeOS, Linux)'#010+ - '**2XR_Prepend to all linker search paths (BeOS, Darwin, FreeBSD'+ - ', Linux, Mac OS, Solaris)'#010+ + 'ile, see the ld manual for more information) (BeOS, Linux)'#010+ + '**2XR_','Prepend to all linker search paths (BeOS, Darwin, FreeB'+ + 'SD, Linux, Mac OS, Solaris)'#010+ '**2Xs_Strip all symbols from executable'#010+ '**2XS_Try to link units statically (default, defines FPC_LINK_STATIC)'#010+ - '**2Xt_Link with',' static libraries (-static is passed to linker)'#010+ + '**2Xt_Link with static libraries (-static i','s passed to linker)'#010+ '**2Xu_Generate executable in UF2 format (embedded targets only)'#010+ '**2Xv_Generate table for Virtual Entry calls'#010+ '**2XV_Use VLink as external linker (default on Amiga, MorphOS)'#010+ - '**2XX_Try to ','smartlink units (defines FPC_LINK_SMART)'#010+ + '**2XX_Try to smartlink units ','(defines FPC_LINK_SMART)'#010+ '**1*_'#010+ '**1?_Show this help'#010+ '**1h_Shows this help without waiting' diff --git a/compiler/options.pas b/compiler/options.pas index f88d814577..a301518ab6 100644 --- a/compiler/options.pas +++ b/compiler/options.pas @@ -1356,7 +1356,10 @@ begin 'A' : begin - paratargetasm:=find_asm_by_string(More); + if CompareText(More,'DEFAULT') = 0 then + paratargetasm:=as_default + else + paratargetasm:=find_asm_by_string(More); if paratargetasm=as_none then IllegalPara(opt); end; @@ -4423,6 +4426,10 @@ begin { maybe override assembler } if (option.paratargetasm<>as_none) then begin + if (option.paratargetasm=as_default) then + begin + option.paratargetasm:=target_info.assem; + end; if not set_target_asm(option.paratargetasm) then begin if assigned(asminfos[option.paratargetasm]) then diff --git a/compiler/systems.inc b/compiler/systems.inc index 70bc884f49..426275b6e7 100644 --- a/compiler/systems.inc +++ b/compiler/systems.inc @@ -209,6 +209,7 @@ type tasm = (as_none + ,as_default ,as_gas { standard gnu assembler } ,as_i386_as_aout ,as_i386_nasmcoff diff --git a/compiler/systems.pas b/compiler/systems.pas index 536fe43269..3d4dae0f7c 100644 --- a/compiler/systems.pas +++ b/compiler/systems.pas @@ -218,7 +218,7 @@ interface newline : string[2]; dirsep : char; assem : tasm; - assemextern : tasm; { external assembler, used by -a } + assemextern : tasm; { external assembler, used by -a and -s } link : tlink; linkextern : tlink; { external linker, used by -s } ar : tar; From a18a6b4391ee8c0786fdbccf8154949b41be86b1 Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 24 Aug 2021 23:16:52 +0200 Subject: [PATCH 097/116] + Aarch64: FMovFMov2FMov 2 optimization --- compiler/aarch64/aoptcpu.pas | 42 +++++++++++++++++++++++++++++++++++- compiler/avr/aoptcpu.pas | 2 ++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/compiler/aarch64/aoptcpu.pas b/compiler/aarch64/aoptcpu.pas index 340e451407..f8570794f9 100644 --- a/compiler/aarch64/aoptcpu.pas +++ b/compiler/aarch64/aoptcpu.pas @@ -549,6 +549,7 @@ Implementation function TCpuAsmOptimizer.OptPass1FMov(var p: tai): Boolean; var hp1: tai; + alloc, dealloc: tai_regalloc; begin { change @@ -565,9 +566,48 @@ Implementation begin asml.Remove(hp1); hp1.free; - DebugMsg(SPeepholeOptimization + 'FMovFMov2FMov done', p); + DebugMsg(SPeepholeOptimization + 'FMovFMov2FMov 1 done', p); Result:=true; end; + + { change + fmov reg0,const + fmov reg1,reg0 + dealloc reg0 + into + fmov reg1,const + } + if MatchOpType(taicpu(p),top_reg,top_realconst) and + GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and + (not RegModifiedBetween(taicpu(p).oper[1]^.reg, p, hp1)) and + MatchInstruction(hp1,A_FMOV,[taicpu(p).condition],[taicpu(p).oppostfix]) and + MatchOpType(taicpu(hp1),top_reg,top_reg) and + MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^.reg) and + (not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1)) and + assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) + then + begin + DebugMsg('Peephole FMovFMov2FMov 2 done', p); + + taicpu(hp1).loadrealconst(1,taicpu(p).oper[1]^.val_real); + + alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous)); + dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next)); + + if assigned(alloc) and assigned(dealloc) then + begin + asml.Remove(alloc); + alloc.Free; + asml.Remove(dealloc); + dealloc.Free; + end; + + { p will be removed, update used register as we continue + with the next instruction after p } + + result:=RemoveCurrentP(p); + end; + { not enabled as apparently not happening if MatchOpType(taicpu(p),top_reg,top_reg) and GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and diff --git a/compiler/avr/aoptcpu.pas b/compiler/avr/aoptcpu.pas index 82263f07e8..56b20353d9 100644 --- a/compiler/avr/aoptcpu.pas +++ b/compiler/avr/aoptcpu.pas @@ -1373,6 +1373,8 @@ Implementation A_SBIC, A_SBIS: Result:=OptPass1SBI(p); + A_FMOV: + Result:=OptPass1FMOV; end; end; end; From 4a67f098ee5f2077417ed8b47e6912a0e4794d1e Mon Sep 17 00:00:00 2001 From: florian Date: Wed, 25 Aug 2021 10:41:03 +0200 Subject: [PATCH 098/116] * reverted wrongly committed file --- compiler/avr/aoptcpu.pas | 2 -- 1 file changed, 2 deletions(-) diff --git a/compiler/avr/aoptcpu.pas b/compiler/avr/aoptcpu.pas index 56b20353d9..82263f07e8 100644 --- a/compiler/avr/aoptcpu.pas +++ b/compiler/avr/aoptcpu.pas @@ -1373,8 +1373,6 @@ Implementation A_SBIC, A_SBIS: Result:=OptPass1SBI(p); - A_FMOV: - Result:=OptPass1FMOV; end; end; end; From 0919916ba7102963f41214f2590bc874eeff20d9 Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 12:26:00 +0000 Subject: [PATCH 099/116] Initial .gitlab-ci.yml file --- .gitlab-ci.yml | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 .gitlab-ci.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 0000000000..68600c565c --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,47 @@ +# This file is a template, and might need editing before it works on your project. +# To contribute improvements to CI/CD templates, please follow the Development guide at: +# https://docs.gitlab.com/ee/development/cicd/templates.html +# This specific template is located at: +# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml + +# This is a sample GitLab CI/CD configuration file that should run without any modifications. +# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts, +# it uses echo commands to simulate the pipeline execution. +# +# A pipeline is composed of independent jobs that run scripts, grouped into stages. +# Stages run in sequential order, but jobs within stages run in parallel. +# +# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages + +image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild + +stages: # List of stages for jobs, and their order of execution + - build + - test + - deploy + +build-job: # This job runs in the build stage, which runs first. + stage: build + script: + - echo "Compiling the code..." + - echo "Compile complete." + +unit-test-job: # This job runs in the test stage. + stage: test # It only starts when the job in the build stage completes successfully. + script: + - echo "Running unit tests... This will take about 60 seconds." + - sleep 60 + - echo "Code coverage is 90%" + +lint-test-job: # This job also runs in the test stage. + stage: test # It can run at the same time as unit-test-job (in parallel). + script: + - echo "Linting code... This will take about 10 seconds." + - sleep 10 + - echo "No lint issues found." + +deploy-job: # This job runs in the deploy stage. + stage: deploy # It only runs when *both* jobs in the test stage complete successfully. + script: + - echo "Deploying application..." + - echo "Application successfully deployed." From ff69b7479e8b683b1c2acbcee5fa4025374f1a51 Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 12:33:57 +0000 Subject: [PATCH 100/116] Added make command to .gitlab-ci.yml --- .gitlab-ci.yml | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 68600c565c..d83a2bb170 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,26 +4,17 @@ # This specific template is located at: # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml -# This is a sample GitLab CI/CD configuration file that should run without any modifications. -# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts, -# it uses echo commands to simulate the pipeline execution. -# -# A pipeline is composed of independent jobs that run scripts, grouped into stages. -# Stages run in sequential order, but jobs within stages run in parallel. -# -# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages - image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild stages: # List of stages for jobs, and their order of execution - build - test - - deploy build-job: # This job runs in the build stage, which runs first. stage: build script: - echo "Compiling the code..." + - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 OPT="-gl" FPMAKEOPT="-T 4" - echo "Compile complete." unit-test-job: # This job runs in the test stage. @@ -32,16 +23,3 @@ unit-test-job: # This job runs in the test stage. - echo "Running unit tests... This will take about 60 seconds." - sleep 60 - echo "Code coverage is 90%" - -lint-test-job: # This job also runs in the test stage. - stage: test # It can run at the same time as unit-test-job (in parallel). - script: - - echo "Linting code... This will take about 10 seconds." - - sleep 10 - - echo "No lint issues found." - -deploy-job: # This job runs in the deploy stage. - stage: deploy # It only runs when *both* jobs in the test stage complete successfully. - script: - - echo "Deploying application..." - - echo "Application successfully deployed." From db677c9fe3893752b58c83a3d716617ec82d7efb Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 12:48:51 +0000 Subject: [PATCH 101/116] * Cleaned up .gitlab-ci.yml * Added regression testing --- .gitlab-ci.yml | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d83a2bb170..393a66121b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,8 +1,7 @@ -# This file is a template, and might need editing before it works on your project. -# To contribute improvements to CI/CD templates, please follow the Development guide at: -# https://docs.gitlab.com/ee/development/cicd/templates.html -# This specific template is located at: +# This .gitlab.ci.yml is based on: # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml +# the FPC specific parts are partly from: +# https://gitlab.com/alb42/testconversion2/-/blob/main/.gitlab-ci.yml image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild @@ -13,13 +12,14 @@ stages: # List of stages for jobs, and their order of execution build-job: # This job runs in the build stage, which runs first. stage: build script: - - echo "Compiling the code..." - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 OPT="-gl" FPMAKEOPT="-T 4" - - echo "Compile complete." - -unit-test-job: # This job runs in the test stage. - stage: test # It only starts when the job in the build stage completes successfully. + +regression-test-job: # This job runs in the test stage. + stage: test # It only starts when the job in the build stage completes successfully. script: - - echo "Running unit tests... This will take about 60 seconds." - - sleep 60 - - echo "Code coverage is 90%" + - FPC_SRC=$(pwd) + - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 + - cd tests + - make clean TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 + - make full TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 + From 21914bf43bac54b0d18d6e97702b44d7061f174f Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 12:57:49 +0000 Subject: [PATCH 102/116] * build and test must be one job --- .gitlab-ci.yml | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 393a66121b..2bdcfcefc6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -6,17 +6,12 @@ image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild stages: # List of stages for jobs, and their order of execution - - build - - test + - buildandtest -build-job: # This job runs in the build stage, which runs first. - stage: build +build-and-test-job: # This job runs in the build stage, which runs first. + stage: buildandtest script: - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 OPT="-gl" FPMAKEOPT="-T 4" - -regression-test-job: # This job runs in the test stage. - stage: test # It only starts when the job in the build stage completes successfully. - script: - FPC_SRC=$(pwd) - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 - cd tests From 2be893cb179ac147d3df8cb74189a40455e2864d Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 15:04:59 +0000 Subject: [PATCH 103/116] + build fpts2junit + generate testresult.xml artifact --- .gitlab-ci.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2bdcfcefc6..a1907f0dcb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -11,10 +11,20 @@ stages: # List of stages for jobs, and their order of execution build-and-test-job: # This job runs in the build stage, which runs first. stage: buildandtest script: - - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 OPT="-gl" FPMAKEOPT="-T 4" + - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 FPMAKEOPT="-T 4" - FPC_SRC=$(pwd) - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 - cd tests + - cd utils + - make fpts2junit + - cd .. - make clean TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 - make full TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 - + - cd $FPC_SRC + - tests/utils/fpts2junit $FPC_SRC/tests/output/x86_64-linux/ testresult.xml + artifacts: + when: always + paths: + - testresult.xml + reports: + junit: testresult.xml From 683e5b873b5c7d00f56fd9178ffc3656dfb4b89a Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 15:11:39 +0000 Subject: [PATCH 104/116] * build fpts2junit after testing so all directories are present --- .gitlab-ci.yml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a1907f0dcb..9bff62d20d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -15,11 +15,10 @@ build-and-test-job: # This job runs in the build stage, which runs first. - FPC_SRC=$(pwd) - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 - cd tests - - cd utils - - make fpts2junit - - cd .. - make clean TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 - make full TEST_FPC=$FPC_COMPILER TEST_DELTEMP=1 -j 4 + - cd utils + - make fpts2junit - cd $FPC_SRC - tests/utils/fpts2junit $FPC_SRC/tests/output/x86_64-linux/ testresult.xml artifacts: From 98574a88a3546b679b5a83afaff710b6123a759a Mon Sep 17 00:00:00 2001 From: FPK Date: Thu, 26 Aug 2021 16:03:26 +0000 Subject: [PATCH 105/116] + do fullcycle --- .gitlab-ci.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9bff62d20d..4990a60531 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -5,12 +5,15 @@ image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild -stages: # List of stages for jobs, and their order of execution +stages: - buildandtest -build-and-test-job: # This job runs in the build stage, which runs first. +build-and-test-job: stage: buildandtest script: + - cd compiler + - make fullcycle + - cd .. - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 FPMAKEOPT="-T 4" - FPC_SRC=$(pwd) - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 From e80560e59c8abbdd5ec21c445fce25b3627aad3a Mon Sep 17 00:00:00 2001 From: florian Date: Fri, 27 Aug 2021 22:31:11 +0200 Subject: [PATCH 106/116] * fix test for targets with FPC_COMP_IS_INT64 defined --- packages/fcl-json/tests/testcomps.pas | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/packages/fcl-json/tests/testcomps.pas b/packages/fcl-json/tests/testcomps.pas index 7398cb9014..de127c74ae 100644 --- a/packages/fcl-json/tests/testcomps.pas +++ b/packages/fcl-json/tests/testcomps.pas @@ -659,7 +659,11 @@ end; constructor TCompComponent.Create(AOwner: TComponent); begin inherited; +{$if defined(FPC_COMP_IS_INT64)} + F:=Round(4.56); +{$else defined(FPC_COMP_IS_INT64)} F:=4.56; +{$endif defined(FPC_COMP_IS_INT64)} end; { TCurrencyComponent } From e9b880c94770696d7db39f43d59762103a0a9b6e Mon Sep 17 00:00:00 2001 From: FPK Date: Sat, 28 Aug 2021 17:22:31 +0000 Subject: [PATCH 107/116] * factored out the fullcycle job as proposed by Marcus --- .gitlab-ci.yml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4990a60531..d79d02233e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -6,14 +6,18 @@ image: registry.gitlab.com/freepascal.org/fpc/source:buster_fpcbuild stages: + - compilercycle - buildandtest +compiler-fullcycle-job: + stage: compilercycle + script: + - cd compiler + - make fullcycle + build-and-test-job: stage: buildandtest script: - - cd compiler - - make fullcycle - - cd .. - make -j 4 all OS_TARGET=linux CPU_TARGET=x86_64 FPMAKEOPT="-T 4" - FPC_SRC=$(pwd) - FPC_COMPILER=$FPC_SRC/compiler/ppcx64 From efd0c250dfeaa0bbffb4d61e90e6d99dd2b94b0f Mon Sep 17 00:00:00 2001 From: Sven Barth Date: Sat, 28 Aug 2021 17:58:34 +0200 Subject: [PATCH 108/116] * fix for #39310 by fixing various small issues in tabstractrecordsymtable.has_single_field: - initialize the returned def to a safe default - correctly reset the found symbol for each loop - reset the result when descending into a record + added test --- compiler/symtable.pas | 10 ++++++++-- tests/webtbs/tw39310.pp | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 tests/webtbs/tw39310.pp diff --git a/compiler/symtable.pas b/compiler/symtable.pas index 8117af72f7..140412c765 100644 --- a/compiler/symtable.pas +++ b/compiler/symtable.pas @@ -1633,6 +1633,7 @@ implementation sym: tfieldvarsym; begin result:=false; + def:=generrordef; { If a record contains a union, it does not contain a "single non-composite field" in the context of certain ABIs requiring special treatment for such records } @@ -1642,8 +1643,8 @@ implementation { a record/object can contain other things than fields } currentsymlist:=symlist; { recurse in arrays and records } - sym:=nil; repeat + sym:=nil; { record has one field? } for i:=0 to currentsymlist.Count-1 do begin @@ -1674,7 +1675,12 @@ implementation end; { if the array element is again a record, continue descending } if currentdef.typ=recorddef then - currentsymlist:=trecorddef(currentdef).symtable.SymList + begin + { the record might be empty, so reset the result until we've + really found something } + result:=false; + currentsymlist:=trecorddef(currentdef).symtable.SymList + end else begin { otherwise we found the type of the single element } diff --git a/tests/webtbs/tw39310.pp b/tests/webtbs/tw39310.pp new file mode 100644 index 0000000000..eec8ea1d1a --- /dev/null +++ b/tests/webtbs/tw39310.pp @@ -0,0 +1,21 @@ +{ %NORUN } + +{$MODESWITCH ADVANCEDRECORDS} +Program tw39310; + +Type + Rec0 = record + end; + + Rec1 = record + r:Rec0; + Procedure Proc; + end; + +Procedure Rec1.Proc; + begin + end; + +Begin +End. + From d3615788a8e4c57f113f1d1cd6e76be97bf96664 Mon Sep 17 00:00:00 2001 From: florian Date: Sun, 29 Aug 2021 21:00:51 +0200 Subject: [PATCH 109/116] * generate a def. file only if really necessary --- compiler/options.pas | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/compiler/options.pas b/compiler/options.pas index a301518ab6..ba242a2227 100644 --- a/compiler/options.pas +++ b/compiler/options.pas @@ -1740,13 +1740,13 @@ begin end; 'D' : begin - include(init_settings.globalswitches,cs_link_deffile); j:=1; while j<=length(more) do begin case more[j] of 'd' : begin + include(init_settings.globalswitches,cs_link_deffile); description:=Copy(more,j+1,255); break; end; @@ -1762,6 +1762,7 @@ begin end; 'v' : begin + include(init_settings.globalswitches,cs_link_deffile); dllversion:=Copy(more,j+1,255); l:=pos('.',dllversion); dllminor:=0; @@ -1792,7 +1793,10 @@ begin break; end; 'w' : - usewindowapi:=true; + begin + include(init_settings.globalswitches,cs_link_deffile); + usewindowapi:=true; + end; '-' : begin exclude(init_settings.globalswitches,cs_link_deffile); From f134e3b0eec1866a21572feb012813fa14623b87 Mon Sep 17 00:00:00 2001 From: ccrause Date: Wed, 25 Aug 2021 20:46:48 +0200 Subject: [PATCH 110/116] Sorted help options. --- compiler/msg/errore.msg | 134 +++++++-------- compiler/msgidx.inc | 2 +- compiler/msgtxt.inc | 369 ++++++++++++++++++++-------------------- 3 files changed, 253 insertions(+), 252 deletions(-) diff --git a/compiler/msg/errore.msg b/compiler/msg/errore.msg index 5ac021ba1f..933a0df79c 100644 --- a/compiler/msg/errore.msg +++ b/compiler/msg/errore.msg @@ -3876,46 +3876,46 @@ F*0*_Only options valid for the default or selected platform are listed. **2Adefault_Use default assembler 3*2Aas_Assemble using GNU AS 3*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS +3*2Acoff_COFF (Go32v2) using internal writer +3*2Aelf_ELF (Linux) using internal writer 3*2Amacho_Mach-O (Darwin, Intel 32 bit) using internal writer -8*2Anasm_Assemble using Nasm -8*2Anasmobj_Assemble using Nasm +3*2Amasm_Obj file using Masm (Microsoft) 3*2Anasm_Assemble using Nasm 3*2Anasmcoff_COFF (Go32v2) file using Nasm -3*2Anasmelf_ELF32 (Linux) file using Nasm -3*2Anasmwin32_Win32 object file using Nasm -3*2Anasmwdosx_Win32/WDOSX object file using Nasm 3*2Anasmdarwin_macho32 object file using Nasm (experimental) -3*2Awasm_Obj file using Wasm (Watcom) +3*2Anasmelf_ELF32 (Linux) file using Nasm 3*2Anasmobj_Obj file using Nasm -3*2Amasm_Obj file using Masm (Microsoft) -3*2Atasm_Obj file using Tasm (Borland) -3*2Aelf_ELF (Linux) using internal writer -3*2Acoff_COFF (Go32v2) using internal writer +3*2Anasmwdosx_Win32/WDOSX object file using Nasm +3*2Anasmwin32_Win32 object file using Nasm 3*2Apecoff_PE-COFF (Win32) using internal writer +3*2Atasm_Obj file using Tasm (Borland) +3*2Awasm_Obj file using Wasm (Watcom) 3*2Ayasm_Assemble using Yasm (experimental) 4*2Aas_Assemble using GNU AS -4*2Agas_Assemble using GNU GAS 4*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS -4*2Amasm_Win64 object file using ml64 (Microsoft) -4*2Apecoff_PE-COFF (Win64) using internal writer 4*2Aelf_ELF (Linux-64bit) using internal writer -4*2Ayasm_Assemble using Yasm (experimental) +4*2Agas_Assemble using GNU GAS +4*2Amasm_Win64 object file using ml64 (Microsoft) 4*2Anasm_Assemble using Nasm (experimental) -4*2Anasmwin64_Assemble Win64 object file using Nasm (experimental) -4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental) 4*2Anasmdarwin_Assemble darwin macho64 object file using Nasm (experimental) +4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental) +4*2Anasmwin64_Assemble Win64 object file using Nasm (experimental) +4*2Apecoff_PE-COFF (Win64) using internal writer +4*2Ayasm_Assemble using Yasm (experimental) 6*2Aas_Unix o-file using GNU AS 6*2Agas_GNU Motorola assembler 6*2Amit_MIT Syntax (old GAS) 6*2Amot_Standard Motorola assembler 6*2Avasm_Use vasm to assemble +8*2Anasm_Assemble using Nasm +8*2Anasmobj_Assemble using Nasm A*2Aas_Assemble using GNU AS A*2Aas-darwin_Assemble using GNU AS for Darwin targets A*2Aclang_Assemble using clang A*2Aelf_Assemble using internal ELF writer a*2Aas_Assemble using GNU AS +a*2Aas-clang_Assemble using clang for other targets a*2Aclang_Assemble using clang for darwin/ios targets -a*2Aas-clang_Assemble using clang for other targets P*2Aas_Assemble using GNU AS S*2Aas_Assemble using GNU AS s*2Aas_Assemble using GNU AS @@ -3925,8 +3925,8 @@ W*2Allvm-mc_Assemble using llvm-mc W*2Awabt_Assemble using wasa x*2Aas_Assemble using GNU AS Z*2Asdcc-sdasz80_Assemble using SDCC-SDASZ80 -Z*2Az80asm_Assemble using z80asm Z*2Avasm_Assemble using Vasm +Z*2Az80asm_Assemble using z80asm # Used only internally by IDE **1b_Generate browser info **2bl_Generate local symbol info @@ -3955,9 +3955,9 @@ P*2CN_Generate nil-pointer checks (AIX-only) **2CO_Check for possible overflow of integer operations **2Cp_Select instruction set; see fpc -i or fpc -ic for possible values **2CP=_ packing settings -**3CPPACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, 4 and 8 **3CPPACKENUM=_ enum packing: 0, 1, 2 and 4 or DEFAULT or NORMAL **3CPPACKRECORD=_ record packing: 0 or DEFAULT or NORMAL, 1, 2, 4, 8, 16 and 32 +**3CPPACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, 4 and 8 **2Cr_Range checking **2CR_Verify object method call validity **2Cs_Set stack checking size to @@ -3987,8 +3987,8 @@ A*2CV_Set section threadvar model to **2CX_Create also smartlinked library **1d_Defines the symbol **1D_Generate a DEF file -**2DD_Set the date string returned by %DATE% to x, it is not checked for being a valid date string **2Dd_Set description to +**2DD_Set the date string returned by %DATE% to x, it is not checked for being a valid date string **2DT_Set the time string returned by %TIME% to x, it is not checked for being a valid time string **2Dv_Set DLL version to *O2Dw_PM application @@ -4016,19 +4016,19 @@ A*2CV_Set section threadvar model to **2FR_Set resource (.res) linker to **2Fu_Add to unit path **2FU_Set unit output path to , overrides -FE -**2FW_Store generated whole-program optimization feedback in **2Fw_Load previously stored whole-program optimization feedback from +**2FW_Store generated whole-program optimization feedback in *g1g_Generate debug information (default format for target) *g2gc_Generate checks for pointers (experimental, only available on some targets, might generate false positive) *g2gh_Use heaptrace unit (for memory leak/corruption debugging) *g2gl_Use line info unit (show more info with backtraces) *g2gm_Generate Microsoft CodeView debug information (experimental) *g2go_Set debug information options +*g3godwarfcpp_ Simulate C++ debug information in DWARF +*g3godwarfmethodclassprefix_ Prefix method names in DWARF with class name +*g3godwarfomflinnum_ Generate line number information in OMF LINNUM records in MS LINK format in addition to the DWARF debug information (Open Watcom Debugger/Linker compatibility) *g3godwarfsets_ Enable DWARF 'set' type debug information (breaks gdb < 6.5) *g3gostabsabsincludes_ Store absolute/full include file paths in Stabs -*g3godwarfmethodclassprefix_ Prefix method names in DWARF with class name -*g3godwarfcpp_ Simulate C++ debug information in DWARF -*g3godwarfomflinnum_ Generate line number information in OMF LINNUM records in MS LINK format in addition to the DWARF debug information (Open Watcom Debugger/Linker compatibility) *g2gp_Preserve case in stabs symbol names *g2gs_Generate Stabs debug information *g2gt_Trash local variables (to detect uninitialized uses; multiple 't' changes the trashing value) @@ -4038,36 +4038,36 @@ A*2CV_Set section threadvar model to *g2gw3_Generate DWARFv3 debug information *g2gw4_Generate DWARFv4 debug information (experimental) **1i_Information -**2iD_Return compiler date -**2iSO_Return compiler OS -**2iSP_Return compiler host processor -**2iTO_Return target OS -**2iTP_Return target processor -**2iV_Return short compiler version -**2iW_Return full compiler version **2ia_Return list of supported ABI targets **2ib_Return the used code generation backend type **2ic_Return list of supported CPU instruction sets +**2iD_Return compiler date **2if_Return list of supported FPU instruction sets **2ii_Return list of supported inline assembler modes **2im_Return list of supported modeswitches **2io_Return list of supported optimizations **2ir_Return list of recognized compiler and RTL features +**2iSO_Return compiler OS +**2iSP_Return compiler host processor **2it_Return list of supported targets +**2iTO_Return target OS +**2iTP_Return target processor **2iu_Return list of supported microcontroller types +**2iV_Return short compiler version **2iw_Return list of supported whole program optimizations +**2iW_Return full compiler version **1I_Add to include path **1k_Pass to the linker **1l_Write logo **1M_Set language mode to / enable modeswitch (see option -im) -**2Mfpc_Free Pascal dialect (default) -**2Mobjfpc_FPC mode with Object Pascal support **2Mdelphi_Delphi 7 compatibility mode -**2Mtp_TP/BP 7.0 compatibility mode -**2Mmacpas_Macintosh Pascal dialects compatibility mode -**2Miso_ISO 7185 mode -**2Mextendedpascal_ISO 10206 mode **2Mdelphiunicode_Delphi 2009 and later compatibility mode +**2Mextendedpascal_ISO 10206 mode +**2Mfpc_Free Pascal dialect (default) +**2Miso_ISO 7185 mode +**2Mmacpas_Macintosh Pascal dialects compatibility mode +**2Mobjfpc_FPC mode with Object Pascal support +**2Mtp_TP/BP 7.0 compatibility mode **2*_Each mode (as listed above) enables its default set of modeswitches. **2*_Other modeswitches are disabled and need to be enabled one by another. **1M-_Disable modeswitch (see option -im) @@ -4082,9 +4082,9 @@ A*2CV_Set section threadvar model to **2Oa=_Set alignment **2Oo[NO]_Enable or disable optimizations; see fpc -i or fpc -io for possible values **2Op_Set target cpu for optimizing; see fpc -i or fpc -ic for possible values -**2OW_Generate whole-program optimization feedback for optimization ; see fpc -i or fpc -iw for possible values -**2Ow_Perform whole-program optimization ; see fpc -i or fpc -iw for possible values **2Os_Optimize for size rather than speed +**2Ow_Perform whole-program optimization ; see fpc -i or fpc -iw for possible values +**2OW_Generate whole-program optimization feedback for optimization ; see fpc -i or fpc -iw for possible values **1pg_Generate profile code for gprof (defines FPC_PROFILE) F*1P_Target CPU / compiler related options: F*2PB_Show default compiler binary @@ -4099,25 +4099,30 @@ F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipsel,powerpc, 8*2Ratt_Read AT&T style assembler 8*2Rintel_Read Intel style assembler 6*2RMOT_Read Motorola style assembler +**1s_Do not call assembler and linker +**2sh_Generate script to link on host, automatically switches to external assembler writer +**2sr_Skip register allocation phase (use with -alr), automatically switches to external assembler writer +**2st_Generate script to assemble and link on target, automatically switches to external assembler writer +**2sT_Generate script only to link on target **1S_Syntax options: **2S2_Same as -Mobjfpc -**2Sc_Support operators like C (*=,+=,/= and -=) **2Sa_Turn on assertions +**2Sc_Support operators like C (*=,+=,/= and -=) **2Sd_Same as -Mdelphi **2Se_Error options. is a combination of the following: **3*_ : Compiler halts after the errors (default is 1) -**3*_w : Compiler also halts after warnings -**3*_n : Compiler also halts after notes **3*_h : Compiler also halts after hints +**3*_n : Compiler also halts after notes +**3*_w : Compiler also halts after warnings **2Sf_Enable certain features in compiler and RTL; see fpc -i or fpc -ir for possible values) **2Sg_Enable LABEL and GOTO (default in -Mtp and -Mdelphi) **2Sh_Use reference counted strings (ansistring by default) instead of shortstrings **2Si_Turn on inlining of procedures/functions declared as "inline" -**2Sj_Allows typed constants to be writeable (default in all modes) -**2Sk_Load fpcylix unit **2SI_Set interface style to **3SIcom_COM compatible interface (default) **3SIcorba_CORBA compatible interface +**2Sj_Allows typed constants to be writeable (default in all modes) +**2Sk_Load fpcylix unit **2Sm_Support macros like C (global) **2So_Same as -Mtp **2Sr_Transparent file names in ISO mode @@ -4125,11 +4130,6 @@ F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipsel,powerpc, **2Sv_Support vector processing (use CPU vector extensions if available) **2Sx_Enable exception keywords (default in Delphi/ObjFPC modes) **2Sy_@ returns a typed pointer, same as $T+ -**1s_Do not call assembler and linker -**2sh_Generate script to link on host, automatically switches to external assembler writer -**2sT_Generate script only to link on target -**2st_Generate script to assemble and link on target, automatically switches to external assembler writer -**2sr_Skip register allocation phase (use with -alr), automatically switches to external assembler writer **1T_Target operating system: # i386 targets 3*2Tandroid_Android @@ -4149,8 +4149,8 @@ F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipsel,powerpc, 3*2Tnetwlibc_Novell Netware Module (libc) 3*2Topenbsd_OpenBSD 3*2Tos2_OS/2 / eComStation -3*2Tsymbian_Symbian OS 3*2Tsolaris_Solaris +3*2Tsymbian_Symbian OS 3*2Twatcom_Watcom compatible DOS extender 3*2Twdosx_WDOSX DOS extender 3*2Twin32_Windows 32 Bit @@ -4228,11 +4228,11 @@ p*2Tdarwin_Darwin/Mac OS X p*2Tembedded_Embedded p*2Tlinux_Linux # riscv32 targets -R*2Tlinux_Linux R*2Tembedded_Embedded +R*2Tlinux_Linux # riscv64 targets -r*2Tlinux_Linux r*2Tembedded_Embedded +r*2Tlinux_Linux # sparc targets S*2Tlinux_Linux S*2Tsolaris_Solaris @@ -4247,8 +4247,8 @@ x*2Tfreertos_FreeRTOS x*2Tlinux_Linux # z80 targets Z*2Tembedded_Embedded -Z*2Tzxspectrum_ZX Spectrum Z*2Tmsxdos_MSX-DOS +Z*2Tzxspectrum_ZX Spectrum # wasm32 targets W*2Tembedded_Embedded W*2Twasi_The WebAssembly System Interface (WASI) @@ -4259,18 +4259,18 @@ W*2Twasi_The WebAssembly System Interface (WASI) **2Ur_Generate release unit files (never automatically recompiled) **2Us_Compile a system unit **1v_Be verbose. is a combination of the following letters: -**2*_e : Show errors (default) 0 : Show nothing (except errors) -**2*_w : Show warnings u : Show unit info -**2*_n : Show notes t : Show tried/used files -**2*_h : Show hints c : Show conditionals -**2*_i : Show general info d : Show debug info -**2*_l : Show linenumbers r : Rhide/GCC compatibility mode -**2*_s : Show time stamps q : Show message numbers -**2*_a : Show everything x : Show info about invoked tools -**2*_b : Write file names messages p : Write tree.log with parse tree -**2*_ with full path v : Write fpcdebug.txt with -**2*_z : Write output to stderr lots of debugging info +**2*_0 : Show nothing (except errors) p : Write tree.log with parse tree +**2*_a : Show everything q : Show message numbers +**2*_b : Write file names messages r : Rhide/GCC compatibility mode +**2*_ with full path s : Show time stamps +**2*_c : Show conditionals t : Show tried/used files +**2*_d : Show debug info u : Show unit info +**2*_e : Show errors (default) v : Write fpcdebug.txt with +**2*_h : Show hints lots of debugging info +**2*_i : Show general info w : Show warnings +**2*_l : Show linenumbers x : Show info about invoked tools **2*_m, : Do not show messages numbered and +**2*_n : Show notes z : Write output to stderr F*1V_Append '-' to the used compiler binary name (e.g. for version) **1W_Target-specific options (targets) 3*2WA_Specify native type application (Windows) @@ -4344,8 +4344,8 @@ A*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (Darwin) 4*2WR_Generate relocation code (Windows) A*2WR_Generate relocation code (Windows) 8*2Wt_Set the target executable format -8*3Wtexe_Create a DOS .EXE file (default) 8*3Wtcom_Create a DOS .COM file (requires tiny memory model) +8*3Wtexe_Create a DOS .EXE file (default) P*2WT_Specify MPW tool type application (Classic Mac OS) 6*2WQ_Set executable metadata format (Sinclair QL) 6*3WQqhdr_Set metadata to QDOS File Header style (default) @@ -4356,15 +4356,15 @@ P*2WT_Specify MPW tool type application (Classic Mac OS) **2Xa_Generate code which allows to use more than 2 GB static data on 64 Bit targets (Linux) **2Xc_Pass --shared/-dynamic to the linker (BeOS, Darwin, FreeBSD, Linux) **2Xd_Do not search default library path (sometimes required for cross-compiling when not using -XR) +**2XD_Try to link units dynamically (defines FPC_LINK_DYNAMIC) **2Xe_Use external linker **2Xf_Substitute pthread library name for linking (BSD) **2Xg_Create debuginfo in a separate file and add a debuglink section to executable -**2XD_Try to link units dynamically (defines FPC_LINK_DYNAMIC) **2Xi_Use internal linker L*2XlS_LLVM utilties suffix (e.g. -7 in case clang is called clang-7) **2XLA_Define library substitutions for linking -**2XLO_Define order of library linking **2XLD_Exclude default order of standard libraries +**2XLO_Define order of library linking **2Xm_Generate link map **2XM_Set the name of the 'main' program routine (default is 'main') **2Xn_Use target system native linker instead of GNU ld (Solaris, AIX) diff --git a/compiler/msgidx.inc b/compiler/msgidx.inc index 655f194e0f..bd25256044 100644 --- a/compiler/msgidx.inc +++ b/compiler/msgidx.inc @@ -1141,7 +1141,7 @@ const option_info=11024; option_help_pages=11025; - MsgTxtSize = 88167; + MsgTxtSize = 88168; MsgIdxMax : array[1..20] of longint=( 28,107,361,131,99,63,147,37,223,68, diff --git a/compiler/msgtxt.inc b/compiler/msgtxt.inc index e4446c9432..1390914a0a 100644 --- a/compiler/msgtxt.inc +++ b/compiler/msgtxt.inc @@ -1475,144 +1475,144 @@ const msgtxt : array[0..000367,1..240] of char=( '**2Adefau','lt_Use default assembler'#010+ '3*2Aas_Assemble using GNU AS'#010+ '3*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ - '3*2Amacho_Mach-O (Darwin, Intel 32 bit) using internal writer'#010+ - '8*2Anasm_Assemble using Nasm'#010+ - '8*2Anasmobj_Assemble using Nasm'#010+ - '3*2Anasm_Ass','emble using Nasm'#010+ - '3*2Anasmcoff_COFF (Go32v2) file using Nasm'#010+ - '3*2Anasmelf_ELF32 (Linux) file using Nasm'#010+ - '3*2Anasmwin32_Win32 object file using Nasm'#010+ - '3*2Anasmwdosx_Win32/WDOSX object file using Nasm'#010+ - '3*2Anasmdarwin_macho32 object file using Nasm ','(experimental)'#010+ - '3*2Awasm_Obj file using Wasm (Watcom)'#010+ - '3*2Anasmobj_Obj file using Nasm'#010+ - '3*2Amasm_Obj file using Masm (Microsoft)'#010+ - '3*2Atasm_Obj file using Tasm (Borland)'#010+ + '3*2Acoff_COFF (Go32v2) using internal writer'#010+ '3*2Aelf_ELF (Linux) using internal writer'#010+ - '3*2Acoff_COFF (Go32v2) using inte','rnal writer'#010+ + '3*2Amacho_Mach-O (Darwin, Intel 32 bit) using in','ternal writer'#010+ + '3*2Amasm_Obj file using Masm (Microsoft)'#010+ + '3*2Anasm_Assemble using Nasm'#010+ + '3*2Anasmcoff_COFF (Go32v2) file using Nasm'#010+ + '3*2Anasmdarwin_macho32 object file using Nasm (experimental)'#010+ + '3*2Anasmelf_ELF32 (Linux) file using Nasm'#010+ + '3*2Anasmob','j_Obj file using Nasm'#010+ + '3*2Anasmwdosx_Win32/WDOSX object file using Nasm'#010+ + '3*2Anasmwin32_Win32 object file using Nasm'#010+ '3*2Apecoff_PE-COFF (Win32) using internal writer'#010+ + '3*2Atasm_Obj file using Tasm (Borland)'#010+ + '3*2Awasm_Obj file using Wasm (Watcom)'#010, '3*2Ayasm_Assemble using Yasm (experimental)'#010+ '4*2Aas_Assemble using GNU AS'#010+ - '4*2Agas_Assemble using GNU GAS'#010+ '4*2Aas-darwin_Assemble Darwin Mach-O using GNU GAS'#010+ - '4*2Amasm_Win64 object fi','le using ml64 (Microsoft)'#010+ - '4*2Apecoff_PE-COFF (Win64) using internal writer'#010+ '4*2Aelf_ELF (Linux-64bit) using internal writer'#010+ - '4*2Ayasm_Assemble using Yasm (experimental)'#010+ + '4*2Agas_Assemble using GNU GAS'#010+ + '4*2Amasm_Win64 object file using ml64',' (Microsoft)'#010+ '4*2Anasm_Assemble using Nasm (experimental)'#010+ - '4*2Anasmwin64_Assemble Win64 ','object file using Nasm (experimental)'#010+ - '4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental)'+ - #010+ '4*2Anasmdarwin_Assemble darwin macho64 object file using Nasm (experim'+ 'ental)'#010+ + '4*2Anasmelf_Assemble Linux-64bit object file using Nasm (experimental)'+ + #010+ + '4*2Anasmwin64_Assemble Win64 object',' file using Nasm (experimental)'#010+ + '4*2Apecoff_PE-COFF (Win64) using internal writer'#010+ + '4*2Ayasm_Assemble using Yasm (experimental)'#010+ '6*2Aas_Unix o-file using GNU AS'#010+ - '6*2Agas_GNU Motorola a','ssembler'#010+ + '6*2Agas_GNU Motorola assembler'#010+ '6*2Amit_MIT Syntax (old GAS)'#010+ - '6*2Amot_Standard Motorola assembler'#010+ + '6*2Amot_Standard Motoro','la assembler'#010+ '6*2Avasm_Use vasm to assemble'#010+ + '8*2Anasm_Assemble using Nasm'#010+ + '8*2Anasmobj_Assemble using Nasm'#010+ 'A*2Aas_Assemble using GNU AS'#010+ 'A*2Aas-darwin_Assemble using GNU AS for Darwin targets'#010+ 'A*2Aclang_Assemble using clang'#010+ 'A*2Aelf_Assemble usin','g internal ELF writer'#010+ 'a*2Aas_Assemble using GNU AS'#010+ + 'a*2Aas-clang_Assemble using clang for other targets'#010+ 'a*2Aclang_Assemble using clang for darwin/ios targets'#010+ - 'a*2Aas-clang_Assemble using clang for other targets '#010+ 'P*2Aas_Assemble using GNU AS'#010+ 'S*2Aas_Assemble using GNU AS'#010+ - 's*2Aas_Assemble using GN','U AS'#010+ + 's*2Aas_Assemble using GNU',' AS'#010+ 'v*2Aas_Assemble using GNU AS'#010+ 'W*2Abinaryen_Assemble using GNU AS for wasm32 (wasm-as)'#010+ 'W*2Allvm-mc_Assemble using llvm-mc'#010+ 'W*2Awabt_Assemble using wasa'#010+ 'x*2Aas_Assemble using GNU AS'#010+ 'Z*2Asdcc-sdasz80_Assemble using SDCC-SDASZ80'#010+ - 'Z*2Az80asm_A','ssemble using z80asm'#010+ - 'Z*2Avasm_Assemble using Vasm'#010+ + 'Z*2Avasm_Asse','mble using Vasm'#010+ + 'Z*2Az80asm_Assemble using z80asm'#010+ '**1b_Generate browser info'#010+ '**2bl_Generate local symbol info'#010+ '**1B_Build all modules'#010+ '**1C_Code generation options:'#010+ '**2C3_Turn on ieee error checking for constants'#010+ - '**2Ca_Select ABI; see f','pc -i or fpc -ia for possible values'#010+ + '**2Ca_Select ABI; see fp','c -i or fpc -ia for possible values'#010+ '**2Cb_Generate code for a big-endian variant of the target architectur'+ 'e'#010+ '**2Cc_Set default calling convention to '#010+ '**2CD_Create also dynamic library (not supported)'#010+ - '**2Ce_Compilation with emulated fl','oating point opcodes'#010+ + '**2Ce_Compilation with emulated flo','ating point opcodes'#010+ '**2CE_Generate FPU code which can raise exceptions'#010+ '**2Cf_Select fpu instruction set to use; see fpc -i or fpc -if for '+ 'possible values'#010+ '**2CF_Minimal floating point constant precision (default, 32, 64)'#010+ - '**2Cg_Generat','e PIC code'#010+ + '**2Cg_Generate',' PIC code'#010+ '**2Ch[,m]_ bytes min heap size (between 1023 and 67107840) and o'+ 'ptionally [m] max heap size'#010+ '**2Ci_IO-checking'#010+ 'A*2CI_Select instruction set on ARM: ARM or THUMB'#010+ 'L*2Cl_LLVM code generation options'#010+ - 'L*3Clflto_Enable Link-','time optimisation (needed both when compiling '+ + 'L*3Clflto_Enable Link-t','ime optimisation (needed both when compiling '+ 'units and programs/libraries)'#010+ 'L*3Clfltonosystem_Disable LTO for the system unit (needed with at leas'+ 't Xcode 10.2 and earlier due to linker bugs)'#010+ - 'L*3Clv_LLVM target version: Xcode-10.1, 7.0, 8','.0, .., 10.0'#010+ + 'L*3Clv_LLVM target version: Xcode-10.1, 7.0, 8.','0, .., 10.0'#010+ '**2Cn_Omit linking stage'#010+ 'P*2CN_Generate nil-pointer checks (AIX-only)'#010+ '**2Co_Check overflow of integer operations'#010+ '**2CO_Check for possible overflow of integer operations'#010+ - '**2Cp_Select instruction set; see fpc -i or fpc -ic for',' possible '+ + '**2Cp_Select instruction set; see fpc -i or fpc -ic for ','possible '+ 'values'#010+ '**2CP=_ packing settings'#010+ - '**3CPPACKSET=_ set allocation: 0, 1 or DEFAULT or NORMAL, 2, 4 '+ - 'and 8'#010+ '**3CPPACKENUM=_ enum packing: 0, 1, 2 and 4 or DEFAULT or NORMA'+ 'L'#010+ - '**3CPPACKRECORD=_ record packing: 0 o','r DEFAULT or NORMAL, 1, '+ - '2, 4, 8, 16 and 32'#010+ + '**3CPPACKRECORD=_ record packing: 0 or DEFAULT or NORMAL, 1, 2,'+ + ' 4, 8, 16 and 32'#010+ + '**3CPPACKSET=_ set allocati','on: 0, 1 or DEFAULT or NORMAL, 2, '+ + '4 and 8'#010+ '**2Cr_Range checking'#010+ '**2CR_Verify object method call validity'#010+ '**2Cs_Set stack checking size to '#010+ '**2Ct_Stack checking (for testing only, see manual)'#010+ - '8*2CT_Target-specific code generation op','tions'#010+ + '8*2CT_Target-specific code generation opt','ions'#010+ '3*2CT_Target-specific code generation options'#010+ '4*2CT_Target-specific code generation options'#010+ 'p*2CT_Target-specific code generation options'#010+ 'P*2CT_Target-specific code generation options'#010+ - 'J*2CT_Target-specific code generati','on options'#010+ + 'J*2CT_Target-specific code generatio','n options'#010+ 'A*2CT_Target-specific code generation options'#010+ 'p*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ ' (AIX)'#010+ 'P*3CTsmalltoc_ Generate smaller TOCs at the expense of execution speed'+ ' (AIX)'#010+ - 'J*3CTautogetterprefix=X_ ','Automatically create getters for propertie'+ + 'J*3CTautogetterprefix=X_ A','utomatically create getters for propertie'+ 's with prefix X (empty string disables)'#010+ 'J*3CTautosetterprefix=X_ Automatically create setters for properties '+ 'with prefix X (empty string disables)'#010+ - '8*3CTcld_ Emit a CLD instruction b','efore using the x8'+ + '8*3CTcld_ Emit a CLD instruction be','fore using the x8'+ '6 string instructions'#010+ '3*3CTcld_ Emit a CLD instruction before using the x86 '+ 'string instructions'#010+ '4*3CTcld_ Emit a CLD instruction before using the x86 '+ 'string instructions'#010+ - '8*3CTfarprocspushodd','bp_ Increment BP before pushing it in the '+ + '8*3CTfarprocspushoddb','p_ Increment BP before pushing it in the '+ 'prologue of far functions'#010+ 'J*3CTcompactintarrayinit_ Generate smaller (but potentially slower) co'+ 'de for initializing integer array constants'#010+ - 'J*3CTenumfieldinit_ Initialize enumeration fie','lds in construct'+ + 'J*3CTenumfieldinit_ Initialize enumeration fiel','ds in construct'+ 'ors to enumtype(0), after calling inherited constructors'#010+ 'J*3CTinitlocals_ Initialize local variables that trigger a JV'+ 'M bytecode verification error if used uninitialized (slows down code)'#010+ - 'J*3CTlowercaseprocstart_ L','owercase the first character of procedure'+ + 'J*3CTlowercaseprocstart_ Lo','wercase the first character of procedure'+ '/function/method names'#010+ 'A*3CTthumbinterworking_ Generate Thumb interworking-safe code if possi'+ 'ble'#010+ 'J*2Cv_Var/out parameter copy-out checking'#010+ 'A*2CV_Set section threadvar model to '#010+ - '**2CX_Create als','o smartlinked library'#010+ + '**2CX_Create also',' smartlinked library'#010+ '**1d_Defines the symbol '#010+ '**1D_Generate a DEF file'#010+ + '**2Dd_Set description to '#010+ '**2DD_Set the date string returned by %DATE% to x, it is not checke'+ 'd for being a valid date string'#010+ - '**2Dd_Set description to '#010+ - '**2DT_Set the time string',' returned by %TIME% to x, it is not chec'+ + '**2DT_Set the time string ','returned by %TIME% to x, it is not chec'+ 'ked for being a valid time string'#010+ '**2Dv_Set DLL version to '#010+ '*O2Dw_PM application'#010+ @@ -1620,166 +1620,166 @@ const msgtxt : array[0..000367,1..240] of char=( '**1E_Same as -Cn'#010+ '**1fPIC_Same as -Cg'#010+ '**1F_Set file names and paths:'#010+ - '**2Fa[,y',']_(for a program) load units and [y] before uses is p'+ + '**2Fa[,y]','_(for a program) load units and [y] before uses is p'+ 'arsed'#010+ '**2Fc_Set input codepage to '#010+ '**2FC_Set RC compiler binary name to '#010+ '**2Fd_Disable the compiler'#039's internal directory cache'#010+ - '**2FD_Set the directory where to search f','or compiler utilities'#010+ + '**2FD_Set the directory where to search fo','r compiler utilities'#010+ '**2Fe_Redirect error output to '#010+ '**2FE_Set exe/unit output path to '#010+ '**2Ff_Add to framework path (Darwin only), or set IDF path to <'+ 'x> (Xtensa-FreeRTOS)'#010+ - '**2FF_Use fpcres as RC to RES compiler instead o','f windres or gorc'#010+ + '**2FF_Use fpcres as RC to RES compiler instead of',' windres or gorc'#010+ '**2Fi_Add to include path'#010+ '**2Fl_Add to library path'#010+ '**2FL_Use as dynamic linker'#010+ '**2Fm_Load unicode conversion table from .txt in the compiler di'+ 'r'#010+ - '**2FM_Set the directory where to search for un','icode binary files'#010+ + '**2FM_Set the directory where to search for uni','code binary files'#010+ '**2FN_Add to list of default unit scopes (namespaces)'#010+ '**2Fo_Add to object path'#010+ '**2Fr_Load error message file '#010+ '**2FR_Set resource (.res) linker to '#010+ '**2Fu_Add to unit path'#010+ - '**2FU_Set unit ','output path to , overrides -FE'#010+ - '**2FW_Store generated whole-program optimization feedback in '#010+ + '**2FU_Set unit o','utput path to , overrides -FE'#010+ '**2Fw_Load previously stored whole-program optimization feedback fr'+ 'om '#010+ + '**2FW_Store generated whole-program optimization feedback in '#010+ '*g1g_Generate debug information (default format for target)'#010+ - '*','g2gc_Generate checks for pointers (experimental, only available on '+ + '*g','2gc_Generate checks for pointers (experimental, only available on '+ 'some targets, might generate false positive)'#010+ '*g2gh_Use heaptrace unit (for memory leak/corruption debugging)'#010+ '*g2gl_Use line info unit (show more info with backtraces)'#010+ - '*g2gm_','Generate Microsoft CodeView debug information (experimental)'#010+ + '*g2gm_G','enerate Microsoft CodeView debug information (experimental)'#010+ '*g2go_Set debug information options'#010+ - '*g3godwarfsets_ Enable DWARF '#039'set'#039' type debug information (bre'+ - 'aks gdb < 6.5)'#010+ - '*g3gostabsabsincludes_ Store absolute/full include file paths i','n Sta'+ - 'bs'#010+ + '*g3godwarfcpp_ Simulate C++ debug information in DWARF'#010+ '*g3godwarfmethodclassprefix_ Prefix method names in DWARF with class n'+ 'ame'#010+ - '*g3godwarfcpp_ Simulate C++ debug information in DWARF'#010+ - '*g3godwarfomflinnum_ Generate line number information in OMF LINNUM re'+ - 'cords in MS LINK format in additi','on to the DWARF debug information ('+ + '*g3godwarfom','flinnum_ Generate line number information in OMF LINNUM '+ + 'records in MS LINK format in addition to the DWARF debug information ('+ 'Open Watcom Debugger/Linker compatibility)'#010+ + '*g3godwarfsets_ Enable DWARF '#039'set'#039' type debug information (bre'+ + 'aks gdb <',' 6.5)'#010+ + '*g3gostabsabsincludes_ Store absolute/full include file paths in Stabs'+ + #010+ '*g2gp_Preserve case in stabs symbol names'#010+ '*g2gs_Generate Stabs debug information'#010+ '*g2gt_Trash local variables (to detect uninitialized uses; multiple '#039+ - 't'#039' changes t','he trashing value)'#010+ + 't'#039' changes th','e trashing value)'#010+ '*g2gv_Generates programs traceable with Valgrind'#010+ '*g2gw_Generate DWARFv2 debug information (same as -gw2)'#010+ '*g2gw2_Generate DWARFv2 debug information'#010+ '*g2gw3_Generate DWARFv3 debug information'#010+ - '*g2gw4_Generate DWARFv4 debug in','formation (experimental)'#010+ + '*g2gw4_Generate DWARFv4 debug inf','ormation (experimental)'#010+ '**1i_Information'#010+ - '**2iD_Return compiler date'#010+ - '**2iSO_Return compiler OS'#010+ - '**2iSP_Return compiler host processor'#010+ - '**2iTO_Return target OS'#010+ - '**2iTP_Return target processor'#010+ - '**2iV_Return short compiler version'#010+ - '**2iW_Return ful','l compiler version'#010+ '**2ia_Return list of supported ABI targets'#010+ '**2ib_Return the used code generation backend type'#010+ '**2ic_Return list of supported CPU instruction sets'#010+ - '**2if_Return list of supported FPU instruction sets'#010+ - '**2ii_Return list of su','pported inline assembler modes'#010+ + '**2iD_Return compiler date'#010+ + '**2if_Return list of suppo','rted FPU instruction sets'#010+ + '**2ii_Return list of supported inline assembler modes'#010+ '**2im_Return list of supported modeswitches'#010+ '**2io_Return list of supported optimizations'#010+ '**2ir_Return list of recognized compiler and RTL features'#010+ + '**2iSO_Return',' compiler OS'#010+ + '**2iSP_Return compiler host processor'#010+ '**2it_Return list of supported targets'#010+ - '**2iu_Return list of su','pported microcontroller types'#010+ - '**2iw_Return list of supported whole program optimizations'#010+ + '**2iTO_Return target OS'#010+ + '**2iTP_Return target processor'#010+ + '**2iu_Return list of supported microcontroller types'#010+ + '**2iV_Return short compiler version'#010+ + '**2iw_','Return list of supported whole program optimizations'#010+ + '**2iW_Return full compiler version'#010+ '**1I_Add to include path'#010+ '**1k_Pass to the linker'#010+ '**1l_Write logo'#010+ '**1M_Set language mode to / enable modeswitch (see option -'+ - 'im',')'#010+ - '**2Mfpc_Free Pascal dialect (default)'#010+ - '**2Mobjfpc_FPC mode with Object Pascal support'#010+ + 'im)',#010+ '**2Mdelphi_Delphi 7 compatibility mode'#010+ - '**2Mtp_TP/BP 7.0 compatibility mode'#010+ - '**2Mmacpas_Macintosh Pascal dialects compatibility mode'#010+ - '**2Miso_ISO 7185 mode'#010, - '**2Mextendedpascal_ISO 10206 mode'#010+ '**2Mdelphiunicode_Delphi 2009 and later compatibility mode'#010+ + '**2Mextendedpascal_ISO 10206 mode'#010+ + '**2Mfpc_Free Pascal dialect (default)'#010+ + '**2Miso_ISO 7185 mode'#010+ + '**2Mmacpas_Macintosh Pascal dialects compatibil','ity mode'#010+ + '**2Mobjfpc_FPC mode with Object Pascal support'#010+ + '**2Mtp_TP/BP 7.0 compatibility mode'#010+ '**2*_Each mode (as listed above) enables its default set of modeswitch'+ 'es.'#010+ '**2*_Other modeswitches are disabled and need to be enabled one by ano'+ - 'the','r.'#010+ + 'ther','.'#010+ '**1M-_Disable modeswitch (see option -im)'#010+ '**1n_Do not read the default config files'#010+ '**1o_Change the name of the executable produced to '#010+ '**1O_Optimizations:'#010+ '**2O-_Disable optimizations'#010+ - '**2O1_Level 1 optimizations (quick an','d debugger friendly)'#010+ + '**2O1_Level 1 optimizations (quick and',' debugger friendly)'#010+ '**2O2_Level 2 optimizations (-O1 + quick optimizations)'#010+ '**2O3_Level 3 optimizations (-O2 + slow optimizations)'#010+ '**2O4_Level 4 optimizations (-O3 + optimizations which might have unex'+ 'pected side effects)'#010+ - '**2Oa=_Set ','alignment'#010+ + '**2Oa=_Set a','lignment'#010+ '**2Oo[NO]_Enable or disable optimizations; see fpc -i or fpc -io fo'+ 'r possible values'#010+ '**2Op_Set target cpu for optimizing; see fpc -i or fpc -ic for poss'+ 'ible values'#010+ - '**2OW_Generate whole-program optimization feedback for op','timizati'+ - 'on ; see fpc -i or fpc -iw for possible values'#010+ - '**2Ow_Perform whole-program optimization ; see fpc -i or fpc -iw'+ - ' for possible values'#010+ '**2Os_Optimize for size rather than speed'#010+ - '**1pg_Generate profile code for gprof (defines FP','C_PROFILE)'#010+ + '**2Ow_Perform wh','ole-program optimization ; see fpc -i or fpc -'+ + 'iw for possible values'#010+ + '**2OW_Generate whole-program optimization feedback for optimization'+ + ' ; see fpc -i or fpc -iw for possible values'#010+ + '**1pg_Generate profile code for gprof (defines FPC','_PROFILE)'#010+ 'F*1P_Target CPU / compiler related options:'#010+ 'F*2PB_Show default compiler binary'#010+ 'F*2PP_Show default target cpu'#010+ 'F*2P_Set target CPU (aarch64,arm,avr,i386,i8086,jvm,m68k,mips,mipse'+ 'l,powerpc,powerpc64,sparc,x86_64)'#010+ - '**1R_Assem','bler reading style:'#010+ + '**1R_Assemb','ler reading style:'#010+ '**2Rdefault_Use default assembler for target'#010+ '3*2Ratt_Read AT&T style assembler'#010+ '3*2Rintel_Read Intel style assembler'#010+ '4*2Ratt_Read AT&T style assembler'#010+ '4*2Rintel_Read Intel style assembler'#010+ - '8*2Ratt_Read AT&T style assembler',#010+ + '8*2Ratt_Read AT&T style assembler'#010, '8*2Rintel_Read Intel style assembler'#010+ '6*2RMOT_Read Motorola style assembler'#010+ - '**1S_Syntax options:'#010+ - '**2S2_Same as -Mobjfpc'#010+ - '**2Sc_Support operators like C (*=,+=,/= and -=)'#010+ - '**2Sa_Turn on assertions'#010+ - '**2Sd_Same as -Mdelphi'#010+ - '**2Se_Error optio','ns. is a combination of the following:'#010+ - '**3*_ : Compiler halts after the errors (default is 1)'#010+ - '**3*_w : Compiler also halts after warnings'#010+ - '**3*_n : Compiler also halts after notes'#010+ - '**3*_h : Compiler also halts after hints'#010+ - '**2Sf_Ena','ble certain features in compiler and RTL; see fpc -i or fpc'+ - ' -ir for possible values)'#010+ - '**2Sg_Enable LABEL and GOTO (default in -Mtp and -Mdelphi)'#010+ - '**2Sh_Use reference counted strings (ansistring by default) instead of'+ - ' shortstrings'#010+ - '**2Si_Turn o','n inlining of procedures/functions declared as "inline"'#010+ - '**2Sj_Allows typed constants to be writeable (default in all modes)'#010+ - '**2Sk_Load fpcylix unit'#010+ - '**2SI_Set interface style to '#010+ - '**3SIcom_COM compatible interface (default)'#010+ - '**3SIcorba_C','ORBA compatible interface'#010+ - '**2Sm_Support macros like C (global)'#010+ - '**2So_Same as -Mtp'#010+ - '**2Sr_Transparent file names in ISO mode'#010+ - '**2Ss_Constructor name must be init (destructor must be done)'#010+ - '**2Sv_Support vector processing (use CPU vector extensi','ons if availa'+ - 'ble)'#010+ - '**2Sx_Enable exception keywords (default in Delphi/ObjFPC modes)'#010+ - '**2Sy_@ returns a typed pointer, same as $T+'#010+ '**1s_Do not call assembler and linker'#010+ - '**2sh_Generate script to link on host, automatically switches to ','ext'+ - 'ernal assembler writer'#010+ - '**2sT_Generate script only to link on target'#010+ + '**2sh_Generate script to link on host, automatically switches to exter'+ + 'nal assembler writer'#010+ + '**2sr_Skip register allocation phase',' (use with -alr), automatically '+ + 'switches to external assembler writer'#010+ '**2st_Generate script to assemble and link on target, automatically sw'+ 'itches to external assembler writer'#010+ - '**2sr_Skip register allocation phase (use with -alr), automatic','ally '+ - 'switches to external assembler writer'#010+ + '**2sT_Generate script only to link on target'#010+ + '**1S_Syntax opti','ons:'#010+ + '**2S2_Same as -Mobjfpc'#010+ + '**2Sa_Turn on assertions'#010+ + '**2Sc_Support operators like C (*=,+=,/= and -=)'#010+ + '**2Sd_Same as -Mdelphi'#010+ + '**2Se_Error options. is a combination of the following:'#010+ + '**3*_ : Compiler halts after the errors (defa','ult is 1)'#010+ + '**3*_h : Compiler also halts after hints'#010+ + '**3*_n : Compiler also halts after notes'#010+ + '**3*_w : Compiler also halts after warnings'#010+ + '**2Sf_Enable certain features in compiler and RTL; see fpc -i or fpc -'+ + 'ir for possible values)'#010+ + '**2Sg_Enab','le LABEL and GOTO (default in -Mtp and -Mdelphi)'#010+ + '**2Sh_Use reference counted strings (ansistring by default) instead of'+ + ' shortstrings'#010+ + '**2Si_Turn on inlining of procedures/functions declared as "inline"'#010+ + '**2SI_Set interface style to '#010+ + '**3','SIcom_COM compatible interface (default)'#010+ + '**3SIcorba_CORBA compatible interface'#010+ + '**2Sj_Allows typed constants to be writeable (default in all modes)'#010+ + '**2Sk_Load fpcylix unit'#010+ + '**2Sm_Support macros like C (global)'#010+ + '**2So_Same as -Mtp'#010+ + '**2Sr_Transpa','rent file names in ISO mode'#010+ + '**2Ss_Constructor name must be init (destructor must be done)'#010+ + '**2Sv_Support vector processing (use CPU vector extensions if availabl'+ + 'e)'#010+ + '**2Sx_Enable exception keywords (default in Delphi/ObjFPC modes)'#010+ + '**2Sy_@ returns a typed pointer, same as $T+'#010+ '**1T_Target operating system:'#010+ '3*2Tandroid_Android'#010+ '3*2Taros_AROS'#010+ @@ -1787,7 +1787,7 @@ const msgtxt : array[0..000367,1..240] of char=( '3*2Tdarwin_Darwin/Mac OS X'#010+ '3*2Tembedded_Embedded'#010+ '3*2Temx_OS/2 via EMX (including EMX/RSX extender)'#010+ - '3*2Tfreebsd_FreeB','SD'#010+ + '3*2Tfreebsd_FreeBS','D'#010+ '3*2Tgo32v2_Version 2 of DJ Delorie DOS extender'#010+ '3*2Thaiku_Haiku'#010+ '3*2Tiphonesim_iPhoneSimulator from iOS SDK 3.2+ (older versions: -Tdar'+ @@ -1795,15 +1795,15 @@ const msgtxt : array[0..000367,1..240] of char=( '3*2Tlinux_Linux'#010+ '3*2Tnativent_Native NT API (experimental)'#010+ '3*2Tnetbsd_NetBSD'#010+ - '3*2Tnetware_Novell Net','ware Module (clib)'#010+ + '3*2Tnetware_Novell Netw','are Module (clib)'#010+ '3*2Tnetwlibc_Novell Netware Module (libc)'#010+ '3*2Topenbsd_OpenBSD'#010+ '3*2Tos2_OS/2 / eComStation'#010+ - '3*2Tsymbian_Symbian OS'#010+ '3*2Tsolaris_Solaris'#010+ + '3*2Tsymbian_Symbian OS'#010+ '3*2Twatcom_Watcom compatible DOS extender'#010+ '3*2Twdosx_WDOSX DOS extender'#010+ - '3*2Twin32_Windows ','32 Bit'#010+ + '3*2Twin32_Windows 3','2 Bit'#010+ '3*2Twince_Windows CE'#010+ '4*2Tandroid_Android'#010+ '4*2Taros_AROS'#010+ @@ -1815,7 +1815,7 @@ const msgtxt : array[0..000367,1..240] of char=( '4*2Tiphonesim_iPhoneSimulator'#010+ '4*2Tlinux_Linux'#010+ '4*2Tnetbsd_NetBSD'#010+ - '4','*2Topenbsd_OpenBSD'#010+ + '4*','2Topenbsd_OpenBSD'#010+ '4*2Tsolaris_Solaris'#010+ '4*2Twin64_Win64 (64 bit Windows systems)'#010+ '6*2Tamiga_Commodore Amiga'#010+ @@ -1825,7 +1825,7 @@ const msgtxt : array[0..000367,1..240] of char=( '6*2Tnetbsd_NetBSD'#010+ '6*2Tmacosclassic_Classic Mac OS'#010+ '6*2Tpalmos_PalmOS'#010+ - '6*','2Tsinclairql_Sinclair QL'#010+ + '6*2','Tsinclairql_Sinclair QL'#010+ '8*2Tembedded_Embedded'#010+ '8*2Tmsdos_MS-DOS (and compatible)'#010+ '8*2Twin16_Windows 16 Bit'#010+ @@ -1836,7 +1836,7 @@ const msgtxt : array[0..000367,1..240] of char=( 'A*2Tgba_Game Boy Advance'#010+ 'A*2Tios_iOS'#010+ 'A*2Tlinux_Linux'#010+ - 'A*2','Tnds_Nintendo DS'#010+ + 'A*2T','nds_Nintendo DS'#010+ 'A*2Tnetbsd_NetBSD'#010+ 'A*2Tpalmos_PalmOS'#010+ 'A*2Tsymbian_Symbian'#010+ @@ -1848,7 +1848,7 @@ const msgtxt : array[0..000367,1..240] of char=( 'a*2Tlinux_Linux'#010+ 'a*2Twin64_Windows 64'#010+ 'J*2Tandroid_Android'#010+ - 'J*2Tjava_J','ava'#010+ + 'J*2Tjava_Ja','va'#010+ 'm*2Tandroid_Android'#010+ 'm*2Tembedded_Embedded'#010+ 'm*2Tlinux_Linux'#010+ @@ -1860,99 +1860,100 @@ const msgtxt : array[0..000367,1..240] of char=( 'P*2Tembedded_Embedded'#010+ 'P*2Tlinux_Linux'#010+ 'P*2Tmacosclassic_Classic Mac OS'#010+ - 'P*2Tmorphos_M','orphOS'#010+ + 'P*2Tmorphos_Mo','rphOS'#010+ 'P*2Tnetbsd_NetBSD'#010+ 'P*2Twii_Wii'#010+ 'p*2Taix_AIX'#010+ 'p*2Tdarwin_Darwin/Mac OS X'#010+ 'p*2Tembedded_Embedded'#010+ 'p*2Tlinux_Linux'#010+ - 'R*2Tlinux_Linux'#010+ 'R*2Tembedded_Embedded'#010+ - 'r*2Tlinux_Linux'#010+ + 'R*2Tlinux_Linux'#010+ 'r*2Tembedded_Embedded'#010+ + 'r*2Tlinux_Linux'#010+ 'S*2Tlinux_Linux'#010+ 'S*2Tsolaris_Solaris'#010+ - 's*2Tlinux_Linu','x'#010+ + 's*2Tlinux_Linux',#010+ 'V*2Tembedded_Embedded'#010+ 'x*2Tembedded_Embedded'#010+ 'x*2Tfreertos_FreeRTOS'#010+ 'x*2Tlinux_Linux'#010+ 'Z*2Tembedded_Embedded'#010+ - 'Z*2Tzxspectrum_ZX Spectrum'#010+ 'Z*2Tmsxdos_MSX-DOS'#010+ + 'Z*2Tzxspectrum_ZX Spectrum'#010+ 'W*2Tembedded_Embedded'#010+ 'W*2Twasi_The WebAssembly System Interface (WASI)'#010+ - '**1u_Undefines',' the symbol '#010+ + '**1u_Undefines ','the symbol '#010+ '**1U_Unit options:'#010+ '**2Un_Do not check where the unit name matches the file name'#010+ '**2Ur_Generate release unit files (never automatically recompiled)'#010+ '**2Us_Compile a system unit'#010+ - '**1v_Be verbose. is a combination of the f','ollowing letters:'#010+ - '**2*_e : Show errors (default) 0 : Show nothing (except errors)'#010+ - '**2*_w : Show warnings u : Show unit info'#010+ - '**2*_n : Show notes t : Show tried/used files'#010+ - '**2*_h : Show hints ',' c : Show conditionals'#010+ - '**2*_i : Show general info d : Show debug info'#010+ - '**2*_l : Show linenumbers r : Rhide/GCC compatibility mode'#010+ - '**2*_s : Show time stamps q : Show message numbers'#010+ - '**2*_a : Show everything ',' x : Show info about invoked too'+ - 'ls'#010+ - '**2*_b : Write file names messages p : Write tree.log with parse tre'+ - 'e'#010+ - '**2*_ with full path v : Write fpcdebug.txt with'#010+ - '**2*_z : Write output to stderr lots of debuggin','g info'#010+ - '**2*_m, : Do not show messages numbered and '#010+ + '**1v_Be verbose. is a combination of the fo','llowing letters:'#010+ + '**2*_0 : Show nothing (except errors) p : Write tree.log with parse tr'+ + 'ee'#010+ + '**2*_a : Show everything q : Show message numbers'#010+ + '**2*_b : Write file names messages r : Rhide/GCC compatibility mode'+ + #010+ + '**2*_ with fu','ll path s : Show time stamps'#010+ + '**2*_c : Show conditionals t : Show tried/used files'#010+ + '**2*_d : Show debug info u : Show unit info'#010+ + '**2*_e : Show errors (default) v : Write fpcdebug.txt with'#010+ + '**2*_h : S','how hints lots of debugging info'#010+ + '**2*_i : Show general info w : Show warnings'#010+ + '**2*_l : Show linenumbers x : Show info about invoked tool'+ + 's'#010+ + '**2*_m, : Do not show messages numbered and ',#010+ + '**2*_n : Show notes z : Write output to stderr'#010+ 'F*1V_Append '#039'-'#039' to the used compiler binary name (e.g. f'+ 'or version)'#010+ '**1W_Target-specific options (targets)'#010+ '3*2WA_Specify native type application (Windows)'#010+ - '4*2WA_Speci','fy native type application (Windows)'#010+ + '4*2WA_Spec','ify native type application (Windows)'#010+ 'A*2WA_Specify native type application (Windows)'#010+ '3*2Wb_Create a bundle instead of a library (Darwin)'#010+ 'P*2Wb_Create a bundle instead of a library (Darwin)'#010+ - 'p*2Wb_Create a bundle instead of a library (Darwin)',#010+ + 'p*2Wb_Create a bundle instead of a library (Darwin',')'#010+ 'a*2Wb_Create a bundle instead of a library (Darwin)'#010+ 'A*2Wb_Create a bundle instead of a library (Darwin)'#010+ '4*2Wb_Create a bundle instead of a library (Darwin)'#010+ '3*2WB_Create a relocatable image (Windows, Symbian)'#010+ - '3*2WB_Set image base to ','(Windows, Symbian)'#010+ + '3*2WB_Set image base to ',' (Windows, Symbian)'#010+ '4*2WB_Create a relocatable image (Windows)'#010+ '4*2WB_Set image base to (Windows)'#010+ 'A*2WB_Create a relocatable image (Windows, Symbian)'#010+ 'A*2WB_Set image base to (Windows, Symbian)'#010+ - 'Z*2WB_Set image base to (ZX ','Spectrum)'#010+ + 'Z*2WB_Set image base to (ZX',' Spectrum)'#010+ '3*2WC_Specify console type application (EMX, OS/2, Windows)'#010+ '4*2WC_Specify console type application (Windows)'#010+ 'A*2WC_Specify console type application (Windows)'#010+ 'P*2WC_Specify console type application (Classic Mac OS)'#010+ - '3*2WD_Use DEFFIL','E to export functions of DLL or EXE (Windows)'#010+ + '3*2WD_Use DEFFI','LE to export functions of DLL or EXE (Windows)'#010+ '4*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ 'A*2WD_Use DEFFILE to export functions of DLL or EXE (Windows)'#010+ '3*2We_Use external resources (Darwin)'#010+ - '4*2We_Use external resources (Da','rwin)'#010+ + '4*2We_Use external resources (D','arwin)'#010+ 'a*2We_Use external resources (Darwin)'#010+ 'A*2We_Use external resources (Darwin)'#010+ 'P*2We_Use external resources (Darwin)'#010+ 'p*2We_Use external resources (Darwin)'#010+ '3*2WF_Specify full-screen type application (EMX, OS/2)'#010+ - '3*2WG_Specify graphic type ','application (EMX, OS/2, Windows)'#010+ + '3*2WG_Specify graphic type',' application (EMX, OS/2, Windows)'#010+ '4*2WG_Specify graphic type application (Windows)'#010+ 'A*2WG_Specify graphic type application (Windows)'#010+ 'P*2WG_Specify graphic type application (Classic Mac OS)'#010+ '3*2Wi_Use internal resources (Darwin)'#010+ - '4*2Wi_Use inter','nal resources (Darwin)'#010+ + '4*2Wi_Use inte','rnal resources (Darwin)'#010+ 'a*2Wi_Use internal resources (Darwin)'#010+ 'A*2Wi_Use internal resources (Darwin)'#010+ 'P*2Wi_Use internal resources (Darwin)'#010+ 'p*2Wi_Use internal resources (Darwin)'#010+ '3*2WI_Turn on/off the usage of import sections (Windows)'#010+ - '4*2WI_Tu','rn on/off the usage of import sections (Windows)'#010+ + '4*2WI_T','urn on/off the usage of import sections (Windows)'#010+ 'A*2WI_Turn on/off the usage of import sections (Windows)'#010+ '8*2Wh_Use huge code for units (ignored for models with CODE in a uniqu'+ 'e segment)'#010+ '8*2Wm_Set memory model'#010+ - '8*3WmTiny_Tiny memory model',#010+ + '8*3WmTiny_Tiny memory mode','l'#010+ '8*3WmSmall_Small memory model (default)'#010+ '8*3WmMedium_Medium memory model'#010+ '8*3WmCompact_Compact memory model'#010+ @@ -1960,80 +1961,80 @@ const msgtxt : array[0..000367,1..240] of char=( '8*3WmHuge_Huge memory model'#010+ '3*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ - '4*','2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Dar'+ + '4','*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Dar'+ 'win)'#010+ 'p*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ 'P*2WM_Minimum Mac OS X deployment version: 10.4, 10.5.1, ... (Darwi'+ 'n)'#010+ - '3*2WN_Do not generate r','elocation code, needed for debugging (Windows'+ + '3*2WN_Do not generate ','relocation code, needed for debugging (Windows'+ ')'#010+ '4*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ 'A*2WN_Do not generate relocation code, needed for debugging (Windows)'#010+ - 'A*2Wp_Specify the controller type; see fpc -i or f','pc -iu for poss'+ + 'A*2Wp_Specify the controller type; see fpc -i or ','fpc -iu for poss'+ 'ible values'#010+ 'm*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ 'R*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ - 'V*2Wp_Specify the controller type; see fpc -i or f','pc -iu for poss'+ + 'V*2Wp_Specify the controller type; see fpc -i or ','fpc -iu for poss'+ 'ible values'#010+ 'x*2Wp_Specify the controller type; see fpc -i or fpc -iu for possib'+ 'le values'#010+ '3*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (iphonesim)'#010+ - '4*2WP_Minimum iOS deployment version: 8.0, 8.0.2, ... (iphone','sim)'+ + '4*2WP_Minimum iOS deployment version: 8.0, 8.0.2, ... (iphon','esim)'+ #010+ 'a*2WP_Minimum iOS deployment version: 7.0, 7.1.2, ... (Darwin)'#010+ 'A*2WP_Minimum iOS deployment version: 3.0, 5.0.1, ... (Darwin)'#010+ '3*2WR_Generate relocation code (Windows)'#010+ '4*2WR_Generate relocation code (Windows)'#010+ - 'A*2WR_Generate reloca','tion code (Windows)'#010+ + 'A*2WR_Generate reloc','ation code (Windows)'#010+ '8*2Wt_Set the target executable format'#010+ - '8*3Wtexe_Create a DOS .EXE file (default)'#010+ '8*3Wtcom_Create a DOS .COM file (requires tiny memory model)'#010+ + '8*3Wtexe_Create a DOS .EXE file (default)'#010+ 'P*2WT_Specify MPW tool type application (Classic Mac OS)'#010+ - '6*2WQ_Set execu','table metadata format (Sinclair QL)'#010+ + '6*2WQ_Set exec','utable metadata format (Sinclair QL)'#010+ '6*3WQqhdr_Set metadata to QDOS File Header style (default)'#010+ '6*3WQxtcc_Set metadata to XTcc style'#010+ '**2WX_Enable executable stack (Linux)'#010+ '**1X_Executable options:'#010+ - '**2X9_Generate linkerscript for GNU Binutils ','ld older than version 2'+ + '**2X9_Generate linkerscript for GNU Binutils',' ld older than version 2'+ '.19.1 (Linux)'#010+ '**2Xa_Generate code which allows to use more than 2 GB static data on '+ '64 Bit targets (Linux)'#010+ '**2Xc_Pass --shared/-dynamic to the linker (BeOS, Darwin, FreeBSD, Lin'+ 'ux)'#010+ - '**2Xd_Do not search default library ','path (sometimes required for cro'+ + '**2Xd_Do not search default library',' path (sometimes required for cro'+ 'ss-compiling when not using -XR)'#010+ + '**2XD_Try to link units dynamically (defines FPC_LINK_DYNAMIC)'#010+ '**2Xe_Use external linker'#010+ '**2Xf_Substitute pthread library name for linking (BSD)'#010+ - '**2Xg_Create debuginfo in a separate file and add a debuglink section '+ - 'to executable'#010+ - '**2XD_Try',' to link units dynamically (defines FPC_LINK_DYNAMIC)'#010+ + '**2Xg_Create debuginfo i','n a separate file and add a debuglink sectio'+ + 'n to executable'#010+ '**2Xi_Use internal linker'#010+ 'L*2XlS_LLVM utilties suffix (e.g. -7 in case clang is called clang-'+ '7)'#010+ '**2XLA_Define library substitutions for linking'#010+ - '**2XLO_Define order of library lin','king'#010+ - '**2XLD_Exclude default order of standard libraries'#010+ + '**2XLD_Exclude default order of s','tandard libraries'#010+ + '**2XLO_Define order of library linking'#010+ '**2Xm_Generate link map'#010+ '**2XM_Set the name of the '#039'main'#039' program routine (default i'+ 's '#039'main'#039')'#010+ '**2Xn_Use target system native linker instead of GNU ld (Solaris, AIX)'+ #010+ - 'F*2Xp_First se','arch for the compiler binary in the directory '#010+ + 'F*2Xp_First s','earch for the compiler binary in the directory '#010+ '**2XP_Prepend the binutils names with the prefix '#010+ '**2Xr_Set the linker'#039's rlink-path to (needed for cross comp'+ 'ile, see the ld manual for more information) (BeOS, Linux)'#010+ - '**2XR_','Prepend to all linker search paths (BeOS, Darwin, FreeB'+ + '**2XR','_Prepend to all linker search paths (BeOS, Darwin, FreeB'+ 'SD, Linux, Mac OS, Solaris)'#010+ '**2Xs_Strip all symbols from executable'#010+ '**2XS_Try to link units statically (default, defines FPC_LINK_STATIC)'#010+ - '**2Xt_Link with static libraries (-static i','s passed to linker)'#010+ + '**2Xt_Link with static libraries (-static ','is passed to linker)'#010+ '**2Xu_Generate executable in UF2 format (embedded targets only)'#010+ '**2Xv_Generate table for Virtual Entry calls'#010+ '**2XV_Use VLink as external linker (default on Amiga, MorphOS)'#010+ - '**2XX_Try to smartlink units ','(defines FPC_LINK_SMART)'#010+ + '**2XX_Try to smartlink units ',' (defines FPC_LINK_SMART)'#010+ '**1*_'#010+ '**1?_Show this help'#010+ '**1h_Shows this help without waiting' From fec8cb76297e8a30e5c705c54e13cd769745f40f Mon Sep 17 00:00:00 2001 From: Ondrej Pokorny Date: Sat, 28 Aug 2021 16:53:04 +0200 Subject: [PATCH 111/116] * TEncoding.GetEncoding - create unicode encodings, not only MBCS --- rtl/objpas/sysutils/sysencoding.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/objpas/sysutils/sysencoding.inc b/rtl/objpas/sysutils/sysencoding.inc index 5776a05fc4..417a749c50 100644 --- a/rtl/objpas/sysutils/sysencoding.inc +++ b/rtl/objpas/sysutils/sysencoding.inc @@ -454,7 +454,7 @@ begin ACodePage := CodePageNameToCodePage(AnsiString(EncodingName)); if ACodePage = $FFFF then raise EEncodingError.CreateFmt(SNotValidCodePageName, [EncodingName]); - Result := TMBCSEncoding.Create(ACodePage); + Result := GetEncoding(ACodePage); end; function TEncoding.GetString(const Bytes: TBytes): UnicodeString; From 133f76c8b7d13e00c891007cebc4a4ceaee80594 Mon Sep 17 00:00:00 2001 From: Pierre Muller Date: Mon, 30 Aug 2021 17:33:32 +0200 Subject: [PATCH 112/116] Ignore all BuildUnit_{package_name}.pp generated file --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 863abd9ebd..1d733c3097 100644 --- a/.gitignore +++ b/.gitignore @@ -30,6 +30,7 @@ fpcmade.* *-stamp.* build-stamp.* +BuildUnit_*.pp log.* faillist.* link*.res From bb2fd561bb253910d57a33b067c269e7894acf08 Mon Sep 17 00:00:00 2001 From: florian Date: Thu, 26 Aug 2021 23:51:20 +0200 Subject: [PATCH 113/116] * do fullcycle with -j 4 --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d79d02233e..d52f7a3c4c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -13,7 +13,7 @@ compiler-fullcycle-job: stage: compilercycle script: - cd compiler - - make fullcycle + - make fullcycle -j 4 build-and-test-job: stage: buildandtest From 757868983c28a1dc93b564dcc8e38582566255bb Mon Sep 17 00:00:00 2001 From: Sven Barth Date: Mon, 30 Aug 2021 14:51:35 +0200 Subject: [PATCH 114/116] * fix #39329: adjust visibilties of PT and TArr in TVector<> and TDeque<> so that they can be correctly used either by descendants or users outside of the class --- packages/fcl-stl/src/gdeque.pp | 5 ++++- packages/fcl-stl/src/gvector.pp | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/packages/fcl-stl/src/gdeque.pp b/packages/fcl-stl/src/gdeque.pp index 54f90667e3..b39bfa0431 100644 --- a/packages/fcl-stl/src/gdeque.pp +++ b/packages/fcl-stl/src/gdeque.pp @@ -23,10 +23,13 @@ interface type generic TDeque=class - private + public type PT=^T; + protected + type TArr=array of T; + private var FData:TArr; FDataSize:SizeUInt; diff --git a/packages/fcl-stl/src/gvector.pp b/packages/fcl-stl/src/gvector.pp index 9724f1248b..deae9a4037 100644 --- a/packages/fcl-stl/src/gvector.pp +++ b/packages/fcl-stl/src/gvector.pp @@ -21,10 +21,13 @@ type { TVector } generic TVector = class - private + public type PT = ^ T; + protected + type TArr = array of T; + private var FCapacity:SizeUInt; FDataSize:SizeUInt; From 4d8ecfb42270e418060c9de45ac5a1527150c66c Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 31 Aug 2021 20:28:23 +0200 Subject: [PATCH 115/116] * unified internal error --- compiler/cgobj.pas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/cgobj.pas b/compiler/cgobj.pas index 24e0af97ec..01be2544c9 100644 --- a/compiler/cgobj.pas +++ b/compiler/cgobj.pas @@ -757,7 +757,7 @@ implementation if getsupreg(r)R_INTREGISTER then internalerror(2017091101); From 1f272f8f90cb1fc0a0a9ba3723aad13ebfcc5f03 Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 31 Aug 2021 21:24:28 +0200 Subject: [PATCH 116/116] * we cannot do SSA during partial writes to arrays which span multiple registers, resolves #39325 --- compiler/hlcgobj.pas | 8 +++++++- tests/webtbs/tw39325.pp | 8 ++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 tests/webtbs/tw39325.pp diff --git a/compiler/hlcgobj.pas b/compiler/hlcgobj.pas index 54917bfeac..b961831bd5 100644 --- a/compiler/hlcgobj.pas +++ b/compiler/hlcgobj.pas @@ -688,7 +688,8 @@ implementation fmodule, verbose,defutil,paramgr, symtable, - nbas,ncon,nld,ncgrtti,pass_2, + nbas,ncon,nld,nmem, + ncgrtti,pass_2, cgobj,cutils,procinfo, {$ifdef x86} cgx86, @@ -4652,6 +4653,11 @@ implementation inn, asn,isn: result := fen_norecurse_false; + vecn: + { we cannot do SSA during partial writes to arrays which span multiple registers, see also tw39325 } + if (tvecnode(n).left.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and + (tcgsize2size[reg_cgsize(tvecnode(n).left.location.register)]<>tvecnode(n).left.resultdef.size) then + result := fen_norecurse_false; else ; end; diff --git a/tests/webtbs/tw39325.pp b/tests/webtbs/tw39325.pp new file mode 100644 index 0000000000..b9821dedd0 --- /dev/null +++ b/tests/webtbs/tw39325.pp @@ -0,0 +1,8 @@ +{ %OPT=-Ooregvar } +program testopt; +var +ar: array[0..1] of byte; +begin +ar[0] := 1; +ar[1] := 2; +end.