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* TCGMips.a_loadfpu_reg_cgpara: temps of type Double need 8-byte alignment, according to description of sdcX/ldcX instructions. Using TCGSize2Size to specify alignment is somewhat weird, but it is being used in other CPU back-ends and looks working.

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git-svn-id: trunk@23146 -
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sergei 2012-12-15 08:47:11 +00:00
parent 1415569ecb
commit db72b8d7fd
1 changed files with 1 additions and 1 deletions
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compiler/mips/cgcpu.pas
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@ -679,7 +679,7 @@ procedure TCGMIPS.a_loadfpu_reg_cgpara(list: tasmlist; size: tcgsize; const r: t
var
href: treference;
begin
tg.GetTemp(list, TCGSize2Size[size], sizeof(aint), tt_normal, href);
tg.GetTemp(list, TCGSize2Size[size], TCGSize2Size[size], tt_normal, href);
a_loadfpu_reg_ref(list, size, size, r, href);
a_loadfpu_ref_cgpara(list, size, href, paraloc);
tg.Ungettemp(list, href);