From dc92c3eb09ccb3277ef892da3c1f665e3d7ed6da Mon Sep 17 00:00:00 2001 From: nickysn Date: Thu, 15 Oct 2015 15:59:27 +0000 Subject: [PATCH] + i8086 optimization for the code generated for 64-bit shl/shr with a constant in the range 32..47 git-svn-id: trunk@32059 - --- compiler/i8086/n8086mat.pas | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/compiler/i8086/n8086mat.pas b/compiler/i8086/n8086mat.pas index d524fd759c..55ad8edd58 100644 --- a/compiler/i8086/n8086mat.pas +++ b/compiler/i8086/n8086mat.pas @@ -445,6 +445,27 @@ implementation cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,OS_16,v-48,hreg64lo); end; end + { shifting by 32..47 } + else if (right.nodetype=ordconstn) and (v>=32) and (v<=47) and + ((not (cs_opt_size in current_settings.optimizerswitches)) or (v<=33)) then + begin + if nodetype=shln then + begin + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,hreg64lo,hreg64hi); + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,GetNextReg(hreg64lo),GetNextReg(hreg64hi)); + cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_16,0,hreg64lo); + cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_16,0,GetNextReg(hreg64lo)); + cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,v-32,hreg64hi); + end + else + begin + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,hreg64hi,hreg64lo); + cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,GetNextReg(hreg64hi),GetNextReg(hreg64lo)); + cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_16,0,hreg64hi); + cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_16,0,GetNextReg(hreg64hi)); + cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,v-32,hreg64lo); + end; + end else begin { load right operators in a register }