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* some assembling problems fixed
* improved loadaddr_ref_reg
This commit is contained in:
florian
parent
5729da12c7
commit
df906eda61
@ -36,59 +36,63 @@ F6,$02,$06,f6,32
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F7,$02,$07,f7,32
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; MM registers
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S0,$02,$00,s0,0
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S1,$02,$00,s1,0
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D0,$02,$00,d0,0
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S2,$02,$00,s2,0
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S3,$02,$00,s3,0
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D1,$02,$00,d1,0
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S4,$02,$00,s4,0
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S5,$02,$00,s5,0
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D2,$02,$00,d2,0
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S6,$02,$00,s6,0
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S7,$02,$00,s7,0
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D3,$02,$00,d3,0
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S8,$02,$00,s8,0
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S9,$02,$00,s9,0
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D4,$02,$00,d4,0
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S10,$02,$00,s10,0
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S11,$02,$00,s11,0
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D5,$02,$00,d5,0
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S12,$02,$00,s12,0
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S13,$02,$00,s13,0
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D6,$02,$00,d6,0
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S14,$02,$00,s14,0
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S15,$02,$00,s15,0
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D7,$02,$00,d7,0
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S16,$02,$00,s16,0
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S17,$02,$00,s17,0
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D8,$02,$00,d8,0
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S18,$02,$00,s18,0
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S19,$02,$00,s19,0
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D9,$02,$00,d9,0
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S20,$02,$00,s20,0
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S21,$02,$00,s21,0
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D10,$02,$00,d10,0
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S22,$02,$00,s22,0
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S23,$02,$00,s23,0
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D11,$02,$00,d11,0
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S24,$02,$00,s24,0
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S25,$02,$00,s25,0
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D12,$02,$00,d12,0
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S26,$02,$00,s26,0
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S27,$02,$00,s27,0
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D13,$02,$00,d13,0
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S28,$02,$00,s28,0
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S29,$02,$00,s29,0
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D14,$02,$00,d14,0
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S30,$02,$00,s20,0
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S31,$02,$00,s21,0
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D15,$02,$00,d15,0
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S0,$03,$00,s0,0
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S1,$03,$00,s1,0
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D0,$03,$00,d0,0
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S2,$03,$00,s2,0
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S3,$03,$00,s3,0
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D1,$03,$00,d1,0
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S4,$03,$00,s4,0
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S5,$03,$00,s5,0
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D2,$03,$00,d2,0
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S6,$03,$00,s6,0
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S7,$03,$00,s7,0
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D3,$03,$00,d3,0
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S8,$03,$00,s8,0
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S9,$03,$00,s9,0
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D4,$03,$00,d4,0
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S10,$03,$00,s10,0
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S11,$03,$00,s11,0
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D5,$03,$00,d5,0
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S12,$03,$00,s12,0
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S13,$03,$00,s13,0
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D6,$03,$00,d6,0
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S14,$03,$00,s14,0
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S15,$03,$00,s15,0
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D7,$03,$00,d7,0
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S16,$03,$00,s16,0
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S17,$03,$00,s17,0
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D8,$03,$00,d8,0
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S18,$03,$00,s18,0
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S19,$03,$00,s19,0
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D9,$03,$00,d9,0
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S20,$03,$00,s20,0
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S21,$03,$00,s21,0
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D10,$03,$00,d10,0
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S22,$03,$00,s22,0
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S23,$03,$00,s23,0
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D11,$03,$00,d11,0
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S24,$03,$00,s24,0
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S25,$03,$00,s25,0
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D12,$03,$00,d12,0
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S26,$03,$00,s26,0
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S27,$03,$00,s27,0
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D13,$03,$00,d13,0
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S28,$03,$00,s28,0
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S29,$03,$00,s29,0
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D14,$03,$00,d14,0
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S30,$03,$00,s20,0
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S31,$03,$00,s21,0
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D15,$03,$00,d15,0
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;
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; $Log$
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; Revision 1.1 2003-09-04 00:15:29 florian
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; Revision 1.2 2003-09-09 12:53:39 florian
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; * some assembling problems fixed
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; * improved loadaddr_ref_reg
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;
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; Revision 1.1 2003/09/04 00:15:29 florian
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; * first bunch of adaptions of arm compiler for new register type
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;
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;
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@ -443,7 +443,12 @@ unit cgcpu;
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not(is_pc(ref.index))
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) or
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(ref.offset<-4095) or
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(ref.offset>4095) then
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(ref.offset>4095) or
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((oppostfix in [PF_SB,PF_H,PF_SH]) and
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((ref.offset<-255) or
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(ref.offset>255)
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)
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) then
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begin
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{ check consts distance }
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@ -729,7 +734,7 @@ unit cgcpu;
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{ restore int registers and return }
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reference_reset(ref);
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ref.index:=NR_FRAME_POINTER_REG;
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- list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
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list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]),PF_EA));
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end;
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end;
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@ -744,7 +749,10 @@ unit cgcpu;
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var
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b : byte;
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tmpref : treference;
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instr : taicpu;
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begin
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if ref.addressmode<>AM_OFFSET then
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internalerror(200309071);
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tmpref:=ref;
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{ Be sure to have a base register }
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if (tmpref.base=NR_NO) then
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@ -760,12 +768,23 @@ unit cgcpu;
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((tmpref.base<>NR_NO) and (tmpref.index<>NR_NO)) then
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fixref(list,tmpref);
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if ref.index<>NR_NO then
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if tmpref.index<>NR_NO then
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begin
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{!!!!!!!}
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end
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{ else
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list.concat(taicpu.op_reg_reg(A_MOV,r,));
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ref.signindex<0 then }
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else
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begin
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if tmpref.offset>0 then
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list.concat(taicpu.op_reg_reg_const(A_ADD,r,tmpref.base,tmpref.offset))
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else if tmpref.offset<0 then
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list.concat(taicpu.op_reg_reg_const(A_SUB,r,tmpref.base,-tmpref.offset))
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else
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begin
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instr:=taicpu.op_reg_reg(A_MOV,r,tmpref.base);
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rg.add_move_instruction(instr);
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list.concat(instr);
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end;
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end;
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end;
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@ -1093,7 +1112,11 @@ begin
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end.
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{
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$Log$
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Revision 1.17 2003-09-06 16:45:51 florian
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Revision 1.18 2003-09-09 12:53:40 florian
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* some assembling problems fixed
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* improved loadaddr_ref_reg
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Revision 1.17 2003/09/06 16:45:51 florian
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* fixed exit code (no preindexed addressing mode in LDM)
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Revision 1.16 2003/09/06 11:21:50 florian
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@ -242,7 +242,7 @@ unit cpupara;
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end
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else
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begin
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nextintreg := RS_R4;
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nextintreg:=RS_R4;
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paraloc.loc:=LOC_REFERENCE;
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paraloc.reference.index:=NR_STACK_POINTER_REG;
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paraloc.reference.offset:=stack_offset;
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@ -258,7 +258,7 @@ unit cpupara;
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if nextfloatreg<=RS_F3 then
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begin
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paraloc.loc:=LOC_FPUREGISTER;
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paraloc.register:=nextfloatreg;
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paraloc.register:=newreg(R_FPUREGISTER,nextfloatreg,R_SUBWHOLE);
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inc(nextfloatreg);
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end
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else
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@ -328,7 +328,11 @@ begin
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end.
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{
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$Log$
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Revision 1.5 2003-09-05 23:57:01 florian
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Revision 1.6 2003-09-09 12:53:40 florian
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* some assembling problems fixed
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* improved loadaddr_ref_reg
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Revision 1.5 2003/09/05 23:57:01 florian
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* arm is working again as before the new register naming scheme was implemented
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Revision 1.4 2003/09/04 00:15:29 florian
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@ -24,51 +24,51 @@ NR_F4 = $02000004;
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NR_F5 = $02000005;
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NR_F6 = $02000006;
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NR_F7 = $02000007;
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NR_S0 = $02000000;
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NR_S1 = $02000000;
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NR_D0 = $02000000;
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NR_S2 = $02000000;
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NR_S3 = $02000000;
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NR_D1 = $02000000;
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NR_S4 = $02000000;
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NR_S5 = $02000000;
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NR_D2 = $02000000;
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NR_S6 = $02000000;
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NR_S7 = $02000000;
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NR_D3 = $02000000;
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NR_S8 = $02000000;
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NR_S9 = $02000000;
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NR_D4 = $02000000;
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NR_S10 = $02000000;
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NR_S11 = $02000000;
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NR_D5 = $02000000;
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NR_S12 = $02000000;
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NR_S13 = $02000000;
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NR_D6 = $02000000;
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NR_S14 = $02000000;
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NR_S15 = $02000000;
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NR_D7 = $02000000;
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NR_S16 = $02000000;
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NR_S17 = $02000000;
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NR_D8 = $02000000;
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NR_S18 = $02000000;
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NR_S19 = $02000000;
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NR_D9 = $02000000;
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NR_S20 = $02000000;
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NR_S21 = $02000000;
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NR_D10 = $02000000;
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NR_S22 = $02000000;
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NR_S23 = $02000000;
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NR_D11 = $02000000;
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NR_S24 = $02000000;
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NR_S25 = $02000000;
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NR_D12 = $02000000;
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NR_S26 = $02000000;
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NR_S27 = $02000000;
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NR_D13 = $02000000;
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NR_S28 = $02000000;
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NR_S29 = $02000000;
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NR_D14 = $02000000;
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NR_S30 = $02000000;
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NR_S31 = $02000000;
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NR_D15 = $02000000;
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NR_S0 = $03000000;
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NR_S1 = $03000000;
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NR_D0 = $03000000;
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NR_S2 = $03000000;
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NR_S3 = $03000000;
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NR_D1 = $03000000;
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NR_S4 = $03000000;
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NR_S5 = $03000000;
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NR_D2 = $03000000;
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NR_S6 = $03000000;
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NR_S7 = $03000000;
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NR_D3 = $03000000;
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NR_S8 = $03000000;
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NR_S9 = $03000000;
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NR_D4 = $03000000;
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NR_S10 = $03000000;
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NR_S11 = $03000000;
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NR_D5 = $03000000;
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NR_S12 = $03000000;
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NR_S13 = $03000000;
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NR_D6 = $03000000;
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NR_S14 = $03000000;
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NR_S15 = $03000000;
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NR_D7 = $03000000;
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NR_S16 = $03000000;
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NR_S17 = $03000000;
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NR_D8 = $03000000;
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NR_S18 = $03000000;
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NR_S19 = $03000000;
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NR_D9 = $03000000;
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NR_S20 = $03000000;
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NR_S21 = $03000000;
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NR_D10 = $03000000;
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NR_S22 = $03000000;
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NR_S23 = $03000000;
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NR_D11 = $03000000;
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NR_S24 = $03000000;
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NR_S25 = $03000000;
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NR_D12 = $03000000;
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NR_S26 = $03000000;
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NR_S27 = $03000000;
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NR_D13 = $03000000;
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NR_S28 = $03000000;
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NR_S29 = $03000000;
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NR_D14 = $03000000;
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NR_S30 = $03000000;
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NR_S31 = $03000000;
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NR_D15 = $03000000;
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@ -17,13 +17,13 @@
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15,
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16,
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17,
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50,
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51,
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52,
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53,
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54,
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55,
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56,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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@ -49,13 +49,13 @@
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47,
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48,
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49,
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66,
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67,
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68,
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69,
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70,
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71,
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72,
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50,
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51,
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52,
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53,
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54,
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55,
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56,
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57,
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58,
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59,
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@ -65,10 +65,10 @@
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63,
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64,
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65,
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18,
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19,
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20,
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21,
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22,
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23,
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24
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66,
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67,
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68,
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69,
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70,
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71,
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72
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