diff --git a/compiler/sparc/aasmcpu.pas b/compiler/sparc/aasmcpu.pas index cd1df8b764..a3731940b8 100644 --- a/compiler/sparc/aasmcpu.pas +++ b/compiler/sparc/aasmcpu.pas @@ -62,7 +62,6 @@ uses { register allocation } function is_nop:boolean;override; - function is_move:boolean;override; { register spilling code } function spilling_get_operation_type(opnr: longint): topertype;override; @@ -229,15 +228,6 @@ implementation end; - function taicpu.is_move:boolean; - begin - result:=(opcode=A_MOV) and - (oper[0]^.typ=top_reg) and - (oper[1]^.typ=top_reg); - end; - - - function taicpu.spilling_get_operation_type(opnr: longint): topertype; {$WARNING ******Check taicpu.spilling_get_operation_type******} begin @@ -354,7 +344,10 @@ implementation end. { $Log$ - Revision 1.37 2003-12-10 13:16:35 mazen + Revision 1.38 2003-12-19 14:38:03 mazen + * new TRegister definition applied + + Revision 1.37 2003/12/10 13:16:35 mazen * improve hadlign %hi and %lo operators Revision 1.36 2003/10/30 15:03:18 mazen diff --git a/compiler/sparc/cgcpu.pas b/compiler/sparc/cgcpu.pas index 2fb72496dd..a378835f8a 100644 --- a/compiler/sparc/cgcpu.pas +++ b/compiler/sparc/cgcpu.pas @@ -45,11 +45,9 @@ interface function getintregister(list:Taasmoutput;size:Tcgsize):Tregister;override; function getaddressregister(list:Taasmoutput):Tregister;override; function getfpuregister(list:Taasmoutput;size:Tcgsize):Tregister;override; - function getmmregister(list:Taasmoutput;size:Tcgsize):Tregister;override; procedure getexplicitregister(list:Taasmoutput;r:Tregister);override; procedure ungetregister(list:Taasmoutput;r:Tregister);override; procedure add_move_instruction(instr:Taicpu);override; - procedure do_register_allocation(list:Taasmoutput;headertai:tai);override; procedure allocexplicitregisters(list:Taasmoutput;rt:Tregistertype;r:Tcpuregisterset);override; procedure deallocexplicitregisters(list:Taasmoutput;rt:Tregistertype;r:Tcpuregisterset);override; function uses_registers(rt:Tregistertype):boolean;override; @@ -276,13 +274,6 @@ implementation end; - function tcgsparc.getmmregister(list:Taasmoutput;size:Tcgsize):Tregister; - begin - internalerror(200310241); - result:=RS_INVALID; - end; - - procedure tcgsparc.getexplicitregister(list:Taasmoutput;r:Tregister); begin case getregtype(r) of @@ -359,18 +350,6 @@ implementation end; - procedure tcgsparc.do_register_allocation(list:Taasmoutput;headertai:tai); - begin - { Int } - rgint.do_register_allocation(list,headertai); - rgint.translate_registers(list); - - { FPU } - rgfpu.do_register_allocation(list,headertai); - rgfpu.translate_registers(list); - end; - - function TCgSparc.reg_cgsize(const reg:tregister):tcgsize; begin result:=OS_32; @@ -1233,7 +1212,10 @@ begin end. { $Log$ - Revision 1.73 2003-12-09 09:44:22 mazen + Revision 1.74 2003-12-19 14:38:03 mazen + * new TRegister definition applied + + Revision 1.73 2003/12/09 09:44:22 mazen + added uses_registers overloaded method for sparc Revision 1.72 2003/10/29 15:18:33 mazen diff --git a/compiler/sparc/cpubase.pas b/compiler/sparc/cpubase.pas index 26bcccb036..d9e8675ee4 100644 --- a/compiler/sparc/cpubase.pas +++ b/compiler/sparc/cpubase.pas @@ -81,7 +81,7 @@ uses {$i rspnum.inc} ); - regstabs_table : array[tregisterindex] of tregister = ( + regstabs_table : array[tregisterindex] of ShortInt = ( {$i rspstab.inc} ); @@ -550,7 +550,10 @@ implementation end. { $Log$ - Revision 1.57 2003-11-10 19:05:50 peter + Revision 1.58 2003-12-19 14:38:03 mazen + * new TRegister definition applied + + Revision 1.57 2003/11/10 19:05:50 peter * fixed alias/colouring > 255 Revision 1.56 2003/11/01 19:27:54 peter diff --git a/compiler/sparc/rspcon.inc b/compiler/sparc/rspcon.inc index 91c7e0ef05..d6c8a06bd8 100644 --- a/compiler/sparc/rspcon.inc +++ b/compiler/sparc/rspcon.inc @@ -1,138 +1,138 @@ { don't edit, this file is generated from spreg.dat } -NR_NO = $00000000; -NR_G0 = $01000000; -NR_G1 = $01000001; -NR_G2 = $01000002; -NR_G3 = $01000003; -NR_G4 = $01000004; -NR_G5 = $01000005; -NR_G6 = $01000006; -NR_G7 = $01000007; -NR_O0 = $01000008; -NR_O1 = $01000009; -NR_O2 = $0100000a; -NR_O3 = $0100000b; -NR_O4 = $0100000c; -NR_O5 = $0100000d; -NR_O6 = $0100000e; -NR_O7 = $0100000f; -NR_L0 = $01000010; -NR_L1 = $01000011; -NR_L2 = $01000012; -NR_L3 = $01000013; -NR_L4 = $01000014; -NR_L5 = $01000015; -NR_L6 = $01000016; -NR_L7 = $01000017; -NR_I0 = $01000018; -NR_I1 = $01000019; -NR_I2 = $0100001a; -NR_I3 = $0100001b; -NR_I4 = $0100001c; -NR_I5 = $0100001d; -NR_I6 = $0100001e; -NR_I7 = $0100001f; -NR_F0 = $02000000; -NR_F1 = $02000001; -NR_F2 = $02000002; -NR_F3 = $02000003; -NR_F4 = $02000004; -NR_F5 = $02000005; -NR_F6 = $02000006; -NR_F7 = $02000007; -NR_F8 = $02000008; -NR_F9 = $02000009; -NR_F10 = $0200000a; -NR_F11 = $0200000b; -NR_F12 = $0200000c; -NR_F13 = $0200000d; -NR_F14 = $0200000e; -NR_F15 = $0200000f; -NR_F16 = $02000010; -NR_F17 = $02000011; -NR_F18 = $02000012; -NR_F19 = $02000013; -NR_F20 = $02000014; -NR_F21 = $02000015; -NR_F22 = $02000016; -NR_F23 = $02000017; -NR_F24 = $02000018; -NR_F25 = $02000019; -NR_F26 = $0200001a; -NR_F27 = $0200001b; -NR_F28 = $0200001c; -NR_F29 = $0200001d; -NR_F30 = $0200001e; -NR_F31 = $0200001f; -NR_C0 = $03000000; -NR_C1 = $03000001; -NR_C2 = $03000002; -NR_C3 = $03000003; -NR_C4 = $03000004; -NR_C5 = $03000005; -NR_C6 = $03000006; -NR_C7 = $03000007; -NR_C8 = $03000008; -NR_C9 = $03000009; -NR_C10 = $0300000a; -NR_C11 = $0300000b; -NR_C12 = $0300000c; -NR_C13 = $0300000d; -NR_C14 = $0300000e; -NR_C15 = $0300000f; -NR_C16 = $03000010; -NR_C17 = $03000011; -NR_C18 = $03000012; -NR_C19 = $03000013; -NR_C20 = $03000014; -NR_C21 = $03000015; -NR_C22 = $03000016; -NR_C23 = $03000017; -NR_C24 = $03000018; -NR_C25 = $03000019; -NR_C26 = $0300001a; -NR_C27 = $0300001b; -NR_C28 = $0300001c; -NR_C29 = $0300001d; -NR_C30 = $0300001e; -NR_C31 = $0300001f; -NR_FSR = $05000000; -NR_FQ = $05000001; -NR_CSR = $05000002; -NR_CQ = $05000003; -NR_PSR = $05000004; -NR_TBR = $05000005; -NR_WIM = $05000006; -NR_Y = $05000007; -NR_ASR0 = $04000000; -NR_ASR1 = $04000001; -NR_ASR2 = $04000002; -NR_ASR3 = $04000003; -NR_ASR4 = $04000004; -NR_ASR5 = $04000005; -NR_ASR6 = $04000006; -NR_ASR7 = $04000007; -NR_ASR8 = $04000008; -NR_ASR9 = $04000009; -NR_ASR10 = $0400000a; -NR_ASR11 = $0400000b; -NR_ASR12 = $0400000c; -NR_ASR13 = $0400000d; -NR_ASR14 = $0400000e; -NR_ASR15 = $0400000f; -NR_ASR16 = $04000010; -NR_ASR17 = $04000011; -NR_ASR18 = $04000012; -NR_ASR19 = $04000013; -NR_ASR20 = $04000014; -NR_ASR21 = $04000015; -NR_ASR22 = $04000016; -NR_ASR23 = $04000017; -NR_ASR24 = $04000018; -NR_ASR25 = $04000019; -NR_ASR26 = $0400001a; -NR_ASR27 = $0400001b; -NR_ASR28 = $0400001c; -NR_ASR29 = $0400001d; -NR_ASR30 = $0400001e; -NR_ASR31 = $0400001f; +NR_NO = TRegister($00000000); +NR_G0 = TRegister($01000000); +NR_G1 = TRegister($01000001); +NR_G2 = TRegister($01000002); +NR_G3 = TRegister($01000003); +NR_G4 = TRegister($01000004); +NR_G5 = TRegister($01000005); +NR_G6 = TRegister($01000006); +NR_G7 = TRegister($01000007); +NR_O0 = TRegister($01000008); +NR_O1 = TRegister($01000009); +NR_O2 = TRegister($0100000a); +NR_O3 = TRegister($0100000b); +NR_O4 = TRegister($0100000c); +NR_O5 = TRegister($0100000d); +NR_O6 = TRegister($0100000e); +NR_O7 = TRegister($0100000f); +NR_L0 = TRegister($01000010); +NR_L1 = TRegister($01000011); +NR_L2 = TRegister($01000012); +NR_L3 = TRegister($01000013); +NR_L4 = TRegister($01000014); +NR_L5 = TRegister($01000015); +NR_L6 = TRegister($01000016); +NR_L7 = TRegister($01000017); +NR_I0 = TRegister($01000018); +NR_I1 = TRegister($01000019); +NR_I2 = TRegister($0100001a); +NR_I3 = TRegister($0100001b); +NR_I4 = TRegister($0100001c); +NR_I5 = TRegister($0100001d); +NR_I6 = TRegister($0100001e); +NR_I7 = TRegister($0100001f); +NR_F0 = TRegister($02000000); +NR_F1 = TRegister($02000001); +NR_F2 = TRegister($02000002); +NR_F3 = TRegister($02000003); +NR_F4 = TRegister($02000004); +NR_F5 = TRegister($02000005); +NR_F6 = TRegister($02000006); +NR_F7 = TRegister($02000007); +NR_F8 = TRegister($02000008); +NR_F9 = TRegister($02000009); +NR_F10 = TRegister($0200000a); +NR_F11 = TRegister($0200000b); +NR_F12 = TRegister($0200000c); +NR_F13 = TRegister($0200000d); +NR_F14 = TRegister($0200000e); +NR_F15 = TRegister($0200000f); +NR_F16 = TRegister($02000010); +NR_F17 = TRegister($02000011); +NR_F18 = TRegister($02000012); +NR_F19 = TRegister($02000013); +NR_F20 = TRegister($02000014); +NR_F21 = TRegister($02000015); +NR_F22 = TRegister($02000016); +NR_F23 = TRegister($02000017); +NR_F24 = TRegister($02000018); +NR_F25 = TRegister($02000019); +NR_F26 = TRegister($0200001a); +NR_F27 = TRegister($0200001b); +NR_F28 = TRegister($0200001c); +NR_F29 = TRegister($0200001d); +NR_F30 = TRegister($0200001e); +NR_F31 = TRegister($0200001f); +NR_C0 = TRegister($03000000); +NR_C1 = TRegister($03000001); +NR_C2 = TRegister($03000002); +NR_C3 = TRegister($03000003); +NR_C4 = TRegister($03000004); +NR_C5 = TRegister($03000005); +NR_C6 = TRegister($03000006); +NR_C7 = TRegister($03000007); +NR_C8 = TRegister($03000008); +NR_C9 = TRegister($03000009); +NR_C10 = TRegister($0300000a); +NR_C11 = TRegister($0300000b); +NR_C12 = TRegister($0300000c); +NR_C13 = TRegister($0300000d); +NR_C14 = TRegister($0300000e); +NR_C15 = TRegister($0300000f); +NR_C16 = TRegister($03000010); +NR_C17 = TRegister($03000011); +NR_C18 = TRegister($03000012); +NR_C19 = TRegister($03000013); +NR_C20 = TRegister($03000014); +NR_C21 = TRegister($03000015); +NR_C22 = TRegister($03000016); +NR_C23 = TRegister($03000017); +NR_C24 = TRegister($03000018); +NR_C25 = TRegister($03000019); +NR_C26 = TRegister($0300001a); +NR_C27 = TRegister($0300001b); +NR_C28 = TRegister($0300001c); +NR_C29 = TRegister($0300001d); +NR_C30 = TRegister($0300001e); +NR_C31 = TRegister($0300001f); +NR_FSR = TRegister($05000000); +NR_FQ = TRegister($05000001); +NR_CSR = TRegister($05000002); +NR_CQ = TRegister($05000003); +NR_PSR = TRegister($05000004); +NR_TBR = TRegister($05000005); +NR_WIM = TRegister($05000006); +NR_Y = TRegister($05000007); +NR_ASR0 = TRegister($04000000); +NR_ASR1 = TRegister($04000001); +NR_ASR2 = TRegister($04000002); +NR_ASR3 = TRegister($04000003); +NR_ASR4 = TRegister($04000004); +NR_ASR5 = TRegister($04000005); +NR_ASR6 = TRegister($04000006); +NR_ASR7 = TRegister($04000007); +NR_ASR8 = TRegister($04000008); +NR_ASR9 = TRegister($04000009); +NR_ASR10 = TRegister($0400000a); +NR_ASR11 = TRegister($0400000b); +NR_ASR12 = TRegister($0400000c); +NR_ASR13 = TRegister($0400000d); +NR_ASR14 = TRegister($0400000e); +NR_ASR15 = TRegister($0400000f); +NR_ASR16 = TRegister($04000010); +NR_ASR17 = TRegister($04000011); +NR_ASR18 = TRegister($04000012); +NR_ASR19 = TRegister($04000013); +NR_ASR20 = TRegister($04000014); +NR_ASR21 = TRegister($04000015); +NR_ASR22 = TRegister($04000016); +NR_ASR23 = TRegister($04000017); +NR_ASR24 = TRegister($04000018); +NR_ASR25 = TRegister($04000019); +NR_ASR26 = TRegister($0400001a); +NR_ASR27 = TRegister($0400001b); +NR_ASR28 = TRegister($0400001c); +NR_ASR29 = TRegister($0400001d); +NR_ASR30 = TRegister($0400001e); +NR_ASR31 = TRegister($0400001f);