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* MIPS: removed specific handling of 32-bit shifts, generic code does the job just well.

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* Tweak 64-bit shifts to take advantage of 3-address instructions (i.e. don't operate on same register).

git-svn-id: trunk@26142 -
This commit is contained in:
sergei 2013-11-27 11:33:52 +00:00
parent a2c561ebbe
commit e16e19b170
1 changed files with 43 additions and 75 deletions
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118
compiler/mips/ncpumat.pas
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@ -35,8 +35,8 @@ type
procedure pass_generate_code;override; procedure pass_generate_code;override;
end; end;
tMIPSELshlshrnode = class(tshlshrnode) tMIPSELshlshrnode = class(tcgshlshrnode)
procedure pass_generate_code;override; procedure second_64bit;override;
{ everything will be handled in pass_2 } { everything will be handled in pass_2 }
function first_shlshr64bitint: tnode; override; function first_shlshr64bitint: tnode; override;
end; end;
@ -164,96 +164,65 @@ begin
end; end;
procedure tMIPSELshlshrnode.pass_generate_code; procedure tMIPSELshlshrnode.second_64bit;
var var
hregister, hreg64hi, hreg64lo: tregister; hregister, hreg64hi, hreg64lo: tregister;
op: topcg; op: topcg;
shiftval: aword; shiftval: aword;
const
ops: array [boolean] of topcg = (OP_SHR,OP_SHL);
begin begin
{ 64bit without constants need a helper, and is { 64bit without constants need a helper, and is
already replaced in pass1 } already replaced in pass1 }
if is_64bit(left.resultdef) and if (right.nodetype <> ordconstn) then
(right.nodetype <> ordconstn) then
internalerror(200405301); internalerror(200405301);
secondpass(left); location_reset(location, LOC_REGISTER, def_cgsize(resultdef));
secondpass(right);
if is_64bit(left.resultdef) then { load left operator in a register }
hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, resultdef, true);
hreg64hi := left.location.register64.reghi;
hreg64lo := left.location.register64.reglo;
shiftval := tordconstnode(right).Value.svalue and 63;
op := ops[nodetype=shln];
if shiftval > 31 then
begin begin
location_reset(location, LOC_REGISTER, OS_64); if nodetype = shln then
{ load left operator in a register }
hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, u64inttype, False);
hreg64hi := left.location.register64.reghi;
hreg64lo := left.location.register64.reglo;
shiftval := tordconstnode(right).Value.svalue and 63;
if shiftval > 31 then
begin begin
if nodetype = shln then location.register64.reglo:=NR_R0;
begin location.register64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_32, 0, hreg64hi); { if shiftval and 31 = 0, it will optimize to MOVE }
if (shiftval and 31) <> 0 then cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval and 31, hreg64lo, location.register64.reghi);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval and 31, hreg64lo, hreg64lo);
end
else
begin
cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_32, 0, hreg64lo);
if (shiftval and 31) <> 0 then
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval and 31, hreg64hi, hreg64hi);
end;
location.register64.reglo := hreg64hi;
location.register64.reghi := hreg64lo;
end end
else else
begin begin
if shiftval <> 0 then location.register64.reghi:=NR_R0;
begin location.register64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
hregister := cg.getintregister(current_asmdata.CurrAsmList, OS_32); cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval and 31, hreg64hi, location.register64.reglo);
if nodetype = shln then
begin
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, 32 - shiftval, hreg64lo, hregister);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval, hreg64hi, hreg64hi);
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, hreg64hi, hreg64hi);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval, hreg64lo, hreg64lo);
end
else
begin
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, 32 - shiftval, hreg64hi, hregister);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval, hreg64lo, hreg64lo);
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, hreg64lo, hreg64lo);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval, hreg64hi, hreg64hi);
end;
end;
location.register64.reghi := hreg64hi;
location.register64.reglo := hreg64lo;
end; end;
end end
else else
begin begin
{ load left operators in a register } location.register64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, left.resultdef, True); location.register64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
location_reset(location,LOC_REGISTER,def_cgsize(resultdef)); hregister := cg.getintregister(current_asmdata.CurrAsmList, OS_32);
location.register:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
{ determine operator } cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, shiftval, hreg64hi, location.register64.reghi);
if nodetype = shln then cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, shiftval, hreg64lo, location.register64.reglo);
op := OP_SHL if shiftval <> 0 then
else begin
op := OP_SHR; if nodetype = shln then
{ shifting by a constant directly coded: } begin
if (right.nodetype = ordconstn) then cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, 32-shiftval, hreg64lo, hregister);
begin cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, location.register64.reghi, location.register64.reghi);
if tordconstnode(right).Value.svalue and 31 <> 0 then end
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, tordconstnode(right).Value.svalue and 31, left.location.register, location.register); else
end begin
else cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, 32-shiftval, hreg64hi, hregister);
begin cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, location.register64.reglo, location.register64.reglo);
{ load shift count in a register if necessary } end;
hlcg.location_force_reg(current_asmdata.CurrAsmList, right.location, right.resultdef, right.resultdef, True); end;
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, op, OS_32, right.location.Register, left.location.register, location.register);
end;
end; end;
end; end;
@ -266,7 +235,6 @@ procedure tMIPSELnotnode.second_boolean;
var var
hl: tasmlabel; hl: tasmlabel;
tmpreg : TRegister; tmpreg : TRegister;
r64: TRegister64;
begin begin
{ if the location is LOC_JUMP, we do the secondpass after the { if the location is LOC_JUMP, we do the secondpass after the
labels are allocated labels are allocated