diff --git a/compiler/riscv/nrvutil.pas b/compiler/riscv/nrvutil.pas
index 0891a58f14..27a2b3bcca 100644
--- a/compiler/riscv/nrvutil.pas
+++ b/compiler/riscv/nrvutil.pas
@@ -65,9 +65,15 @@ implementation
           current_asmdata.asmlists[al_start].Concat(tai_attribute.create(ait_attribute,tag_stack_align,target_info.stackalign));
           current_asmdata.asmlists[al_start].Concat(tai_attribute.create(ait_attribute,tag_unaligned_access,0));
 {$if defined(RISCV32)}
-          attr_arch:='rv32i2p1';
+          if CPURV_HAS_16REGISTERS in cpu_capabilities[current_settings.cputype] then
+            attr_arch:='rv32e2p0'
+          else
+            attr_arch:='rv32i2p1';
 {$elseif defined(RISCV64)}
-          attr_arch:='rv64i2p1';
+          if CPURV_HAS_16REGISTERS in cpu_capabilities[current_settings.cputype] then
+            attr_arch:='rv64e2p0'
+          else
+            attr_arch:='rv64i2p1';
 {$elseif defined(RISCV128)}
           attr_arch:='rv128i2p1';
 {$endif defined(RISCV32)}
diff --git a/compiler/riscv64/cpuinfo.pas b/compiler/riscv64/cpuinfo.pas
index 21a7912776..4ef4e0112b 100644
--- a/compiler/riscv64/cpuinfo.pas
+++ b/compiler/riscv64/cpuinfo.pas
@@ -127,6 +127,7 @@ Const
       (CPURV_HAS_MUL,
        CPURV_HAS_ATOMIC,
        CPURV_HAS_COMPACT,
+       CPURV_HAS_16REGISTERS,
        CPURV_HAS_ZBA,
        CPURV_HAS_ZBB,
        CPURV_HAS_ZBC,