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+ Merge Add/Sub optimization
git-svn-id: trunk@49508 -
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@ -110,7 +110,8 @@ Implementation
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systems,
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cpuinfo,
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cgobj,procinfo,
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aasmbase,aasmdata;
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aasmbase,aasmdata,
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aoptutils;
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{ Range check must be disabled explicitly as conversions between signed and unsigned
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32-bit values are done without explicit typecasts }
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@ -556,6 +557,9 @@ Implementation
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function TCpuAsmOptimizer.OptPass1ADDSUB(var p: tai): Boolean;
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var
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hp1,hp2: tai;
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sign: Integer;
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newvalue: TCGInt;
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b: byte;
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begin
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Result := OptPass1DataCheckMov(p);
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@ -622,6 +626,45 @@ Implementation
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end;
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end;
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{
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optimize
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add/sub rx,ry,const1
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add/sub rx,rx,const2
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into
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add/sub rx,ry,const1+/-const
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check if the first operation has no postfix and condition
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}
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if MatchInstruction(p,[A_ADD,A_SUB],[C_None],[PF_None]) and
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MatchOptype(taicpu(p),top_reg,top_reg,top_const) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1,[A_ADD,A_SUB],[C_None],[PF_None]) and
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MatchOptype(taicpu(hp1),top_reg,top_reg,top_const) and
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MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[0]^) and
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MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) then
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begin
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sign:=1;
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if (taicpu(p).opcode=A_SUB) xor (taicpu(hp1).opcode=A_SUB) then
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sign:=-1;
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newvalue:=taicpu(p).oper[2]^.val+sign*taicpu(hp1).oper[2]^.val;
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if (not(GenerateThumbCode) and is_shifter_const(newvalue,b)) or
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(GenerateThumbCode and is_thumb_imm(newvalue)) then
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begin
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DebugMsg(SPeepholeOptimization + 'Merge Add/Sub done', p);
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taicpu(p).oper[2]^.val:=newvalue;
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RemoveInstruction(hp1);
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Result:=true;
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if newvalue=0 then
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begin
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RemoveCurrentP(p);
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Exit;
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end;
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end;
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end;
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if (taicpu(p).condition = C_None) and
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(taicpu(p).oppostfix = PF_None) and
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LookForPreindexedPattern(taicpu(p)) then
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