From e2241d97a20287cf4c78e9ee1cfce97b10800a67 Mon Sep 17 00:00:00 2001 From: nickysn Date: Sun, 2 Jun 2013 09:35:30 +0000 Subject: [PATCH] * i8086 optimizations for 32-bit OP_SAR with const >= 16 git-svn-id: trunk@24757 - --- compiler/i8086/cgcpu.pas | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/compiler/i8086/cgcpu.pas b/compiler/i8086/cgcpu.pas index d183c470a0..0be3cea2f2 100644 --- a/compiler/i8086/cgcpu.pas +++ b/compiler/i8086/cgcpu.pas @@ -217,8 +217,9 @@ unit cgcpu; to the high reg, then zero the low register, then do the remaining part of the shift (by const-16) in 16 bit on the high register. the same thing applies to shr with low and high - reversed. } - if (op in [OP_SHR,OP_SHL]) and (a >= 16) then + reversed. sar is exactly like shr, except that instead of + zeroing the high register, we sar it by 15. } + if a>=16 then case op of OP_SHR: begin @@ -232,6 +233,12 @@ unit cgcpu; a_load_const_reg(list,OS_16,0,reg); a_op_const_reg(list,OP_SHL,OS_16,a-16,GetNextReg(reg)); end; + OP_SAR: + begin + a_load_reg_reg(list,OS_16,OS_16,GetNextReg(reg),reg); + a_op_const_reg(list,OP_SAR,OS_16,15,GetNextReg(reg)); + a_op_const_reg(list,OP_SAR,OS_16,a-16,reg); + end; else internalerror(2013060201); end