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* fold <arithmed. op> ...; cmp ...,#0into cmps on arm
* remove unnecessary ldr after str to the same memoy location, however, to do this optimization safely, we should add support for volatile variables git-svn-id: trunk@20399 -
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florian
parent
f0f64a573b
commit
e2c9a8c6a1
@ -36,8 +36,8 @@ Type
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2;override;
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procedure PeepHoleOptPass2;override;
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End;
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End;
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TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
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TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
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{ uses the same constructor as TAopObj }
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{ uses the same constructor as TAopObj }
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procedure PeepHoleOptPass2;override;
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procedure PeepHoleOptPass2;override;
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@ -47,6 +47,7 @@ Implementation
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uses
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uses
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verbose,
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verbose,
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cgutils,
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aasmbase,aasmcpu;
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aasmbase,aasmcpu;
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function CanBeCond(p : tai) : boolean;
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function CanBeCond(p : tai) : boolean;
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@ -59,95 +60,174 @@ Implementation
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end;
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end;
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function RefsEqual(const r1, r2: treference): boolean;
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begin
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refsequal :=
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(r1.offset = r2.offset) and
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(r1.base = r2.base) and
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(r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
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(r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
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(r1.relsymbol = r2.relsymbol) and
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(r1.signindex = r2.signindex) and
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(r1.shiftimm = r2.shiftimm) and
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(r1.addressmode = r2.addressmode) and
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(r1.shiftmode = r2.shiftmode);
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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var
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next1: tai;
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next1: tai;
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hp1: tai;
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hp1,hp2: tai;
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begin
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begin
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result := false;
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result := false;
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case p.typ of
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case p.typ of
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ait_instruction:
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ait_instruction:
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begin
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begin
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case taicpu(p).opcode of
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{
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A_MOV:
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change
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begin
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<op> reg,x,y
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{ fold
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cmp reg,#0
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mov reg1,reg0, shift imm1
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into
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mov reg1,reg1, shift imm2
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<op>s reg,x,y
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to
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}
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mov reg1,reg0, shift imm1+imm2
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{ this optimization can applied only to the currently enabled operations because
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}
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the other operations do not update all flags and FPC does not track flag usage }
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if (taicpu(p).ops=3) and
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if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oppostfix = PF_None) and
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(taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).condition = C_None) and
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getnextinstruction(p,next1) and
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GetNextInstruction(p, hp1) and
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(next1.typ = ait_instruction) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(next1).opcode = A_MOV) and
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(taicpu(hp1).opcode = A_CMP) and
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(taicpu(p).condition=taicpu(next1).condition) and
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(taicpu(hp1).oppostfix = PF_None) and
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(taicpu(next1).ops=3) and
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(taicpu(hp1).condition = C_None) and
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(taicpu(next1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.typ = top_const) and
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(taicpu(next1).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[1]^.reg) and
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(taicpu(hp1).oper[1]^.val = 0) { and
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(taicpu(next1).oper[2]^.typ = top_shifterop) and
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GetNextInstruction(hp1, hp2) and
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(taicpu(next1).oper[2]^.shifterop^.rs = NR_NO) and
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(tai(hp2).typ = ait_instruction) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(next1).oper[2]^.shifterop^.shiftmode) then
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// be careful here, following instructions could use other flags
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begin
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// however after a jump fpc never depends on the value of flags
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inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(next1).oper[2]^.shifterop^.shiftimm);
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(taicpu(hp2).opcode = A_B) and
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{ avoid overflows }
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(taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL])} then
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if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
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begin
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case taicpu(p).oper[2]^.shifterop^.shiftmode of
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taicpu(p).oppostfix:=PF_S;
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SM_ROR:
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asml.remove(hp1);
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taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
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hp1.free;
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SM_ASR:
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end
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taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
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else
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SM_LSR,
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case taicpu(p).opcode of
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SM_LSL:
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A_STR:
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begin
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begin
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hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
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{ change
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InsertLLItem(p.previous, p.next, hp1);
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str reg1,ref
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p.free;
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ldr reg2,ref
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p:=hp1;
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into
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end;
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str reg1,ref
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else
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mov reg2,reg1
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internalerror(2008072803);
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}
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end;
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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asml.remove(next1);
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getnextinstruction(p,hp1) and
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next1.free;
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(hp1.typ = ait_instruction) and
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result := true;
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(taicpu(hp1).opcode = A_LDR) and
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end;
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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end;
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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A_AND:
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begin
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begin
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if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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{
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begin
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change
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asml.remove(hp1);
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and reg2,reg1,const1
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hp1.free;
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and reg2,reg2,const2
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end
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to
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else
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and reg2,reg1,(const1 and const2)
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begin
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}
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taicpu(hp1).opcode:=A_MOV;
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if (taicpu(p).oper[0]^.typ = top_reg) and
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taicpu(hp1).oppostfix:=PF_None;
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(taicpu(p).oper[1]^.typ = top_reg) and
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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(taicpu(p).oper[2]^.typ = top_const) and
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end;
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GetNextInstruction(p, hp1) and
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result := true;
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(tai(hp1).typ = ait_instruction) and
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end;
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(taicpu(hp1).opcode = A_AND) and
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end;
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(taicpu(p).condition=taicpu(hp1).condition) and
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A_MOV:
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(taicpu(p).oppostfix=PF_None) and
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begin
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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{ fold
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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mov reg1,reg0, shift imm1
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(taicpu(hp1).oper[2]^.typ = top_const) and
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mov reg1,reg1, shift imm2
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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to
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(taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
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mov reg1,reg0, shift imm1+imm2
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begin
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}
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taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
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if (taicpu(p).ops=3) and
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taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
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(taicpu(p).oper[0]^.typ = top_reg) and
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asml.remove(hp1);
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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hp1.free;
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(taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
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end;
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getnextinstruction(p,next1) and
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end;
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(next1.typ = ait_instruction) and
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end;
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(taicpu(next1).opcode = A_MOV) and
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(taicpu(p).condition=taicpu(next1).condition) and
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(taicpu(next1).ops=3) and
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(taicpu(next1).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[0]^.reg) and
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(taicpu(next1).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg=taicpu(next1).oper[1]^.reg) and
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(taicpu(next1).oper[2]^.typ = top_shifterop) and
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(taicpu(next1).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(next1).oper[2]^.shifterop^.shiftmode) then
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begin
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inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(next1).oper[2]^.shifterop^.shiftimm);
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{ avoid overflows }
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if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
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case taicpu(p).oper[2]^.shifterop^.shiftmode of
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SM_ROR:
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taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
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SM_ASR:
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taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
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SM_LSR,
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SM_LSL:
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begin
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hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p:=hp1;
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end;
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else
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internalerror(2008072803);
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end;
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asml.remove(next1);
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next1.free;
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result := true;
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end;
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end;
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A_AND:
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begin
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{
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change
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and reg2,reg1,const1
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and reg2,reg2,const2
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to
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and reg2,reg1,(const1 and const2)
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}
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_AND) and
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(taicpu(p).condition=taicpu(hp1).condition) and
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(taicpu(p).oppostfix=PF_None) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(taicpu(hp1).oper[2]^.typ = top_const) and
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
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begin
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taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
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taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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end;
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end;
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end;
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end;
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end;
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end;
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end;
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