mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-11-02 05:09:49 +01:00
Added support for X,Y,and Z register aliases plus low/high forms, and post-incrementation in AVR assembler reader.
Cleaned up parameter and funcretloc information generation in AVR paramanger, and made it closer to GCC's calling convention. Fixed a number of codegenerator bugs generating invalid or broken instructions: CP operands were swapped, a number of instructions had immediate operands, and stack frame epilogue wasn't complete. Added a bunch of peephole optimizations that clears the generated code up a lot. git-svn-id: trunk@26925 -
This commit is contained in:
Jeppe Johansen
parent
68f1a51164
commit
e33550b67d
@ -246,12 +246,16 @@ implementation
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begin
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result:=operand_read;
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case opcode of
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A_CLR,
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A_MOV, A_MOVW:
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if opnr=0 then
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result:=operand_write;
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A_CP,A_CPC,A_CPI,A_PUSH :
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;
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else
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begin
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if opnr=0 then
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result:=operand_write;
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result:=operand_readwrite;
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end;
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end;
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end;
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@ -28,10 +28,12 @@ Unit aoptcpu;
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Interface
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uses cpubase, aasmtai, aopt, aoptcpub;
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uses cpubase, cgbase, aasmtai, aopt, aoptcpub;
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Type
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TCpuAsmOptimizer = class(TAsmOptimizer)
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Function GetNextInstructionUsingReg(Current: tai; Var Next: tai;reg : TRegister): Boolean;
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2;override;
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@ -40,7 +42,8 @@ Type
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Implementation
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uses
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aasmbase,aasmcpu,cgbase;
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aasmbase,aasmcpu,
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globals,globtype;
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function CanBeCond(p : tai) : boolean;
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begin
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@ -48,40 +51,254 @@ Implementation
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end;
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function TCpuAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
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var Next: tai; reg: TRegister): Boolean;
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begin
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Next:=Current;
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repeat
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Result:=GetNextInstruction(Next,Next);
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until not(cs_opt_level3 in current_settings.optimizerswitches) or not(Result) or (Next.typ<>ait_instruction) or (RegInInstruction(reg,Next)) or
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(is_calljmp(taicpu(Next).opcode));
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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next1: tai;
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hp1,hp2,hp3: tai;
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alloc, dealloc: tai_regalloc;
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i: integer;
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begin
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result := false;
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case p.typ of
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_LDI:
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begin
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{ turn
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ldi reg0, imm
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cp reg1, reg0
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dealloc reg0
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into
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cpi reg1, imm
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}
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if (taicpu(p).ops=2) and
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(taicpu(p).oper[0]^.typ=top_reg) and
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(taicpu(p).oper[1]^.typ=top_const) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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(not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
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(taicpu(hp1).opcode=A_CP) and
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(taicpu(hp1).ops=2) and
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(taicpu(hp1).oper[1]^.typ=top_reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg) in [16..31]) and
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(taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
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assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
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begin
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taicpu(hp1).opcode:=A_CPI;
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taicpu(hp1).loadconst(1, taicpu(p).oper[1]^.val);
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alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
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dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
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if assigned(alloc) and assigned(dealloc) then
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begin
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asml.Remove(alloc);
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alloc.Free;
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asml.Remove(dealloc);
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dealloc.Free;
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end;
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GetNextInstruction(p,hp1);
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asml.Remove(p);
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p.Free;
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p:=hp1;
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result:=true;
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end;
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end;
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A_CLR:
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begin
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{ turn the common
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clr rX
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mov/ld rX, rY
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into
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mov/ld rX, rY
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}
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if (taicpu(p).ops=1) and
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(taicpu(p).oper[0]^.typ=top_reg) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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(not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
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(hp1.typ=ait_instruction) and
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(taicpu(hp1).opcode in [A_MOV,A_LD]) and
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(taicpu(hp1).ops>0) and
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(taicpu(hp1).oper[0]^.typ=top_reg) and
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(taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) then
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begin
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asml.Remove(p);
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p.Free;
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p:=hp1;
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result:=true;
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end
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{ turn
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clr rX
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...
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adc rY, rX
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into
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...
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adc rY, r1
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}
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else if (taicpu(p).ops=1) and
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(taicpu(p).oper[0]^.typ=top_reg) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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(not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
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(hp1.typ=ait_instruction) and
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(taicpu(hp1).opcode in [A_ADC,A_SBC]) and
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(taicpu(hp1).ops=2) and
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(taicpu(hp1).oper[1]^.typ=top_reg) and
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(taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[0]^.reg<>taicpu(p).oper[0]^.reg) and
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assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
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begin
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taicpu(hp1).oper[1]^.reg:=NR_R1;
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alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
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dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
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if assigned(alloc) and assigned(dealloc) then
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begin
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asml.Remove(alloc);
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alloc.Free;
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asml.Remove(dealloc);
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dealloc.Free;
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end;
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GetNextInstruction(p,hp1);
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asml.Remove(p);
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p.free;
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p:=hp1;
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result:=true;
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end;
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end;
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A_PUSH:
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begin
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{ turn
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push reg0
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push reg1
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pop reg3
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pop reg2
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into
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movw reg2,reg0
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}
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if (taicpu(p).ops=1) and
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(taicpu(p).oper[0]^.typ=top_reg) and
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GetNextInstruction(p,hp1) and
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(hp1.typ=ait_instruction) and
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(taicpu(hp1).opcode=A_PUSH) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
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((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
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GetNextInstruction(hp1,hp2) and
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(hp2.typ=ait_instruction) and
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(taicpu(hp2).opcode=A_POP) and
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GetNextInstruction(hp2,hp3) and
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(hp3.typ=ait_instruction) and
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(taicpu(hp3).opcode=A_POP) and
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(getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp3).oper[0]^.reg)+1) and
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((getsupreg(taicpu(hp3).oper[0]^.reg) mod 2)=0) then
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begin
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taicpu(p).ops:=2;
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taicpu(p).opcode:=A_MOVW;
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taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
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taicpu(p).loadreg(0, taicpu(hp3).oper[0]^.reg);
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asml.Remove(hp1);
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hp1.Free;
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asml.Remove(hp2);
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hp2.Free;
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asml.Remove(hp3);
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hp3.Free;
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result:=true;
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end;
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end;
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A_MOV:
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begin
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{ turn
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mov reg0, reg1
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push reg0
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dealloc reg0
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into
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push reg1
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}
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if (taicpu(p).ops=2) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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(not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode in [A_PUSH,A_MOV,A_CP,A_CPC,A_ADD,A_SUB,A_EOR,A_AND,A_OR]) and
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RegInInstruction(taicpu(p).oper[0]^.reg, hp1) and
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(not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1)) and
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{(taicpu(hp1).ops=1) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and }
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assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
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begin
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for i := 0 to taicpu(hp1).ops-1 do
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if taicpu(hp1).oper[i]^.typ=top_reg then
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if taicpu(hp1).oper[i]^.reg=taicpu(p).oper[0]^.reg then
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taicpu(hp1).oper[i]^.reg:=taicpu(p).oper[1]^.reg;
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alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
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dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
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if assigned(alloc) and assigned(dealloc) then
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begin
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asml.Remove(alloc);
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alloc.Free;
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asml.Remove(dealloc);
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dealloc.Free;
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end;
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GetNextInstruction(p,hp1);
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asml.Remove(p);
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p.free;
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p:=hp1;
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result:=true;
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end
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{ fold
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mov reg2,reg0
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mov reg3,reg1
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to
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movw reg2,reg0
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}
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if (taicpu(p).ops=2) and
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else if (taicpu(p).ops=2) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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(taicpu(next1).opcode = A_MOV) and
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(taicpu(next1).ops=2) and
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(taicpu(next1).oper[0]^.typ = top_reg) and
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(taicpu(next1).oper[1]^.typ = top_reg) and
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(getsupreg(taicpu(next1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
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getnextinstruction(p,hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_MOV) and
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(taicpu(hp1).ops=2) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
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((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
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((getsupreg(taicpu(p).oper[1]^.reg) mod 2)=0) and
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(getsupreg(taicpu(next1).oper[1]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)+1) then
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(getsupreg(taicpu(hp1).oper[1]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)+1) then
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begin
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alloc:=FindRegAllocBackward(taicpu(hp1).oper[0]^.reg,tai(hp1.Previous));
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if assigned(alloc) then
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begin
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asml.Remove(alloc);
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asml.InsertBefore(alloc,p);
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end;
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taicpu(p).opcode:=A_MOVW;
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asml.remove(next1);
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next1.free;
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asml.remove(hp1);
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hp1.free;
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result := true;
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end;
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end;
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@ -36,7 +36,10 @@ Unit aoptcpub; { Assembler OPTimizer CPU specific Base }
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Interface
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Uses
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cpubase,aasmcpu,AOptBase;
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cpubase,
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cgbase,
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aasmcpu,aasmtai,
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AOptBase;
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Type
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@ -58,6 +61,7 @@ Type
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{ ************************************************************************* }
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TAoptBaseCpu = class(TAoptBase)
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function RegModifiedByInstruction(Reg: TRegister; p1: tai): boolean; override;
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End;
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@ -103,12 +107,26 @@ Implementation
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{ ************************************************************************* }
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{ **************************** TCondRegs ********************************** }
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{ ************************************************************************* }
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Constructor TCondRegs.init;
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Begin
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End;
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Constructor TCondRegs.init;
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Begin
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End;
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Destructor TCondRegs.Done; {$ifdef inl} inline; {$endif inl}
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Begin
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End;
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Destructor TCondRegs.Done; {$ifdef inl} inline; {$endif inl}
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Begin
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End;
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function TAoptBaseCpu.RegModifiedByInstruction(Reg: TRegister; p1: tai): boolean;
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var
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i : Longint;
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begin
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result:=false;
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for i:=0 to taicpu(p1).ops-1 do
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if (taicpu(p1).oper[i]^.typ=top_reg) and (taicpu(p1).oper[i]^.reg=Reg) and (taicpu(p1).spilling_get_operation_type(i) in [operand_write,operand_readwrite]) then
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begin
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result:=true;
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exit;
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end;
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end;
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End.
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@ -559,7 +559,7 @@ unit cgcpu;
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current_asmdata.getjumplabel(l2);
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countreg:=getintregister(list,OS_8);
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a_load_reg_reg(list,size,OS_8,src,countreg);
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list.concat(taicpu.op_reg_const(A_CP,countreg,0));
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list.concat(taicpu.op_reg_const(A_CPI,countreg,0));
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a_jmp_flags(list,F_EQ,l2);
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cg.a_label(list,l1);
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case op of
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@ -677,7 +677,7 @@ unit cgcpu;
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end;
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OP_SUB:
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begin
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list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
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list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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for i:=2 to tcgsize2size[size] do
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@ -689,6 +689,20 @@ unit cgcpu;
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end;
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end;
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end;
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{OP_ADD:
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begin
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list.concat(taicpu.op_reg_const(A_SUBI,reg,(-a) and mask));
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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for i:=2 to tcgsize2size[size] do
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begin
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NextReg;
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mask:=mask shl 8;
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inc(shift,8);
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list.concat(taicpu.op_reg_const(A_ADC,reg,(a and mask) shr shift));
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end;
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end;
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end; }
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else
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begin
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if size in [OS_64,OS_S64] then
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@ -787,11 +801,11 @@ unit cgcpu;
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else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
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begin
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maybegetcpuregister(list,tmpreg);
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emit_mov(list,tmpreg,ref.index);
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emit_mov(list,tmpreg,ref.base);
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maybegetcpuregister(list,GetNextReg(tmpreg));
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emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
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list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
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list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
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emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
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list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
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list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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end
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@ -1329,13 +1343,13 @@ unit cgcpu;
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reg1:=reg2;
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reg2:=tmpreg;
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end;
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list.concat(taicpu.op_reg_reg(A_CP,reg1,reg2));
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list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
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|
||||
for i:=2 to tcgsize2size[size] do
|
||||
begin
|
||||
reg1:=GetNextReg(reg1);
|
||||
reg2:=GetNextReg(reg2);
|
||||
list.concat(taicpu.op_reg_reg(A_CPC,reg1,reg2));
|
||||
list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
|
||||
end;
|
||||
|
||||
a_jmp_cond(list,cmp_op,l);
|
||||
@ -1513,6 +1527,8 @@ unit cgcpu;
|
||||
LocalSize:=current_procinfo.calc_stackframe_size;
|
||||
a_adjust_sp(list,LocalSize);
|
||||
regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
|
||||
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
||||
regs:=regs+[RS_R28,RS_R29];
|
||||
|
||||
for reg:=RS_R0 to RS_R31 do
|
||||
if reg in regs then
|
||||
|
||||
@ -235,11 +235,11 @@ unit cpubase;
|
||||
}
|
||||
NR_PIC_OFFSET_REG = NR_R9;
|
||||
{ Results are returned in this register (32-bit values) }
|
||||
NR_FUNCTION_RETURN_REG = NR_R0;
|
||||
RS_FUNCTION_RETURN_REG = RS_R0;
|
||||
NR_FUNCTION_RETURN_REG = NR_R24;
|
||||
RS_FUNCTION_RETURN_REG = RS_R24;
|
||||
{ Low part of 64bit return value }
|
||||
NR_FUNCTION_RETURN64_LOW_REG = NR_R0;
|
||||
RS_FUNCTION_RETURN64_LOW_REG = RS_R0;
|
||||
NR_FUNCTION_RETURN64_LOW_REG = NR_R22;
|
||||
RS_FUNCTION_RETURN64_LOW_REG = RS_R22;
|
||||
{ High part of 64bit return value }
|
||||
NR_FUNCTION_RETURN64_HIGH_REG = NR_R1;
|
||||
RS_FUNCTION_RETURN64_HIGH_REG = RS_R1;
|
||||
@ -323,6 +323,8 @@ unit cpubase;
|
||||
{ returns the register with the offset of ofs of a continuous set of register starting with r and being continued with rhi }
|
||||
function GetOffsetReg64(const r,rhi: TRegister;ofs : shortint): TRegister;
|
||||
|
||||
function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
|
||||
|
||||
implementation
|
||||
|
||||
uses
|
||||
@ -476,4 +478,10 @@ unit cpubase;
|
||||
end;
|
||||
|
||||
|
||||
function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
|
||||
begin
|
||||
is_calljmp:= o in jmp_instructions;
|
||||
end;
|
||||
|
||||
|
||||
end.
|
||||
|
||||
@ -162,7 +162,10 @@ unit cpupara;
|
||||
result:=not(def.size in [1,2,4]);
|
||||
}
|
||||
else
|
||||
result:=inherited ret_in_param(def,pd);
|
||||
if (def.size > 4) then
|
||||
result:=true
|
||||
else
|
||||
result:=inherited ret_in_param(def,pd);
|
||||
end;
|
||||
end;
|
||||
|
||||
@ -441,7 +444,57 @@ unit cpupara;
|
||||
{ Return in register }
|
||||
else
|
||||
begin
|
||||
if retcgsize in [OS_64,OS_S64] then
|
||||
case retcgsize of
|
||||
OS_32,OS_S32:
|
||||
begin
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R22;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
|
||||
paraloc:=result.add_location;
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R23;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
|
||||
paraloc:=result.add_location;
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R24;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
|
||||
paraloc:=result.add_location;
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R25;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
end;
|
||||
OS_16,OS_S16:
|
||||
begin
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R24;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
|
||||
paraloc:=result.add_location;
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R25;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
end;
|
||||
OS_8,OS_S8:
|
||||
begin
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_R24;
|
||||
paraloc^.size:=OS_8;
|
||||
paraloc^.def:=u8inttype;
|
||||
end;
|
||||
else
|
||||
internalerror(2014030101);
|
||||
end;
|
||||
|
||||
{if retcgsize in [OS_64,OS_S64] then
|
||||
begin
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_FUNCTION_RESULT64_LOW_REG;
|
||||
@ -457,9 +510,9 @@ unit cpupara;
|
||||
begin
|
||||
paraloc^.loc:=LOC_REGISTER;
|
||||
paraloc^.register:=NR_FUNCTION_RETURN_REG;
|
||||
paraloc^.size:=OS_32;
|
||||
paraloc^.def:=u32inttype;
|
||||
end;
|
||||
paraloc^.size:=OS_INT;
|
||||
paraloc^.def:=u16inttype;
|
||||
end;}
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
@ -69,14 +69,20 @@ Unit raavrgas;
|
||||
name : string[2];
|
||||
reg : tregister;
|
||||
end;
|
||||
{
|
||||
|
||||
const
|
||||
extraregs : array[0..19] of treg2str = (
|
||||
(name: 'X'; reg : NR_Z),
|
||||
(name: 'Y'; reg : NR_R1),
|
||||
(name: 'Z'; reg : NR_R2),
|
||||
extraregs : array[0..8] of treg2str = (
|
||||
(name: 'X'; reg : NR_R26),
|
||||
(name: 'XL'; reg : NR_R26),
|
||||
(name: 'XH'; reg : NR_R27),
|
||||
(name: 'Y'; reg : NR_R28),
|
||||
(name: 'YL'; reg : NR_R28),
|
||||
(name: 'YH'; reg : NR_R29),
|
||||
(name: 'Z'; reg : NR_R30),
|
||||
(name: 'ZL'; reg : NR_R30),
|
||||
(name: 'ZH'; reg : NR_R31)
|
||||
);
|
||||
}
|
||||
|
||||
var
|
||||
i : longint;
|
||||
|
||||
@ -85,9 +91,9 @@ Unit raavrgas;
|
||||
{ reg found?
|
||||
possible aliases are always 2 char
|
||||
}
|
||||
if result or (length(s)<>2) then
|
||||
if result or (not (length(s) in [1,2])) then
|
||||
exit;
|
||||
{
|
||||
|
||||
for i:=low(extraregs) to high(extraregs) do
|
||||
begin
|
||||
if s=extraregs[i].name then
|
||||
@ -98,7 +104,6 @@ Unit raavrgas;
|
||||
exit;
|
||||
end;
|
||||
end;
|
||||
}
|
||||
end;
|
||||
|
||||
|
||||
@ -480,7 +485,16 @@ Unit raavrgas;
|
||||
{ save the type of register used. }
|
||||
tempreg:=actasmregister;
|
||||
Consume(AS_REGISTER);
|
||||
if (actasmtoken in [AS_END,AS_SEPARATOR,AS_COMMA]) then
|
||||
if (actasmtoken=AS_PLUS) then
|
||||
begin
|
||||
oper.opr.typ:=OPR_REFERENCE;
|
||||
|
||||
reference_reset_base(oper.opr.ref,tempreg,0,1);
|
||||
oper.opr.ref.addressmode:=AM_POSTINCREMENT;
|
||||
|
||||
consume(AS_PLUS);
|
||||
end
|
||||
else if (actasmtoken in [AS_END,AS_SEPARATOR,AS_COMMA]) then
|
||||
Begin
|
||||
if not (oper.opr.typ in [OPR_NONE,OPR_REGISTER]) then
|
||||
Message(asmr_e_invalid_operand_type);
|
||||
|
||||
@ -635,8 +635,7 @@ begin
|
||||
Add(' /* Internal text space or external memory. */');
|
||||
Add(' .text :');
|
||||
Add(' {');
|
||||
Add(' *(.vectors)');
|
||||
Add(' KEEP(*(.vectors))');
|
||||
Add(' KEEP(*(.init, .init.*))');
|
||||
Add(' /* For data that needs to reside in the lower 64k of progmem. */');
|
||||
Add(' *(.progmem.gcc*)');
|
||||
Add(' *(.progmem*)');
|
||||
@ -862,6 +861,10 @@ begin
|
||||
success:=DoExec(FindUtil(utilsprefix+'objcopy'),'-O ihex '+
|
||||
ChangeFileExt(current_module.exefilename,'.elf')+' '+
|
||||
ChangeFileExt(current_module.exefilename,'.hex'),true,false);
|
||||
if success then
|
||||
success:=DoExec(FindUtil(utilsprefix+'objcopy'),'-O binary '+
|
||||
ChangeFileExt(current_module.exefilename,'.elf')+' '+
|
||||
ChangeFileExt(current_module.exefilename,'.bin'),true,false);
|
||||
end;
|
||||
|
||||
MakeExecutable:=success; { otherwise a recursive call to link method }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user