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* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.

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* Change register type of second operand in CTC1 and CFC1 instructions to R_SPECIALREGISTER, so it is not output using a symbolic name. Mantis #26380.

git-svn-id: trunk@28034 -
This commit is contained in:
sergei 2014-06-22 22:01:44 +00:00
parent 95449a3fd4
commit e367ccc0ee
4 changed files with 32 additions and 25 deletions
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19
compiler/mips/mipsreg.dat
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@ -72,12 +72,15 @@ F29,$02,$06,$1D,f29,$f29,61,61
F30,$02,$06,$1E,f30,$f30,62,62
F31,$02,$06,$1F,f31,$f31,63,63
; Range 0..31 of R_SPECIALREGISTER is used without symbolic names
; and actual register they refer to depends on instruction.
; mips4+ floating-point condition code registers (1-bit)
FCC0,$05,$00,$00,fcc0,$fcc0,-1,-1
FCC1,$05,$00,$01,fcc1,$fcc1,-1,-1
FCC2,$05,$00,$02,fcc2,$fcc2,-1,-1
FCC3,$05,$00,$03,fcc3,$fcc3,-1,-1
FCC4,$05,$00,$04,fcc4,$fcc4,-1,-1
FCC5,$05,$00,$05,fcc5,$fcc5,-1,-1
FCC6,$05,$00,$06,fcc6,$fcc6,-1,-1
FCC7,$05,$00,$07,fcc7,$fcc7,-1,-1
FCC0,$05,$00,$20,fcc0,$fcc0,-1,-1
FCC1,$05,$00,$21,fcc1,$fcc1,-1,-1
FCC2,$05,$00,$22,fcc2,$fcc2,-1,-1
FCC3,$05,$00,$23,fcc3,$fcc3,-1,-1
FCC4,$05,$00,$24,fcc4,$fcc4,-1,-1
FCC5,$05,$00,$25,fcc5,$fcc5,-1,-1
FCC6,$05,$00,$26,fcc6,$fcc6,-1,-1
FCC7,$05,$00,$27,fcc7,$fcc7,-1,-1

6
compiler/mips/racpugas.pas
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@ -566,8 +566,12 @@ Interface
condition := actcondition;
if is_calljmp(opcode) then
ConvertCalljmp(instr);
if (opcode in [A_MTC0,A_MFC0]) then
{ Coprocessor-related instructions have operands referring to both coprocessor registers
and general-purpose ones. The input representation "$<number>" is the same for both,
but symbolic names must not be used for non-GPRs on output. }
if (opcode in [A_MTC0,A_MFC0,A_CFC1,A_CTC1{,A_CFC2,A_CTC2}]) then
begin
{ operands are 1-based here }
if (ops<2) or (operands[2].opr.typ<>OPR_REGISTER) then
message(asmr_e_syn_operand);
operands[2].opr.reg:=newreg(R_SPECIALREGISTER,getsupreg(operands[2].opr.reg),R_SUBNONE);

16
compiler/mips/rmipscon.inc
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@ -64,11 +64,11 @@ NR_F28 = tregister($0206001C);
NR_F29 = tregister($0206001D);
NR_F30 = tregister($0206001E);
NR_F31 = tregister($0206001F);
NR_FCC0 = tregister($05000000);
NR_FCC1 = tregister($05000001);
NR_FCC2 = tregister($05000002);
NR_FCC3 = tregister($05000003);
NR_FCC4 = tregister($05000004);
NR_FCC5 = tregister($05000005);
NR_FCC6 = tregister($05000006);
NR_FCC7 = tregister($05000007);
NR_FCC0 = tregister($05000020);
NR_FCC1 = tregister($05000021);
NR_FCC2 = tregister($05000022);
NR_FCC3 = tregister($05000023);
NR_FCC4 = tregister($05000024);
NR_FCC5 = tregister($05000025);
NR_FCC6 = tregister($05000026);
NR_FCC7 = tregister($05000027);

16
compiler/mips/rmipssup.inc
View File

@ -64,11 +64,11 @@ RS_F28 = $1C;
RS_F29 = $1D;
RS_F30 = $1E;
RS_F31 = $1F;
RS_FCC0 = $00;
RS_FCC1 = $01;
RS_FCC2 = $02;
RS_FCC3 = $03;
RS_FCC4 = $04;
RS_FCC5 = $05;
RS_FCC6 = $06;
RS_FCC7 = $07;
RS_FCC0 = $20;
RS_FCC1 = $21;
RS_FCC2 = $22;
RS_FCC3 = $23;
RS_FCC4 = $24;
RS_FCC5 = $25;
RS_FCC6 = $26;
RS_FCC7 = $27;