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* results of work on arm port last weekend

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This commit is contained in:
florian 2003-09-01 09:54:57 +00:00
parent 301df6dab9
commit e36c23db74
3 changed files with 285 additions and 181 deletions
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155
compiler/arm/cgcpu.pas
View File

@ -95,12 +95,6 @@ unit cgcpu;
procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister; procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
ref: treference); ref: treference);
{ creates the correct branch instruction for a given combination }
{ of asmcondflags and destination addressing mode }
procedure a_jmp(list: taasmoutput; op: tasmop;
c: tasmcond; l: tasmlabel);
end; end;
tcg64farm = class(tcg64f32) tcg64farm = class(tcg64f32)
@ -119,10 +113,12 @@ unit cgcpu;
A_DIVWU,A_DIVW, A_MULLW,A_MULLW,A_NONE,A_NONE, A_DIVWU,A_DIVW, A_MULLW,A_MULLW,A_NONE,A_NONE,
A_ORIS,A_NONE, A_NONE,A_NONE,A_SUBIS,A_XORIS); A_ORIS,A_NONE, A_NONE,A_NONE,A_SUBIS,A_XORIS);
TOpCmp2AsmCond: Array[topcmp] of TAsmCondFlag = (C_NONE,C_EQ,C_GT,
C_LT,C_GE,C_LE,C_NE,C_LE,C_LT,C_GE,C_GT);
} }
const
OpCmp2AsmCond : Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_GT,
C_LT,C_GE,C_LE,C_NE,C_LE,C_LT,C_GE,C_GT);
function is_shifter_const(d : dword;var imm_shift : byte) : boolean; function is_shifter_const(d : dword;var imm_shift : byte) : boolean;
implementation implementation
@ -251,8 +247,15 @@ unit cgcpu;
procedure tcgarm.a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister); procedure tcgarm.a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister);
begin begin
case op of
OP_NEG:
list.concat(taicpu.op_reg_reg_const(A_RSB,dst,src,0));
OP_NOT:
list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
else
a_op_reg_reg_reg(list,op,OS_32,src,dst,dst); a_op_reg_reg_reg(list,op,OS_32,src,dst,dst);
end; end;
end;
const const
@ -303,6 +306,15 @@ unit cgcpu;
else else
list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a)); list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a));
end end
else
begin
{ there could be added some more sophisticated optimizations }
if (op in [OP_MUL,OP_IMUL]) and (a=1) then
a_load_reg_reg(list,size,size,src,dst)
else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
a_load_const_reg(list,size,0,dst)
else if (op in [OP_IMUL]) and (a=-1) then
a_op_reg_reg(list,OP_NEG,size,src,dst)
else else
begin begin
tmpreg := rg.getregisterint(list,size); tmpreg := rg.getregisterint(list,size);
@ -311,6 +323,7 @@ unit cgcpu;
rg.ungetregisterint(list,tmpreg); rg.ungetregisterint(list,tmpreg);
end; end;
end; end;
end;
procedure tcgarm.a_op_reg_reg_reg(list: taasmoutput; op: TOpCg; procedure tcgarm.a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
@ -320,32 +333,29 @@ unit cgcpu;
tmpreg : tregister; tmpreg : tregister;
begin begin
case op of case op of
OP_NEG: OP_NEG,OP_NOT,
list.concat(taicpu.op_reg_reg(op_reg_reg_opcg2asmop[op],dst,dst));
OP_NOT:
list.concat(taicpu.op_reg_reg(A_MVN,dst,dst));
OP_DIV,OP_IDIV: OP_DIV,OP_IDIV:
internalerror(200308281); internalerror(200308281);
OP_SHL: OP_SHL:
begin begin
shifterop_reset(so); shifterop_reset(so);
so.rs:=src2; so.rs:=src1;
so.shiftertype:=SO_LSL; so.shiftertype:=SO_LSL;
list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src1,so)); list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
end; end;
OP_SHR: OP_SHR:
begin begin
shifterop_reset(so); shifterop_reset(so);
so.rs:=src2; so.rs:=src1;
so.shiftertype:=SO_LSR; so.shiftertype:=SO_LSR;
list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src1,so)); list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
end; end;
OP_SAR: OP_SAR:
begin begin
shifterop_reset(so); shifterop_reset(so);
so.rs:=src2; so.rs:=src1;
so.shiftertype:=SO_LSL; so.shiftertype:=SO_ASR;
list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src1,so)); list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
end; end;
OP_IMUL, OP_IMUL,
OP_MUL: OP_MUL:
@ -522,7 +532,7 @@ unit cgcpu;
var var
oppostfix:toppostfix; oppostfix:toppostfix;
begin begin
case ToSize of case FromSize of
{ signed integer registers } { signed integer registers }
OS_8: OS_8:
oppostfix:=PF_B; oppostfix:=PF_B;
@ -603,6 +613,7 @@ unit cgcpu;
procedure tcgarm.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister); procedure tcgarm.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister);
begin begin
list.concat(taicpu.op_reg_reg(A_MVF,reg2,reg1));
end; end;
@ -619,12 +630,36 @@ unit cgcpu;
{ comparison operations } { comparison operations }
procedure tcgarm.a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aword;reg : tregister; procedure tcgarm.a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aword;reg : tregister;
l : tasmlabel); l : tasmlabel);
var
tmpreg : tregister;
b : byte;
begin begin
if reg.enum=R_INTREGISTER then
begin
if is_shifter_const(a,b) then
list.concat(taicpu.op_reg_const(A_CMN,reg,a))
{ CMN reg,0 and CMN reg,$80000000 are different from CMP reg,$ffffffff
and CMP reg,$7fffffff regarding the flags according to the ARM manual }
else if is_shifter_const(not(a),b) and (a<>$7fffffff) and (a<>$ffffffff) then
list.concat(taicpu.op_reg_const(A_CMN,reg,not(a)))
else
begin
tmpreg:=rg.getregisterint(list,size);
a_load_const_reg(list,size,a,tmpreg);
list.concat(taicpu.op_reg_reg(A_CMP,reg,tmpreg));
rg.ungetregisterint(list,tmpreg);
end
end
else
internalerror(200308131);
a_jmp_cond(list,cmp_op,l);
end; end;
procedure tcgarm.a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); procedure tcgarm.a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
begin begin
list.concat(taicpu.op_reg_reg(A_CMP,reg2,reg1));
a_jmp_cond(list,cmp_op,l);
end; end;
@ -646,7 +681,15 @@ unit cgcpu;
procedure tcgarm.g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister); procedure tcgarm.g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister);
var
ai : taicpu;
begin begin
ai:=Taicpu.op_reg_const(A_MOV,reg,1);
ai.setcondition(flags_to_cond(f));
list.concat(ai);
ai:=Taicpu.op_reg_const(A_MOV,reg,0);
ai.setcondition(inverse_cond[flags_to_cond(f)]);
list.concat(ai);
end; end;
@ -660,6 +703,8 @@ unit cgcpu;
rip,rsp,rfp : tregister; rip,rsp,rfp : tregister;
instr : taicpu; instr : taicpu;
begin begin
LocalSize:=align(LocalSize,4);
rsp.enum:=R_INTREGISTER; rsp.enum:=R_INTREGISTER;
rsp.number:=NR_STACK_POINTER_REG; rsp.number:=NR_STACK_POINTER_REG;
a_reg_alloc(list,rsp); a_reg_alloc(list,rsp);
@ -674,7 +719,7 @@ unit cgcpu;
list.concat(taicpu.op_reg_reg(A_MOV,rip,rsp)); list.concat(taicpu.op_reg_reg(A_MOV,rip,rsp));
{ restore int registers and return } { restore int registers and return }
instr:=taicpu.op_reg_regset(A_STM,rsp,rg.used_in_proc_int-[RS_R0..RS_R4]+[RS_R11,RS_R12,RS_R15]); instr:=taicpu.op_reg_regset(A_STM,rsp,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R12,RS_R15]);
instr.oppostfix:=PF_FD; instr.oppostfix:=PF_FD;
list.concat(instr); list.concat(instr);
@ -682,7 +727,7 @@ unit cgcpu;
a_reg_alloc(list,rip); a_reg_alloc(list,rip);
{ allocate necessary stack size } { allocate necessary stack size }
list.concat(taicpu.op_reg_reg_const(A_SUB,rsp,rsp,4)); list.concat(taicpu.op_reg_reg_const(A_SUB,rsp,rsp,LocalSize));
end; end;
@ -705,7 +750,7 @@ unit cgcpu;
r1.enum:=R_INTREGISTER; r1.enum:=R_INTREGISTER;
r1.number:=NR_R11; r1.number:=NR_R11;
{ restore int registers and return } { restore int registers and return }
instr:=taicpu.op_reg_regset(A_LDM,r1,rg.used_in_proc_int-[RS_R0..RS_R4]+[RS_R11,RS_R13,RS_R15]); instr:=taicpu.op_reg_regset(A_LDM,r1,rg.used_in_proc_int-[RS_R0..RS_R3]+[RS_R11,RS_R13,RS_R15]);
instr.oppostfix:=PF_EA; instr.oppostfix:=PF_EA;
list.concat(instr); list.concat(instr);
end; end;
@ -714,6 +759,7 @@ unit cgcpu;
procedure tcgarm.g_restore_frame_pointer(list : taasmoutput); procedure tcgarm.g_restore_frame_pointer(list : taasmoutput);
begin begin
{ the frame pointer on the ARM is restored while the ret is executed }
end; end;
@ -734,26 +780,36 @@ unit cgcpu;
procedure tcgarm.g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset); procedure tcgarm.g_save_standard_registers(list : taasmoutput; usedinproc : Tsupregset);
begin begin
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
end; end;
procedure tcgarm.g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset); procedure tcgarm.g_restore_standard_registers(list : taasmoutput; usedinproc : Tsupregset);
begin begin
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
end; end;
procedure tcgarm.g_save_all_registers(list : taasmoutput); procedure tcgarm.g_save_all_registers(list : taasmoutput);
begin begin
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
end; end;
procedure tcgarm.g_restore_all_registers(list : taasmoutput;accused,acchiused:boolean); procedure tcgarm.g_restore_all_registers(list : taasmoutput;accused,acchiused:boolean);
begin begin
{ we support only ARM standard calling conventions so this procedure has no use on the ARM }
end; end;
procedure tcgarm.a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel); procedure tcgarm.a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
var
ai : taicpu;
begin begin
ai:=Taicpu.Op_sym(A_B,l);
ai.SetCondition(OpCmp2AsmCond[cond]);
ai.is_jmp:=true;
list.concat(ai);
end; end;
@ -764,21 +820,28 @@ unit cgcpu;
end; end;
{ creates the correct branch instruction for a given combination }
{ of asmcondflags and destination addressing mode }
procedure tcgarm.a_jmp(list: taasmoutput; op: tasmop;
c: tasmcond; l: tasmlabel);
begin
end;
procedure tcg64farm.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64); procedure tcg64farm.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
var
tmpreg : tregister;
instr : taicpu;
begin begin
case op of
OP_NEG:
begin
instr:=taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0);
instr.oppostfix:=PF_S;
list.concat(instr);
list.concat(taicpu.op_reg_reg_const(A_RSC,regdst.reghi,regsrc.reghi,0));
end;
else
a_op64_reg_reg_reg(list,op,regsrc,regdst,regdst);
end;
end; end;
procedure tcg64farm.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64); procedure tcg64farm.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);
begin begin
a_op64_const_reg_reg(list,op,value,reg,reg);
end; end;
@ -788,7 +851,32 @@ unit cgcpu;
procedure tcg64farm.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64); procedure tcg64farm.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);
var
instr : taicpu;
begin begin
case op of
OP_AND,OP_OR,OP_XOR:
begin
cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
end;
OP_ADD:
begin
instr:=taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo);
instr.oppostfix:=PF_S;
list.concat(instr);
list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
end;
OP_SUB:
begin
instr:=taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo);
instr.oppostfix:=PF_S;
list.concat(instr);
list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi));
end;
else
internalerror(2003083101);
end;
end; end;
@ -798,7 +886,10 @@ begin
end. end.
{ {
$Log$ $Log$
Revision 1.8 2003-08-29 21:36:28 florian Revision 1.9 2003-09-01 09:54:57 florian
* results of work on arm port last weekend
Revision 1.8 2003/08/29 21:36:28 florian
* fixed procedure entry/exit code * fixed procedure entry/exit code
* started to fix reference handling * started to fix reference handling

18
compiler/arm/narmadd.pas
View File

@ -128,22 +128,21 @@ interface
fpu_fpa10, fpu_fpa10,
fpu_fpa11: fpu_fpa11:
begin begin
{ we will see what instruction set we'll use on the arm for FP
pass_left_right; pass_left_right;
if (nf_swaped in flags) then if (nf_swaped in flags) then
swapleftright; swapleftright;
case nodetype of case nodetype of
addn : addn :
op:=A_FADDs; op:=A_ADF;
muln : muln :
op:=A_FMULs; op:=A_MUF;
subn : subn :
op:=A_FSUBs; op:=A_SUF;
slashn : slashn :
op:=A_FDIVs; op:=A_FDV;
else else
internalerror(200306014); internalerror(200308313);
end; end;
{ force fpureg as location, left right doesn't matter { force fpureg as location, left right doesn't matter
@ -161,7 +160,7 @@ interface
left.location.register,right.location.register,location.register)); left.location.register,right.location.register,location.register));
release_reg_left_right; release_reg_left_right;
}
location.loc:=LOC_FPUREGISTER; location.loc:=LOC_FPUREGISTER;
end; end;
fpu_soft: fpu_soft:
@ -279,7 +278,10 @@ begin
end. end.
{ {
$Log$ $Log$
Revision 1.2 2003-08-25 23:20:38 florian Revision 1.3 2003-09-01 09:54:57 florian
* results of work on arm port last weekend
Revision 1.2 2003/08/25 23:20:38 florian
+ started to implement FPU support for the ARM + started to implement FPU support for the ARM
* fixed a lot of other things * fixed a lot of other things

13
compiler/arm/narmcnv.pas
View File

@ -107,7 +107,15 @@ implementation
procedure tarmtypeconvnode.second_int_to_real; procedure tarmtypeconvnode.second_int_to_real;
var
instr : taicpu;
begin begin
location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
location_force_reg(exprasmlist,left.location,OS_32,true);
location.register:=rg.getregisterfpu(exprasmlist,location.size);
instr:=taicpu.op_reg_reg(A_FLT,location.register,left.location.register);
{ set precision? }
exprasmlist.concat(instr);
end; end;
@ -176,7 +184,10 @@ begin
end. end.
{ {
$Log$ $Log$
Revision 1.2 2003-08-25 23:20:38 florian Revision 1.3 2003-09-01 09:54:57 florian
* results of work on arm port last weekend
Revision 1.2 2003/08/25 23:20:38 florian
+ started to implement FPU support for the ARM + started to implement FPU support for the ARM
* fixed a lot of other things * fixed a lot of other things