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* patch by Jeppe Johansen: The reset vector for stm32f103 didn't have the T bit set, so it will execute a hard fault handler instead of the reset code, which by default is the same, resolves #18630
git-svn-id: trunk@16847 -
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florian
parent
eab29db98a
commit
e39a220945
@ -17,29 +17,29 @@ type
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{$PACKRECORDS 2}
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const
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PeripheralBase = $40000000;
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FSMCBase = $60000000;
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APB1Base = PeripheralBase;
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APB2Base = PeripheralBase+$10000;
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AHBBase = PeripheralBase+$20000;
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SCS_BASE = $E000E000;
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{ FSMC }
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FSMCBank1NOR1 = FSMCBase+$00000000;
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FSMCBank1NOR2 = FSMCBase+$04000000;
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FSMCBank1NOR3 = FSMCBase+$08000000;
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FSMCBank1NOR4 = FSMCBase+$0C000000;
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FSMCBank1PSRAM1 = FSMCBase+$00000000;
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FSMCBank1PSRAM2 = FSMCBase+$04000000;
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FSMCBank1PSRAM3 = FSMCBase+$08000000;
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FSMCBank1PSRAM4 = FSMCBase+$0C000000;
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FSMCBank2NAND1 = FSMCBase+$10000000;
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FSMCBank3NAND2 = FSMCBase+$20000000;
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FSMCBank4PCCARD = FSMCBase+$30000000;
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type
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@ -65,7 +65,7 @@ type
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DCR, res18,
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DMAR, res19: Word;
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end;
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TRTCRegisters = record
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CRH, res1,
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CRL, res2,
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@ -78,20 +78,20 @@ type
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ALRH, res9,
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ALRL, res10: Word;
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end;
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TIWDGRegisters = record
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KR, res1,
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PR, res2,
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RLR, res3,
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SR, res4: word;
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end;
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TWWDGRegisters = record
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CR, res2,
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CFR, res3,
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SR, res4: word;
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end;
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TSPIRegisters = record
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CR1, res1,
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CR2, res2,
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@ -103,7 +103,7 @@ type
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I2SCFGR, res8,
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I2SPR, res9: Word;
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end;
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TUSARTRegisters = record
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SR, res1,
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DR, res2,
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@ -113,7 +113,7 @@ type
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CR3, res6,
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GTPR, res7: Word;
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end;
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TI2CRegisters = record
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CR1, res1,
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CR2, res2,
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@ -125,28 +125,28 @@ type
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CCR, res8: word;
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TRISE: byte;
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end;
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TUSBRegisters = record
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EPR: array[0..7] of DWord;
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res: array[0..7] of dword;
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CNTR, res1,
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ISTR, res2,
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FNR, res3: Word;
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DADDR: byte; res4: word; res5: byte;
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BTABLE: Word;
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end;
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TUSBMem = packed array[0..511] of byte;
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TCANMailbox = record
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IR,
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DTR,
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DLR,
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DHR: DWord;
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end;
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TCANRegisters = record
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MCR,
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MSR,
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@ -156,14 +156,14 @@ type
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IER,
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ESR,
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BTR: DWord;
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res5: array[$020..$17F] of byte;
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TX: array[0..2] of TCANMailbox;
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RX: array[0..2] of TCANMailbox;
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res6: array[$1D0..$1FF] of byte;
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FMR,
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FM1R,
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res9: DWord;
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@ -173,55 +173,55 @@ type
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res13: DWord;
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FA1R, res14: word;
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res15: array[$220..$23F] of byte;
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FOR1,
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FOR2: DWord;
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FB: array[1..13] of array[1..2] of DWord;
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end;
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TBKPRegisters = record
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DR: array[1..10] of record data, res: word; end;
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RTCCR,
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CR,
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CSR,
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res1,res2: DWord;
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DR2: array[11..42] of record data, res: word; end;
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end;
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TPwrRegisters = record
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CR, res: word;
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CSR: Word;
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end;
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TDACRegisters = record
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CR,
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SWTRIGR: DWord;
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DHR12R1, res2,
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DHR12L1, res3,
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DHR8R1, res4,
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DHR12R2, res5,
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DHR12L2, res6,
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DHR8R2, res7: word;
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DHR12RD,
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DHR12LD: DWord;
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DHR8RD, res8,
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DOR1, res9,
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DOR2, res10: Word;
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end;
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TAFIORegisters = record
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EVCR,
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MAPR: DWord;
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EXTICR: array[0..3] of DWord;
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end;
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TEXTIRegisters = record
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IMR,
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EMR,
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@ -230,7 +230,7 @@ type
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SWIER,
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PR: DWord;
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end;
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TPortRegisters = record
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CRL,
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CRH,
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@ -240,7 +240,7 @@ type
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BRR,
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LCKR: DWord;
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end;
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TADCRegisters = record
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SR,
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CR1,
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@ -263,7 +263,7 @@ type
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JDR4, res11: Word;
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DR: DWord;
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end;
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TSDIORegisters = record
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POWER,
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CLKCR,
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@ -284,7 +284,7 @@ type
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FIFOCNT,
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FIFO: DWord;
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end;
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TDMAChannel = record
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CCR, res1,
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CNDTR, res2: word;
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@ -292,13 +292,13 @@ type
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CMAR,
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res: DWord;
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end;
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TDMARegisters = record
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ISR,
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IFCR: DWord;
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Channel: array[0..7] of TDMAChannel;
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end;
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TRCCRegisters = record
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CR,
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CFGR,
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@ -311,17 +311,17 @@ type
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BDCR,
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CSR: DWord;
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end;
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TCRCRegisters = record
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DR: DWord;
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IDR: byte; res1: word; res2: byte;
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CR: byte;
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end;
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TFSMCRegisters = record
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nothingyet: byte;
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end;
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TFlashRegisters = record
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ACR,
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KEYR,
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@ -333,7 +333,7 @@ type
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OBR,
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WRPR: DWord;
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end;
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TNVICRegisters = packed record
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ISER: array[0..7] of longword;
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reserved0: array[0..23] of longword;
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@ -349,7 +349,7 @@ type
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reserved5: array[0..643] of longword;
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STIR: longword;
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end;
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TSCBRegisters = packed record
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CPUID, {!< CPU ID Base Register }
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ICSR, {!< Interrupt Control State Register }
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@ -371,7 +371,7 @@ type
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MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
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ISAR: array[0..4] of longword; {!< ISA Feature Register }
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end;
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TSysTickRegisters = packed record
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Ctrl,
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Load,
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@ -390,50 +390,50 @@ var
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Timer6: TTimerRegisters absolute (APB1Base+$1000);
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Timer7: TTimerRegisters absolute (APB1Base+$1400);
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Timer8: TTimerRegisters absolute (APB2Base+$3400);
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{ RTC }
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RTC: TRTCRegisters absolute (APB1Base+$2800);
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{ WDG }
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WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
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IWDG: TIWDGRegisters absolute (APB1Base+$3000);
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{ SPI }
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SPI1: TSPIRegisters absolute (APB2Base+$3000);
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SPI2: TSPIRegisters absolute (APB1Base+$3800);
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SPI3: TSPIRegisters absolute (APB1Base+$3C00);
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{ USART/UART }
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USART1: TUSARTRegisters absolute (APB2Base+$3800);
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USART2: TUSARTRegisters absolute (APB1Base+$4400);
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USART3: TUSARTRegisters absolute (APB1Base+$4800);
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UART4: TUSARTRegisters absolute (APB1Base+$4C00);
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UART5: TUSARTRegisters absolute (APB1Base+$5000);
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{ I2C }
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I2C1: TI2CRegisters absolute (APB1Base+$5400);
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I2C2: TI2CRegisters absolute (APB1Base+$5800);
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{ USB }
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USB: TUSBRegisters absolute (APB1Base+$5C00);
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USBMem: TUSBMem absolute (APB1Base+$5C00);
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{ CAN }
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CAN: TCANRegisters absolute (APB1Base+$6800);
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{ BKP }
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BKP: TBKPRegisters absolute (APB1Base+$6C00);
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{ PWR }
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PWR: TPwrRegisters absolute (APB1Base+$7000);
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{ DAC }
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DAC: TDACRegisters absolute (APB1Base+$7400);
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{ GPIO }
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AFIO: TAFIORegisters absolute (APB2Base+$0);
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EXTI: TEXTIRegisters absolute (APB2Base+$0400);
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PortA: TPortRegisters absolute (APB2Base+$0800);
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PortB: TPortRegisters absolute (APB2Base+$0C00);
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PortC: TPortRegisters absolute (APB2Base+$1000);
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@ -441,34 +441,34 @@ var
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PortE: TPortRegisters absolute (APB2Base+$1800);
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PortF: TPortRegisters absolute (APB2Base+$1C00);
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PortG: TPortRegisters absolute (APB2Base+$2000);
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{ ADC }
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ADC1: TADCRegisters absolute (APB2Base+$2400);
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ADC2: TADCRegisters absolute (APB2Base+$2800);
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ADC3: TADCRegisters absolute (APB2Base+$3C00);
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{ SDIO }
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SDIO: TSDIORegisters absolute (APB2Base+$8000);
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{ DMA }
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DMA1: TDMARegisters absolute (AHBBase+$0000);
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DMA2: TDMARegisters absolute (AHBBase+$0400);
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{ RCC }
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RCC: TRCCRegisters absolute (AHBBase+$1000);
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{ Flash }
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Flash: TFlashRegisters absolute (AHBBase+$2000);
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{ CRC }
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CRC: TCRCRegisters absolute (AHBBase+$3000);
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{ SCB }
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SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
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{ SysTick }
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SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
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{ NVIC }
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NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
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@ -508,7 +508,7 @@ asm
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.balign 16
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.long _stack_top // First entry in NVIC table is the new stack pointer
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.long _start
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.long _start+1
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//b _start // Reset
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.long _start+1
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//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
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@ -632,7 +632,7 @@ asm
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.L8:
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.long PendingSV_Handler
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.L9:
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.long Systick_Handler
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.long Systick_Handler
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.globl _start
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.text
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