From e43834c5d02abe95d93151fc2a97c56ee918d46d Mon Sep 17 00:00:00 2001
From: nickysn <nickysn@gmail.com>
Date: Fri, 3 Apr 2020 22:19:40 +0000
Subject: [PATCH] * replace 'inc/dec orgreg' with 'inc/dec spilltemp' in
 trgcpu.do_spill_replace

git-svn-id: branches/z80@44552 -
---
 compiler/z80/rgcpu.pas | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/compiler/z80/rgcpu.pas b/compiler/z80/rgcpu.pas
index 40ad24a01a..abbb71f5fa 100644
--- a/compiler/z80/rgcpu.pas
+++ b/compiler/z80/rgcpu.pas
@@ -216,6 +216,17 @@ unit rgcpu;
                     instr.loadref(1,spilltemp);
                     result:=true;
                   end;
+              end
+            { Replace 'inc orgreg' with 'inc spilltemp'
+              and     'dec orgreg' with 'dec spilltemp' }
+            else if (opcode in [A_INC,A_DEC]) and (ops=1) and (oper[0]^.typ=top_reg) then
+              begin
+                if (getregtype(oper[0]^.reg)=regtype) and
+                   (get_alias(getsupreg(oper[0]^.reg))=orgreg) then
+                  begin
+                    instr.loadref(0,spilltemp);
+                    result:=true;
+                  end;
               end;
           end;
       end;