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* RiscV: generate mret only for FreeRTOS and Embedded

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florian 2022-07-20 22:16:19 +02:00
parent 0e8d87bc26
commit e66378ee59
1 changed files with 1 additions and 1 deletions
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2
compiler/riscv/cgrv.pas
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@ -690,7 +690,7 @@ unit cgrv;
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,postcompensation)); list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,postcompensation));
end; end;
if po_interrupt in current_procinfo.procdef.procoptions then if (target_info.system in (systems_freertos+systems_embedded)) and (po_interrupt in current_procinfo.procdef.procoptions) then
begin begin
list.concat(Taicpu.Op_none(A_MRET)); list.concat(Taicpu.Op_none(A_MRET));
end end