From e6b89c98f526394b5b7fbc197a551ab3e8229c2d Mon Sep 17 00:00:00 2001 From: yury Date: Sat, 25 Jul 2020 18:29:59 +0000 Subject: [PATCH] * Changed tsuperregisterworklist.get() to always return the last item from the list. * Reversed sort order of simplifyworklist so nodes with most interferences will get their colors first. Since degree of nodes in simplifyworklist before sorting is always less than the number of usable registers this should not trigger spilling and should lead to a better register allocation in some cases. After these changes sysutils.o for i386-win32 is 80 bytes less. :) git-svn-id: trunk@45857 - --- compiler/cgbase.pas | 4 ++-- compiler/rgobj.pas | 16 +++++++++++++--- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/compiler/cgbase.pas b/compiler/cgbase.pas index c464d762a5..6dca71ba40 100644 --- a/compiler/cgbase.pas +++ b/compiler/cgbase.pas @@ -343,6 +343,7 @@ interface procedure clear; procedure add(s:tsuperregister); function addnodup(s:tsuperregister): boolean; + { returns the last element and removes it from the list } function get:tsuperregister; function readidx(i:word):tsuperregister; procedure deleteidx(i:word); @@ -590,9 +591,8 @@ implementation begin if length=0 then internalerror(200310142); - get:=buf^[0]; - buf^[0]:=buf^[length-1]; dec(length); + get:=buf^[length]; end; diff --git a/compiler/rgobj.pas b/compiler/rgobj.pas index ab1ba5b008..84eaf2d60b 100644 --- a/compiler/rgobj.pas +++ b/compiler/rgobj.pas @@ -929,7 +929,17 @@ unit rgobj; {Sorts the simplifyworklist by the number of interferences the registers in it cause. This allows simplify to execute in - constant time.} + constant time. + + Sort the list in the descending order, since items of simplifyworklist + are retrieved from end to start and then items are added to selectstack. + The selectstack list is also processed from end to start. + + Such way nodes with most interferences will get their colors first. + Since degree of nodes in simplifyworklist before sorting is always + less than the number of usable registers this should not trigger spilling + and should lead to a better register allocation in some cases. + } var p,h,i,leni,lent:longword; t:Tsuperregister; @@ -958,7 +968,7 @@ unit rgobj; leni:=0; if adji<>nil then leni:=adji^.length; - if leni<=lent then + if leni>=lent then break; buf^[i]:=buf^[i-p]; dec(i,p) @@ -1018,7 +1028,7 @@ unit rgobj; var n:cardinal; begin - {If we have 7 cpu registers, and the degree of a node is 7, we cannot + {If we have 7 cpu registers, and the degree of a node >= 7, we cannot assign it to any of the registers, thus it is significant.} for n:=first_imaginary to maxreg-1 do with reginfo[n] do