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* x86: New MovShr/Sar2Movx optimisation
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
3963a30f9e
commit
e7218d09fb
@ -2761,7 +2761,7 @@ unit aoptx86;
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var
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GetNextInstruction_p, TempRegUsed, CrossJump: Boolean;
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PreMessage, RegName1, RegName2, InputVal, MaskNum: string;
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NewSize: topsize;
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NewSize: topsize; NewOffset: asizeint;
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p_SourceReg, p_TargetReg, NewMMReg: TRegister;
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SourceRef, TargetRef: TReference;
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MovAligned, MovUnaligned: TAsmOp;
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@ -4609,54 +4609,155 @@ unit aoptx86;
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exit;
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end;
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{$ifdef x86_64}
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{ Convert:
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movq x(ref),%reg64
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shrq y,%reg64
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To:
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movl x+4(ref),%reg32
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shrl y-32,%reg32 (Remove if y = 32)
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}
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if (taicpu(p).opsize = S_Q) and
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(taicpu(p).oper[0]^.typ = top_ref) and { Second operand will be a register }
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(taicpu(p).oper[0]^.ref^.offset <= $7FFFFFFB) and
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MatchInstruction(hp1, A_SHR, [taicpu(p).opsize]) and
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if (taicpu(p).oper[0]^.typ = top_ref) and { Second operand will be a register }
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MatchInstruction(hp1, A_SHR, A_SAR, [taicpu(p).opsize]) and
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MatchOpType(taicpu(hp1), top_const, top_reg) and
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(taicpu(hp1).oper[0]^.val >= 32) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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begin
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RegName1 := debug_regname(taicpu(hp1).oper[1]^.reg);
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PreMessage := 'movq ' + debug_operstr(taicpu(p).oper[0]^) + ',' + RegName1 + '; ' +
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'shrq $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + RegName1 + ' -> movl ';
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{ Convert to 32-bit }
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setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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taicpu(p).opsize := S_L;
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Inc(taicpu(p).oper[0]^.ref^.offset, 4);
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PreMessage := PreMessage + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg);
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if (taicpu(hp1).oper[0]^.val = 32) then
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{$ifdef x86_64}
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{ Convert:
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movq x(ref),%reg64
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shrq y,%reg64
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To:
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movl x+4(ref),%reg32
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shrl y-32,%reg32 (Remove if y = 32)
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}
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if (taicpu(p).opsize = S_Q) and
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(taicpu(hp1).opcode = A_SHR) and
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(taicpu(hp1).oper[0]^.val >= 32) then
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begin
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DebugMsg(SPeepholeOptimization + PreMessage + ' (MovShr2Mov)', p);
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RemoveInstruction(hp1);
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end
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else
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begin
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{ This will potentially open up more arithmetic operations since
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the peephole optimizer now has a big hint that only the lower
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32 bits are currently in use (and opcodes are smaller in size) }
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setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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taicpu(hp1).opsize := S_L;
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PreMessage := 'movq ' + debug_operstr(taicpu(p).oper[0]^) + ',' + RegName1 + '; ' +
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'shrq $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + RegName1 + ' -> movl ';
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Dec(taicpu(hp1).oper[0]^.val, 32);
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DebugMsg(SPeepholeOptimization + PreMessage +
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'; shrl $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (MovShr2MovShr)', p);
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{ Convert to 32-bit }
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setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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taicpu(p).opsize := S_L;
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Inc(taicpu(p).oper[0]^.ref^.offset, 4);
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PreMessage := PreMessage + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg);
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if (taicpu(hp1).oper[0]^.val = 32) then
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begin
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DebugMsg(SPeepholeOptimization + PreMessage + ' (MovShr2Mov)', p);
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RemoveInstruction(hp1);
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end
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else
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begin
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{ This will potentially open up more arithmetic operations since
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the peephole optimizer now has a big hint that only the lower
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32 bits are currently in use (and opcodes are smaller in size) }
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setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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taicpu(hp1).opsize := S_L;
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Dec(taicpu(hp1).oper[0]^.val, 32);
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DebugMsg(SPeepholeOptimization + PreMessage +
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'; shrl $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (MovShr2MovShr)', p);
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end;
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Result := True;
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Exit;
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end;
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Result := True;
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Exit;
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end;
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{$endif x86_64}
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{ Convert:
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movl x(ref),%reg
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shrl $24,%reg
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To:
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movzbl x+3(ref),%reg
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Do similar things for movl; shrl $16 -> movzwl and movw; shrw $8 -> movzbw
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Also accept sar instead of shr, but convert to movsx instead of movzx
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}
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if taicpu(hp1).opcode = A_SHR then
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MovUnaligned := A_MOVZX
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else
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MovUnaligned := A_MOVSX;
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NewSize := S_NO;
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NewOffset := 0;
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case taicpu(p).opsize of
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S_B:
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{ No valid combinations };
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S_W:
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if (taicpu(hp1).oper[0]^.val = 8) then
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begin
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NewSize := S_BW;
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NewOffset := 1;
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end;
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S_L:
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case taicpu(hp1).oper[0]^.val of
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16:
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begin
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NewSize := S_WL;
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NewOffset := 2;
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end;
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24:
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begin
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NewSize := S_BL;
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NewOffset := 3;
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end;
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else
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;
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end;
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{$ifdef x86_64}
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S_Q:
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case taicpu(hp1).oper[0]^.val of
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32:
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begin
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if taicpu(hp1).opcode = A_SAR then
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begin
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{ 32-bit to 64-bit is a distinct instruction }
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MovUnaligned := A_MOVSXD;
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NewSize := S_LQ;
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NewOffset := 4;
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end
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else
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{ Should have been handled by MovShr2Mov above }
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InternalError(2022081811);
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end;
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48:
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begin
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NewSize := S_WQ;
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NewOffset := 6;
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end;
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56:
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begin
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NewSize := S_BQ;
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NewOffset := 7;
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end;
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else
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;
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end;
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{$endif x86_64}
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else
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InternalError(2022081810);
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end;
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if (NewSize <> S_NO) and
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(taicpu(p).oper[0]^.ref^.offset <= $7FFFFFFF - NewOffset) then
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begin
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PreMessage := 'mov' + debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + RegName1 + '; ' +
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'shr' + debug_opsize2str(taicpu(p).opsize) + ' $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + RegName1 + ' -> ' +
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debug_op2str(MovUnaligned);
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{$ifdef x86_64}
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if MovUnaligned <> A_MOVSXD then
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{ Don't add size suffix for MOVSXD }
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{$endif x86_64}
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PreMessage := PreMessage + debug_opsize2str(NewSize);
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Inc(taicpu(p).oper[0]^.ref^.offset, NewOffset);
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taicpu(p).opcode := MovUnaligned;
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taicpu(p).opsize := NewSize;
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DebugMsg(SPeepholeOptimization + PreMessage + ' ' +
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debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (MovShr/Sar2Movx)', p);
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RemoveInstruction(hp1);
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Result := True;
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Exit;
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end;
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end;
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{ Backward optimisation. If we have:
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func. %reg1,%reg2
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