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+ some more arm binary writer stuff, this is mainly a transfer commit
git-svn-id: trunk@1068 -
This commit is contained in:
florian
parent
9452e2a91f
commit
e7e12f0f31
@ -531,13 +531,36 @@ implementation
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end;
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procedure BuildInsTabCache;
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var
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i : longint;
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begin
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new(instabcache);
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FillChar(instabcache^,sizeof(tinstabcache),$ff);
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i:=0;
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while (i<InsTabEntries) do
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begin
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if InsTabCache^[InsTab[i].Opcode]=-1 then
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InsTabCache^[InsTab[i].Opcode]:=i;
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inc(i);
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end;
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end;
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procedure InitAsm;
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begin
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if not assigned(instabcache) then
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BuildInsTabCache;
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end;
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procedure DoneAsm;
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begin
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if assigned(instabcache) then
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begin
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dispose(instabcache);
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instabcache:=nil;
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end;
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end;
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@ -823,6 +846,23 @@ implementation
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function taicpu.Pass1(offset:longint):longint;
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begin
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Pass1:=0;
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{ Save the old offset and set the new offset }
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InsOffset:=Offset;
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{ Error? }
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if (Insentry=nil) and (InsSize=-1) then
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exit;
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{ set the file postion }
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aktfilepos:=fileinfo;
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{ Get InsEntry }
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if FindInsEntry then
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begin
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InsSize:=4;
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LastInsOffset:=InsOffset;
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Pass1:=InsSize;
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exit;
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end;
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LastInsOffset:=-1;
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end;
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@ -861,8 +901,130 @@ implementation
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end;
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function taicpu.Matches(p:PInsEntry):longint;
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function taicpu.Matches(p:PInsEntry):longint;
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{ * IF_SM stands for Size Match: any operand whose size is not
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* explicitly specified by the template is `really' intended to be
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* the same size as the first size-specified operand.
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* Non-specification is tolerated in the input instruction, but
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* _wrong_ specification is not.
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*
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* IF_SM2 invokes Size Match on only the first _two_ operands, for
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* three-operand instructions such as SHLD: it implies that the
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* first two operands must match in size, but that the third is
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* required to be _unspecified_.
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*
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* IF_SB invokes Size Byte: operands with unspecified size in the
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* template are really bytes, and so no non-byte specification in
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* the input instruction will be tolerated. IF_SW similarly invokes
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* Size Word, and IF_SD invokes Size Doubleword.
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*
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* (The default state if neither IF_SM nor IF_SM2 is specified is
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* that any operand with unspecified size in the template is
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* required to have unspecified size in the instruction too...)
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}
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var
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i,j,asize,oprs : longint;
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siz : array[0..3] of longint;
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begin
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Matches:=100;
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{ Check the opcode and operands }
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if (p^.opcode<>opcode) or (p^.ops<>ops) then
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begin
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Matches:=0;
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exit;
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end;
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{ Check that no spurious colons or TOs are present }
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for i:=0 to p^.ops-1 do
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if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
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begin
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Matches:=0;
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exit;
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end;
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{ Check that the operand flags all match up }
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for i:=0 to p^.ops-1 do
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begin
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if ((p^.optypes[i] and (not oper[i]^.ot)) or
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((p^.optypes[i] and OT_SIZE_MASK) and
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((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
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begin
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if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
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(oper[i]^.ot and OT_SIZE_MASK))<>0 then
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begin
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Matches:=0;
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exit;
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end
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else
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Matches:=1;
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end;
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end;
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{ Check operand sizes }
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{ as default an untyped size can get all the sizes, this is different
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from nasm, but else we need to do a lot checking which opcodes want
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size or not with the automatic size generation }
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asize:=longint($ffffffff);
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(*
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if (p^.flags and IF_SB)<>0 then
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asize:=OT_BITS8
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else if (p^.flags and IF_SW)<>0 then
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asize:=OT_BITS16
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else if (p^.flags and IF_SD)<>0 then
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asize:=OT_BITS32;
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if (p^.flags and IF_ARMASK)<>0 then
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begin
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siz[0]:=0;
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siz[1]:=0;
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siz[2]:=0;
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if (p^.flags and IF_AR0)<>0 then
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siz[0]:=asize
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else if (p^.flags and IF_AR1)<>0 then
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siz[1]:=asize
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else if (p^.flags and IF_AR2)<>0 then
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siz[2]:=asize;
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end
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else
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begin
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{ we can leave because the size for all operands is forced to be
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the same
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but not if IF_SB IF_SW or IF_SD is set PM }
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if asize=-1 then
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exit;
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siz[0]:=asize;
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siz[1]:=asize;
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siz[2]:=asize;
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end;
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if (p^.flags and (IF_SM or IF_SM2))<>0 then
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begin
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if (p^.flags and IF_SM2)<>0 then
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oprs:=2
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else
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oprs:=p^.ops;
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for i:=0 to oprs-1 do
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if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
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begin
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for j:=0 to oprs-1 do
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siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
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break;
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end;
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end
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else
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oprs:=2;
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{ Check operand sizes }
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for i:=0 to p^.ops-1 do
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begin
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if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
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((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
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{ Immediates can always include smaller size }
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((oper[i]^.ot and OT_IMMEDIATE)=0) and
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(((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
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Matches:=2;
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end;
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*)
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end;
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@ -931,8 +1093,6 @@ implementation
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inssize:=-1;
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end;
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end.
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{$ifdef dummy}
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@ -1040,6 +1040,11 @@ Implementation
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objectdata.alloc(Taicpu(hp).Pass1(objectdata.currsec.datasize));
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{$endif NOAG386BIN}
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{$endif i386}
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{$ifdef arm}
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{ reset instructions which could change in pass 2 }
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Taicpu(hp).resetpass2;
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objectdata.alloc(Taicpu(hp).Pass1(objectdata.currsec.datasize));
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{$endif arm}
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end;
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ait_cutobject :
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if SmartAsm then
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@ -1054,12 +1059,8 @@ Implementation
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function TInternalAssembler.TreePass1(hp:Tai):Tai;
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var
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InlineLevel,
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l : longint;
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{$ifdef i386}
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{$ifndef NOAG386BIN}
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l,
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i : longint;
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{$endif NOAG386BIN}
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{$endif i386}
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begin
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inlinelevel:=0;
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while assigned(hp) do
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@ -1210,6 +1211,25 @@ Implementation
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end;
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{$endif NOAG386BIN}
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{$endif i386}
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{$ifdef arm}
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objectdata.alloc(Taicpu(hp).Pass1(objectdata.currsec.datasize));
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{ fixup the references }
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for i:=1 to Taicpu(hp).ops do
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begin
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with Taicpu(hp).oper[i-1]^ do
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begin
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case typ of
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top_ref :
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begin
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if assigned(ref^.symbol) then
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objectlibrary.UsedAsmSymbolListInsert(ref^.symbol);
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if assigned(ref^.relsymbol) then
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objectlibrary.UsedAsmSymbolListInsert(ref^.symbol);
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end;
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end;
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end;
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end;
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{$endif arm}
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end;
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ait_direct :
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Message(asmw_f_direct_not_supported);
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@ -1340,12 +1360,8 @@ Implementation
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but it's better to be on the safe side (PFV) }
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objectoutput.exportsymbol(Tai_label(hp).l);
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end;
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{$ifdef i386}
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{$ifndef NOAG386BIN}
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ait_instruction :
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Taicpu(hp).Pass2(objectdata);
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{$endif NOAG386BIN}
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{$endif i386}
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{$ifdef GDB}
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ait_stabn :
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convertstabs(Tai_stabn(hp).str);
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