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+ implemented OP_SHL/OP_SHR/OP_SAR/OP_ROL/OP_ROR in tcgz80.a_op_const_reg_internal

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git-svn-id: branches/z80@44668 -
This commit is contained in:
nickysn 2020-04-09 21:52:45 +00:00
parent 51e6a3f45b
commit eb3c4546ab
1 changed files with 74 additions and 63 deletions
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137
compiler/z80/cgcpu.pas
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@ -818,6 +818,8 @@ unit cgcpu;
var var
curvalue : byte; curvalue : byte;
tmpop: TAsmOp; tmpop: TAsmOp;
l1: TAsmLabel;
instr: taicpu;
begin begin
optimize_op_const(size,op,a); optimize_op_const(size,op,a);
@ -925,69 +927,78 @@ unit cgcpu;
end; end;
OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR: OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
begin begin
list.Concat(tai_comment.Create(strpnew('WARNING! not implemented: a_op_const_reg_internal, OP_shift/ror'))); if size in [OS_64,OS_S64] then
//if a*tcgsize2size[size]<=8 then a:=a and 63
// begin else
// for j:=1 to a do a:=a and 31;
// begin if a<>0 then
// case op of begin
// OP_SHR: if a>1 then
// list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1))); begin
// OP_SHL: current_asmdata.getjumplabel(l1);
// list.concat(taicpu.op_reg(A_LSL,reg)); getcpuregister(list,NR_B);
// OP_SAR: list.concat(taicpu.op_reg_const(A_LD,NR_B,a));
// list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1))); end;
// OP_ROR: if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
// begin case op of
// { load carry? } OP_ROL:
// if not(size in [OS_8,OS_S8]) then begin
// begin list.concat(taicpu.op_reg(A_RRC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
// list.concat(taicpu.op_none(A_CLC)); list.concat(taicpu.op_reg(A_RLC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
// list.concat(taicpu.op_reg_const(A_SBRC,reg,0)); end;
// list.concat(taicpu.op_none(A_SEC)); OP_ROR:
// end; begin
// list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1))); list.concat(taicpu.op_reg(A_RLC,reg));
// end; list.concat(taicpu.op_reg(A_RRC,reg));
// OP_ROL: end;
// begin end;
// { load carry? } if a>1 then
// if not(size in [OS_8,OS_S8]) then cg.a_label(list,l1);
// begin case op of
// list.concat(taicpu.op_none(A_CLC)); OP_SHL:
// list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1),7)); list.concat(taicpu.op_reg(A_SLA,reg));
// list.concat(taicpu.op_none(A_SEC)); OP_SHR:
// end; list.concat(taicpu.op_reg(A_SRL,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
// list.concat(taicpu.op_reg(A_ROL,reg)) OP_SAR:
// end; list.concat(taicpu.op_reg(A_SRA,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
// else OP_ROL:
// internalerror(2011030901); if size in [OS_8,OS_S8] then
// end; list.concat(taicpu.op_reg(A_RLC,reg))
// if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then else
// begin list.concat(taicpu.op_reg(A_RL,reg));
// for i:=2 to tcgsize2size[size] do OP_ROR:
// begin if size in [OS_8,OS_S8] then
// case op of list.concat(taicpu.op_reg(A_RRC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)))
// OP_ROR, else
// OP_SHR: list.concat(taicpu.op_reg(A_RR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
// list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i))); else
// OP_ROL, internalerror(2020040903);
// OP_SHL: end;
// list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(reg,reghi,i-1))); if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
// OP_SAR: begin
// list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i))); for i:=2 to tcgsize2size[size] do
// else begin
// internalerror(2011030902); case op of
// end; OP_ROR,
// end; OP_SHR,
// end; OP_SAR:
// end; list.concat(taicpu.op_reg(A_RR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i)));
// end OP_ROL,
//else OP_SHL:
// begin list.concat(taicpu.op_reg(A_RL,GetOffsetReg64(reg,reghi,i-1)));
// tmpreg:=getintregister(list,size); else
// a_load_const_reg(list,size,a,tmpreg); internalerror(2020040904);
// a_op_reg_reg(list,op,size,tmpreg,reg); end;
// end; end;
end;
if a>1 then
begin
instr:=taicpu.op_sym(A_DJNZ,l1);
instr.is_jmp:=true;
list.concat(instr);
ungetcpuregister(list,NR_B);
end;
end;
end; end;
OP_ADD: OP_ADD:
begin begin