From ebc55c0f4e18dde0904bcb33ccff8f5e29173b9d Mon Sep 17 00:00:00 2001 From: Yuriy Sydorov Date: Mon, 6 Sep 2021 18:57:41 +0300 Subject: [PATCH] * If in a move instruction "MOV reg1,reg2" one of the registers must be spilled, but reg1 and reg2 are coalesced, then this is a no-op instruction and no spilling is needed. (cherry picked from commit b43ee410906633123e66b8f5fc619277bf9abbef) --- compiler/rgobj.pas | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/compiler/rgobj.pas b/compiler/rgobj.pas index 86ef5316c5..1e2c777a41 100644 --- a/compiler/rgobj.pas +++ b/compiler/rgobj.pas @@ -2415,6 +2415,20 @@ unit rgobj; if not spilled then exit; + { Check if the instruction is "OP reg1,reg2" and reg1 is coalesced with reg2 } + if (regs.reginfocount=1) and (instr.ops=2) and + (instr.oper[0]^.typ=top_reg) and (instr.oper[1]^.typ=top_reg) and + (getregtype(instr.oper[0]^.reg)=getregtype(instr.oper[1]^.reg)) then + begin + { Set both registers in the instruction to the same register } + setsupreg(instr.oper[0]^.reg, regs.reginfo[0].orgreg); + setsupreg(instr.oper[1]^.reg, regs.reginfo[0].orgreg); + { In case of MOV reg,reg no spilling is needed. + This MOV will be removed later in translate_registers() } + if instr.is_same_reg_move(regtype) then + exit; + end; + {$if defined(x86) or defined(mips) or defined(sparcgen) or defined(arm) or defined(m68k)} { Try replacing the register with the spilltemp. This is useful only for the i386,x86_64 that support memory locations for several instructions