From ec3a04da9b8f5f172ce3563ee17b17cae393eef3 Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Wed, 1 Jun 2022 22:31:26 +0200
Subject: [PATCH]   + forgotten pseudo-instructions added

---
 compiler/riscv/cpubase.pas  | 2 +-
 compiler/riscv/itcpugas.pas | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler/riscv/cpubase.pas b/compiler/riscv/cpubase.pas
index 5395e974f6..05b0db7fbb 100644
--- a/compiler/riscv/cpubase.pas
+++ b/compiler/riscv/cpubase.pas
@@ -125,7 +125,7 @@ uses
         A_SFENCE_VM,
 
         { pseudo instructions for accessiong control and status registers }
-        A_RDINSTRET,A_RDCYCLE,A_RDTIME,A_CSRR,A_CSRW,A_CSRS,A_CSRC,A_CSRWI,
+        A_RDINSTRET,A_RDINSTRETH,A_RDCYCLE,A_RDCYCLEH,A_RDTIME,A_RDTIMEH,A_CSRR,A_CSRW,A_CSRS,A_CSRC,A_CSRWI,
         A_CSRSI,A_CSRCI
       );
 
diff --git a/compiler/riscv/itcpugas.pas b/compiler/riscv/itcpugas.pas
index 6e8dfa5824..3abe2f21ff 100644
--- a/compiler/riscv/itcpugas.pas
+++ b/compiler/riscv/itcpugas.pas
@@ -116,7 +116,7 @@ unit itcpugas;
         'sfence.vm',
 
         { pseudo instructions for accessiong control and status registers }
-        'rdinstret','rdcycle','rdtime','csrr','csrw','csrs','csrc','csrwi',
+        'rdinstret','rdinstreth','rdcycle','rdcycleh','rdtime','rdtimeh','csrr','csrw','csrs','csrc','csrwi',
         'csrsi','csrci'
         );