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https://gitlab.com/freepascal.org/fpc/source.git
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+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
* more fixes to m68k for 64-bit operations
This commit is contained in:
carl
parent
d709f6720b
commit
ed77671a9b
@ -72,6 +72,13 @@ unit cg64f32;
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procedure a_param64_ref(list : taasmoutput;const r : treference;const locpara : tparalocation);override;
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procedure a_param64_loc(list : taasmoutput;const l : tlocation;const locpara : tparalocation);override;
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{# This routine tries to optimize the a_op64_const_reg operation, by
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removing superfluous opcodes. Returns TRUE if normal processing
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must continue in op64_const_reg, otherwise, everything is processed
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entirely in this routine, by emitting the appropriate 32-bit opcodes.
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}
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function optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : qword; var reg: tregister64): boolean;override;
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procedure g_rangecheck64(list: taasmoutput; const p: tnode;
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const todef: tdef); override;
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end;
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@ -620,6 +627,98 @@ unit cg64f32;
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end;
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end;
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function tcg64f32.optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : qword; var reg: tregister64): boolean;
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var
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lowvalue, highvalue : cardinal;
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hreg: tregister;
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begin
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lowvalue := cardinal(a);
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highvalue:= a shr 32;
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{ assume it will be optimized out }
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optimize64_op_const_reg := true;
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case op of
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OP_ADD:
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begin
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if a = 0 then
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exit;
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end;
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OP_AND:
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begin
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if lowvalue <> high(cardinal) then
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cg.a_op_const_reg(list,op,lowvalue,reg.reglo);
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if highvalue <> high(cardinal) then
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cg.a_op_const_reg(list,op,highvalue,reg.reghi);
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{ already emitted correctly }
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exit;
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end;
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OP_OR:
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begin
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if lowvalue <> 0 then
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cg.a_op_const_reg(list,op,lowvalue,reg.reglo);
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if highvalue <> 0 then
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cg.a_op_const_reg(list,op,highvalue,reg.reghi);
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{ already emitted correctly }
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exit;
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end;
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OP_SUB:
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begin
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if a = 0 then
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exit;
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end;
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OP_XOR:
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begin
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end;
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OP_SHL:
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begin
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if a = 0 then
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exit;
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{ simply clear low-register
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and shift the rest and swap
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registers.
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}
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if (a > 31) then
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begin
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cg.a_load_const_reg(list,OS_32,0,reg.reglo);
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cg.a_op_const_reg(list,OP_SHL,a mod 32,reg.reghi);
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{ swap the registers }
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hreg := reg.reghi;
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reg.reghi := reg.reglo;
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reg.reglo := hreg;
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exit;
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end;
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end;
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OP_SHR:
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begin
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if a = 0 then exit;
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{ simply clear high-register
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and shift the rest and swap
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registers.
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}
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if (a > 31) then
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begin
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cg.a_load_const_reg(list,OS_32,0,reg.reghi);
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cg.a_op_const_reg(list,OP_SHL,a mod 32,reg.reglo);
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{ swap the registers }
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hreg := reg.reghi;
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reg.reghi := reg.reglo;
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reg.reglo := hreg;
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exit;
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end;
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end;
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OP_IMUL,OP_MUL:
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begin
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if a = 1 then exit;
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end;
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OP_IDIV,OP_DIV:
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begin
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if a = 1 then exit;
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end;
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else
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internalerror(20020817);
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end;
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optimize64_op_const_reg := false;
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end;
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(*
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procedure int64f32_assignment_int64_reg(p : passignmentnode);
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@ -633,7 +732,11 @@ begin
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end.
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{
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$Log$
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Revision 1.26 2002-08-17 22:09:43 florian
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Revision 1.27 2002-08-19 18:17:47 carl
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+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
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* more fixes to m68k for 64-bit operations
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Revision 1.26 2002/08/17 22:09:43 florian
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* result type handling in tcgcal.pass_2 overhauled
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* better tnode.dowrite
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* some ppc stuff fixed
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@ -173,6 +173,12 @@ unit cg64f64;
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const todef: tdef);
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begin
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end;
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function tcg64f64.optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : qword; var reg: tregister64): boolean;
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begin
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{ this should be the same routine as optimize_const_reg!!!!!!!! }
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end;
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procedure tcg.a_reg_alloc(list : taasmoutput;r : tregister64);
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@ -190,7 +196,11 @@ unit cg64f64;
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end.
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{
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$Log$
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Revision 1.3 2002-08-17 22:09:43 florian
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Revision 1.4 2002-08-19 18:17:48 carl
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+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
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* more fixes to m68k for 64-bit operations
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Revision 1.3 2002/08/17 22:09:43 florian
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* result type handling in tcgcal.pass_2 overhauled
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* better tnode.dowrite
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* some ppc stuff fixed
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@ -248,13 +248,15 @@ unit cgobj;
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This routine tries to optimize the const_reg opcode, and should be
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called at the start of a_op_const_reg. It returns the actual opcode
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to emit, and the constant value to emit. If this routine returns
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FALSE, no instruction should be emitted (.eg : imul reg by 1 )
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TRUE, @var(no) instruction should be emitted (.eg : imul reg by 1 )
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@param(op The opcode to emit, returns the opcode which must be emitted)
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@param(a The constant which should be emitted, returns the constant which must
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be amitted)
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}
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function optimize_const_reg(var op: topcg; var a : aword): boolean;virtual;
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be emitted)
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@param(reg The register to emit the opcode with, returns the register with
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which the opcode will be emitted)
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}
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function optimize_op_const_reg(list: taasmoutput; var op: topcg; var a : aword; var reg: tregister): boolean;virtual;
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{#
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This routine is used in exception management nodes. It should
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@ -447,6 +449,19 @@ unit cgobj;
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procedure a_param64_ref(list : taasmoutput;const r : treference;const loc : tparalocation);virtual;abstract;
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procedure a_param64_loc(list : taasmoutput;const l : tlocation;const loc : tparalocation);virtual;abstract;
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{
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This routine tries to optimize the const_reg opcode, and should be
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called at the start of a_op64_const_reg. It returns the actual opcode
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to emit, and the constant value to emit. If this routine returns
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TRUE, @var(no) instruction should be emitted (.eg : imul reg by 1 )
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@param(op The opcode to emit, returns the opcode which must be emitted)
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@param(a The constant which should be emitted, returns the constant which must
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be emitted)
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@param(reg The register to emit the opcode with, returns the register with
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which the opcode will be emitted)
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}
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function optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : qword; var reg: tregister64): boolean;virtual;abstract;
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{ override to catch 64bit rangechecks }
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@ -756,21 +771,21 @@ unit cgobj;
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end;
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function tcg.optimize_const_reg(var op: topcg; var a : aword): boolean;
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function tcg.optimize_op_const_reg(list: taasmoutput; var op: topcg; var a : aword; var reg:tregister): boolean;
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var
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powerval : longint;
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begin
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optimize_const_reg := true;
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optimize_op_const_reg := false;
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case op of
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{ or with zero returns same result }
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OP_OR : if a = 0 then optimize_const_reg := false;
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OP_OR : if a = 0 then optimize_op_const_reg := true;
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{ and with max returns same result }
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OP_AND : if (a = high(a)) then optimize_const_reg := false;
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OP_AND : if (a = high(a)) then optimize_op_const_reg := true;
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{ division by 1 returns result }
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OP_DIV :
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begin
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if a = 1 then
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optimize_const_reg := false
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optimize_op_const_reg := true
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else if ispowerof2(int64(a), powerval) then
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begin
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a := powerval;
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@ -781,7 +796,7 @@ unit cgobj;
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OP_IDIV:
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begin
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if a = 1 then
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optimize_const_reg := false
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optimize_op_const_reg := true
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else if ispowerof2(int64(a), powerval) then
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begin
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a := powerval;
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@ -792,7 +807,7 @@ unit cgobj;
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OP_MUL,OP_IMUL:
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begin
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if a = 1 then
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optimize_const_reg := false
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optimize_op_const_reg := true
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else if ispowerof2(int64(a), powerval) then
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begin
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a := powerval;
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@ -802,8 +817,8 @@ unit cgobj;
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end;
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OP_SAR,OP_SHL,OP_SHR:
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begin
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if a = 1 then
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optimize_const_reg := false;
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if a = 0 then
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optimize_op_const_reg := true;
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exit;
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end;
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end;
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@ -1553,7 +1568,11 @@ finalization
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end.
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{
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$Log$
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Revision 1.52 2002-08-17 22:09:43 florian
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Revision 1.53 2002-08-19 18:17:48 carl
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+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
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* more fixes to m68k for 64-bit operations
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Revision 1.52 2002/08/17 22:09:43 florian
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* result type handling in tcgcal.pass_2 overhauled
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* better tnode.dowrite
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* some ppc stuff fixed
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@ -38,7 +38,11 @@
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{
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$Log$
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Revision 1.5 2002-08-15 15:11:53 carl
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Revision 1.6 2002-08-19 18:17:48 carl
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+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
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* more fixes to m68k for 64-bit operations
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Revision 1.5 2002/08/15 15:11:53 carl
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* oldset define is now correct for all cpu's except i386
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* correct compilation problems because of the above
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@ -50,3 +54,6 @@
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+ log added
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}
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{
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}
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@ -30,7 +30,7 @@ unit cgcpu;
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cginfo,cgbase,cgobj,
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aasmbase,aasmtai,aasmcpu,
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cpubase,cpuinfo,cpupara,
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node,symconst;
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node,symconst,cg64f32;
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type
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tcg68k = class(tcg)
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@ -61,13 +61,7 @@ unit cgcpu;
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{ generates overflow checking code for a node }
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procedure g_overflowcheck(list: taasmoutput; const p: tnode); override;
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procedure g_copyvaluepara_openarray(list : taasmoutput;const ref:treference;elesize:integer); override;
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{
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This routine should setup the stack frame and allocate @var(localsize) bytes on
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the local stack (for local variables). It should also setup the frame pointer,
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so that all variables are now accessed via the frame pointer register.
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}
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procedure g_stackframe_entry(list : taasmoutput;localsize : longint);override;
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{ restores the previous frame pointer at procedure exit }
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procedure g_restore_frame_pointer(list : taasmoutput);override;
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procedure g_return_from_proc(list : taasmoutput;parasize : aword);override;
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procedure g_save_standard_registers(list : taasmoutput; usedinproc : tregisterset);override;
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@ -85,6 +79,10 @@ unit cgcpu;
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end;
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tcg64f68k = class(tcg64f32)
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procedure a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);override;
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procedure a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);override;
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end;
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{ This function returns true if the reference+offset is valid.
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Otherwise extra code must be generated to solve the reference.
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@ -110,7 +108,7 @@ Implementation
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uses
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globtype,globals,verbose,systems,cutils,
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symdef,symsym,defbase,paramgr,
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rgobj,tgobj,rgcpu,cg64f32;
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rgobj,tgobj,rgcpu;
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const
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@ -168,7 +166,9 @@ Implementation
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end;
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end;
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{****************************************************************************}
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{ TCG68K }
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{****************************************************************************}
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function tcg68k.fixref(list: taasmoutput; var ref: treference): boolean;
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var
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@ -285,7 +285,11 @@ Implementation
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procedure tcg68k.a_loadfpu_reg_reg(list: taasmoutput; reg1, reg2: tregister);
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begin
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list.concat(taicpu.op_reg_reg(A_FMOVE,S_FD,reg1,reg2));
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{ in emulation mode, only 32-bit single is supported }
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if cs_fp_emulation in aktmoduleswitches then
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list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg1,reg2))
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else
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list.concat(taicpu.op_reg_reg(A_FMOVE,S_FD,reg1,reg2));
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end;
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@ -299,7 +303,11 @@ Implementation
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if opsize = S_FX then
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internalerror(20020729);
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fixref(list,href);
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list.concat(taicpu.op_ref_reg(A_FMOVE,opsize,href,reg));
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{ in emulation mode, only 32-bit single is supported }
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if cs_fp_emulation in aktmoduleswitches then
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list.concat(taicpu.op_ref_reg(A_MOVE,S_L,href,reg))
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else
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list.concat(taicpu.op_ref_reg(A_FMOVE,opsize,href,reg));
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end;
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procedure tcg68k.a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference);
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@ -310,7 +318,11 @@ Implementation
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{ extended is not supported, since it is not available on Coldfire }
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if opsize = S_FX then
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internalerror(20020729);
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list.concat(taicpu.op_reg_ref(A_FMOVE,opsize,reg, ref));
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{ in emulation mode, only 32-bit single is supported }
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if cs_fp_emulation in aktmoduleswitches then
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list.concat(taicpu.op_reg_ref(A_MOVE,S_L,reg, ref))
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else
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list.concat(taicpu.op_reg_ref(A_FMOVE,opsize,reg, ref));
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end;
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procedure tcg68k.a_loadmm_reg_reg(list: taasmoutput; reg1, reg2: tregister);
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@ -341,7 +353,7 @@ Implementation
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opcode : tasmop;
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begin
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{ need to emit opcode? }
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if not optimize_const_reg(op, a) then
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if optimize_op_const_reg(list, op, a, reg) then
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exit;
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opcode := topcg2tasmop[op];
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case op of
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@ -1100,15 +1112,133 @@ Implementation
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list.concat(ai);
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end;
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{****************************************************************************}
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{ TCG64F68K }
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{****************************************************************************}
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procedure tcg64f68k.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
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var
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hreg1, hreg2 : tregister;
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opcode : tasmop;
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begin
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opcode := topcg2tasmop[op];
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case op of
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OP_ADD :
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begin
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{ if one of these three registers is an address
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register, we'll really get into problems!
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}
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if rg.isaddressregister(regdst.reglo) or
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rg.isaddressregister(regdst.reghi) or
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rg.isaddressregister(regsrc.reghi) then
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internalerror(20020817);
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list.concat(taicpu.op_reg_reg(A_ADD,S_L,regsrc.reglo,regdst.reglo));
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list.concat(taicpu.op_reg_reg(A_ADDX,S_L,regsrc.reghi,regdst.reghi));
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end;
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OP_AND,OP_OR :
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begin
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{ at least one of the registers must be a data register }
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if (rg.isaddressregister(regdst.reglo) and
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rg.isaddressregister(regsrc.reglo)) or
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(rg.isaddressregister(regsrc.reghi) and
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rg.isaddressregister(regdst.reghi))
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then
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internalerror(20020817);
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cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
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cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
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end;
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{ this is handled in 1st pass for 32-bit cpu's (helper call) }
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OP_IDIV,OP_DIV,
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OP_IMUL,OP_MUL: internalerror(2002081701);
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{ this is also handled in 1st pass for 32-bit cpu's (helper call) }
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OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
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OP_SUB:
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begin
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{ if one of these three registers is an address
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register, we'll really get into problems!
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}
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if rg.isaddressregister(regdst.reglo) or
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rg.isaddressregister(regdst.reghi) or
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rg.isaddressregister(regsrc.reghi) then
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internalerror(20020817);
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list.concat(taicpu.op_reg_reg(A_SUB,S_L,regsrc.reglo,regdst.reglo));
|
||||
list.concat(taicpu.op_reg_reg(A_SUBX,S_L,regsrc.reghi,regdst.reghi));
|
||||
end;
|
||||
OP_XOR:
|
||||
begin
|
||||
if rg.isaddressregister(regdst.reglo) or
|
||||
rg.isaddressregister(regsrc.reglo) or
|
||||
rg.isaddressregister(regsrc.reghi) or
|
||||
rg.isaddressregister(regdst.reghi) then
|
||||
internalerror(20020817);
|
||||
list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reglo,regdst.reglo));
|
||||
list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reghi,regdst.reghi));
|
||||
end;
|
||||
end; { end case }
|
||||
end;
|
||||
|
||||
|
||||
procedure tcg64f68k.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : qword;reg : tregister64);
|
||||
var
|
||||
lowvalue : cardinal;
|
||||
highvalue : cardinal;
|
||||
begin
|
||||
{ is it optimized out ? }
|
||||
if optimize64_op_const_reg(list,op,value,reg) then
|
||||
exit;
|
||||
|
||||
lowvalue := cardinal(value);
|
||||
highvalue:= value shr 32;
|
||||
|
||||
{ the destination registers must be data registers }
|
||||
if rg.isaddressregister(reg.reglo) or
|
||||
rg.isaddressregister(reg.reghi) then
|
||||
internalerror(20020817);
|
||||
case op of
|
||||
OP_ADD :
|
||||
begin
|
||||
list.concat(taicpu.op_const_reg(A_ADD,S_L,lowvalue,reg.reglo));
|
||||
list.concat(taicpu.op_const_reg(A_ADDX,S_L,highvalue,reg.reglo));
|
||||
end;
|
||||
OP_AND :
|
||||
begin
|
||||
{ should already be optimized out }
|
||||
internalerror(2002081801);
|
||||
end;
|
||||
OP_OR :
|
||||
begin
|
||||
{ should already be optimized out }
|
||||
internalerror(2002081802);
|
||||
end;
|
||||
{ this is handled in 1st pass for 32-bit cpu's (helper call) }
|
||||
OP_IDIV,OP_DIV,
|
||||
OP_IMUL,OP_MUL: internalerror(2002081701);
|
||||
{ this is also handled in 1st pass for 32-bit cpu's (helper call) }
|
||||
OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
|
||||
OP_SUB:
|
||||
begin
|
||||
list.concat(taicpu.op_const_reg(A_SUB,S_L,lowvalue,reg.reglo));
|
||||
list.concat(taicpu.op_const_reg(A_SUBX,S_L,highvalue,reg.reglo));
|
||||
end;
|
||||
OP_XOR:
|
||||
begin
|
||||
list.concat(taicpu.op_const_reg(A_EOR,S_L,lowvalue,reg.reglo));
|
||||
list.concat(taicpu.op_const_reg(A_EOR,S_L,highvalue,reg.reglo));
|
||||
end;
|
||||
end; { end case }
|
||||
end;
|
||||
|
||||
begin
|
||||
cg := tcg68k.create;
|
||||
cg64 :=tcg64f32.create;
|
||||
cg64 :=tcg64f68k.create;
|
||||
end.
|
||||
|
||||
{
|
||||
$Log$
|
||||
Revision 1.4 2002-08-16 14:24:59 carl
|
||||
Revision 1.5 2002-08-19 18:17:48 carl
|
||||
+ optimize64_op_const_reg implemented (optimizes 64-bit constant opcodes)
|
||||
* more fixes to m68k for 64-bit operations
|
||||
|
||||
Revision 1.4 2002/08/16 14:24:59 carl
|
||||
* issameref() to test if two references are the same (then emit no opcodes)
|
||||
+ ret_in_reg to replace ret_in_acc
|
||||
(fix some register allocation bugs at the same time)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user