mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-22 06:49:27 +02:00
+ Added newra version of Ti386shlshrnode
+ Added interference graph construction code
This commit is contained in:
daniel
parent
fb55235acc
commit
eedc447400
@ -1029,9 +1029,13 @@ interface
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{ right.location<>LOC_REGISTER }
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if (nodetype=subn) and (nf_swaped in flags) then
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begin
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{$ifdef newra}
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r:=rg.getregisterint(exprasmlist,OS_INT);
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{$else}
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rg.getexplicitregisterint(exprasmlist,NR_EDI);
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r.enum:=R_INTREGISTER;
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r.number:=NR_EDI;
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{$endif}
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cg64.a_load64low_loc_reg(exprasmlist,right.location,r);
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emit_reg_reg(op1,opsize,left.location.registerlow,r);
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emit_reg_reg(A_MOV,opsize,r,left.location.registerlow);
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@ -1636,7 +1640,11 @@ begin
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end.
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{
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$Log$
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Revision 1.57 2003-03-08 13:59:17 daniel
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Revision 1.58 2003-03-08 20:36:41 daniel
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+ Added newra version of Ti386shlshrnode
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+ Added interference graph construction code
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Revision 1.57 2003/03/08 13:59:17 daniel
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* Work to handle new register notation in ag386nsm
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+ Added newra version of Ti386moddivnode
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@ -70,6 +70,7 @@ implementation
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var r,r2,hreg1,hreg2:Tregister;
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power:longint;
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hl:Tasmlabel;
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op:Tasmop;
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pushedregs:Tmaybesave;
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begin
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@ -81,111 +82,105 @@ implementation
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maybe_restore(exprasmlist,left.location,pushedregs);
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if codegenerror then
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exit;
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location_copy(location,left.location);
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if is_64bitint(resulttype.def) then
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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{ put numerator in register }
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location_reset(location,LOC_REGISTER,OS_INT);
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resulttype.def) Then
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begin
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if (aktOptProcessor <> class386) and
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not(cs_littlesize in aktglobalswitches) then
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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begin
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{ no jumps, but more operations }
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hreg2:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,S_L,31,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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emit_const_reg(A_AND,S_L,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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{ release EDX if we used it }
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rg.ungetregisterint(exprasmlist,hreg2);
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{ do the shift }
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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else
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begin
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{ a jump, but less operations }
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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objectlibrary.getlabel(hl);
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emitjmp(C_NS,hl);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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end
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else
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emit_const_reg(A_SHR,S_L,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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{ put numerator in register }
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location_reset(location,LOC_REGISTER,OS_INT);
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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{Bring denominator to a register.}
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rg.getexplicitregisterint(exprasmlist,NR_EAX);
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r.enum:=R_INTREGISTER;
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r.number:=NR_EAX;
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r2.enum:=R_INTREGISTER;
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r2.number:=NR_EDX;
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emit_reg_reg(A_MOV,S_L,hreg1,r);
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rg.ungetregisterint(exprasmlist,hreg1);
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rg.getexplicitregisterint(exprasmlist,NR_EDX);
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{Sign extension depends on the left type.}
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if torddef(left.resulttype.def).typ=u32bit then
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emit_reg_reg(A_XOR,S_L,r2,r2)
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else
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emit_none(A_CDQ,S_NO);
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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{Division depends on the right type.}
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if torddef(right.resulttype.def).typ=u32bit then
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op:=A_DIV
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else
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op:=A_IDIV;
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,S_L,right.location.reference)
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else
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emit_reg(op,S_L,right.location.register);
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location_release(exprasmlist,right.location);
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{Copy the result into a new register. Release EAX & EDX.}
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if nodetype=divn then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resulttype.def) Then
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begin
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if (aktOptProcessor <> class386) and
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not(CS_LittleSize in aktglobalswitches) then
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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begin
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{ no jumps, but more operations }
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hreg2:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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{ if the left value is signed, hreg2 := $ffffffff,
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otherwise 0 }
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emit_const_reg(A_SAR,S_L,31,hreg2);
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{ if signed, hreg2 := right value-1, otherwise 0 }
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emit_const_reg(A_AND,S_L,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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{ release EDX if we used it }
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{ also releas EDI }
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rg.ungetregisterint(exprasmlist,hreg2);
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{ do the shift }
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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else
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begin
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{ a jump, but less operations }
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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objectlibrary.getlabel(hl);
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emitjmp(C_NS,hl);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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end
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else
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emit_const_reg(A_SHR,S_L,power,hreg1);
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location.register:=hreg1;
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rg.ungetregisterint(exprasmlist,r2);
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location.register:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,r,location.register);
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rg.ungetregisterint(exprasmlist,r);
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end
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else
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begin
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{Bring denominator to a register.}
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hreg2:=rg.getregisterint(exprasmlist,OS_INT);
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if right.location.loc<>LOC_CREGISTER then
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location_release(exprasmlist,right.location);
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cg.a_load_loc_reg(exprasmlist,right.location,hreg2);
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rg.getexplicitregisterint(exprasmlist,NR_EAX);
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rg.getexplicitregisterint(exprasmlist,NR_EDX);
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r.enum:=R_INTREGISTER;
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r.number:=NR_EAX;
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r2.enum:=R_INTREGISTER;
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r2.number:=NR_EDX;
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emit_reg_reg(A_MOV,S_L,hreg1,r);
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rg.ungetregisterint(exprasmlist,hreg1);
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{Sign extension depends on the left type.}
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if torddef(left.resulttype.def).typ=u32bit then
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emit_reg_reg(A_XOR,S_L,r2,r2)
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else
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emit_none(A_CDQ,S_NO);
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{Division depends on the right type.}
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if torddef(right.resulttype.def).typ=u32bit then
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emit_reg(A_DIV,S_L,hreg2)
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else
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emit_reg(A_IDIV,S_L,hreg2);
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rg.ungetregisterint(exprasmlist,hreg2);
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if nodetype=divn then
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begin
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rg.ungetregisterint(exprasmlist,r2);
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location.register:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,r,location.register);
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rg.ungetregisterint(exprasmlist,r);
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end
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else
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begin
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rg.ungetregisterint(exprasmlist,r);
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location.register:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,r2,location.register);
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rg.ungetregisterint(exprasmlist,r2);
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end;
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rg.ungetregisterint(exprasmlist,r);
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location.register:=rg.getregisterint(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,r2,location.register);
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rg.ungetregisterint(exprasmlist,r2);
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end;
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end;
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end;
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end;
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{$else}
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procedure ti386moddivnode.pass_2;
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@ -414,10 +409,175 @@ implementation
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function ti386shlshrnode.first_shlshr64bitint: tnode;
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begin
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result := nil;
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end;
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begin
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result := nil;
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end;
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{$ifdef newra}
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procedure ti386shlshrnode.pass_2;
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var hregister2,hregisterhigh,hregisterlow:Tregister;
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r,r2:Tregister;
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op:Tasmop;
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l1,l2,l3:Tasmlabel;
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pushedregs:Tmaybesave;
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begin
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secondpass(left);
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maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
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secondpass(right);
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maybe_restore(exprasmlist,left.location,pushedregs);
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{ determine operator }
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if nodetype=shln then
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op:=A_SHL
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else
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op:=A_SHR;
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if is_64bitint(left.resulttype.def) then
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begin
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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location_force_reg(exprasmlist,left.location,OS_64,false);
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hregisterhigh:=left.location.registerhigh;
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hregisterlow:=left.location.registerlow;
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if hregisterhigh.enum<>R_INTREGISTER then
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internalerror(200302056);
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if hregisterlow.enum<>R_INTREGISTER then
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internalerror(200302056);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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{ shrd/shl works only for values <=31 !! }
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if Tordconstnode(right).value>31 then
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begin
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if nodetype=shln then
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begin
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emit_reg_reg(A_XOR,S_L,hregisterhigh,hregisterhigh);
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if ((tordconstnode(right).value and 31) <> 0) then
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emit_const_reg(A_SHL,S_L,tordconstnode(right).value and 31,
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hregisterlow);
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end
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else
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begin
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emit_reg_reg(A_XOR,S_L,hregisterlow,hregisterlow);
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if ((tordconstnode(right).value and 31) <> 0) then
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emit_const_reg(A_SHR,S_L,tordconstnode(right).value and 31,
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hregisterhigh);
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end;
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location.registerhigh:=hregisterlow;
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location.registerlow:=hregisterhigh;
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end
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else
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begin
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if nodetype=shln then
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begin
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emit_const_reg_reg(A_SHLD,S_L,tordconstnode(right).value and 31,
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hregisterlow,hregisterhigh);
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emit_const_reg(A_SHL,S_L,tordconstnode(right).value and 31,
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hregisterlow);
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end
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else
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begin
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emit_const_reg_reg(A_SHRD,S_L,tordconstnode(right).value and 31,
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hregisterhigh,hregisterlow);
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emit_const_reg(A_SHR,S_L,tordconstnode(right).value and 31,
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hregisterhigh);
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end;
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location.registerlow:=hregisterlow;
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location.registerhigh:=hregisterhigh;
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end;
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end
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else
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begin
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{ load right operators in a register }
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rg.getexplicitregisterint(exprasmlist,NR_ECX);
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hregister2.enum:=R_INTREGISTER;
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hregister2.number:=NR_ECX;
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cg.a_load_loc_reg(exprasmlist,right.location,hregister2);
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if right.location.loc<>LOC_CREGISTER then
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location_release(exprasmlist,right.location);
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{ left operator is already in a register }
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{ hence are both in a register }
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{ is it in the case ECX ? }
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r.enum:=R_INTREGISTER;
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r.number:=NR_ECX;
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r2.enum:=R_INTREGISTER;
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r2.number:=NR_CL;
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{ the damned shift instructions work only til a count of 32 }
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{ so we've to do some tricks here }
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objectlibrary.getlabel(l1);
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objectlibrary.getlabel(l2);
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objectlibrary.getlabel(l3);
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emit_const_reg(A_CMP,S_L,64,hregister2);
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emitjmp(C_L,l1);
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emit_reg_reg(A_XOR,S_L,hregisterlow,hregisterlow);
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emit_reg_reg(A_XOR,S_L,hregisterhigh,hregisterhigh);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l1);
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emit_const_reg(A_CMP,S_L,32,hregister2);
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emitjmp(C_L,l2);
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emit_const_reg(A_SUB,S_L,32,hregister2);
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if nodetype=shln then
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begin
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emit_reg_reg(A_SHL,S_L,r2,hregisterlow);
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emit_reg_reg(A_MOV,S_L,hregisterlow,hregisterhigh);
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emit_reg_reg(A_XOR,S_L,hregisterlow,hregisterlow);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l2);
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emit_reg_reg_reg(A_SHLD,S_L,r2,hregisterlow,hregisterhigh);
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emit_reg_reg(A_SHL,S_L,r2,hregisterlow);
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end
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else
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begin
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emit_reg_reg(A_SHR,S_L,r2,hregisterhigh);
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emit_reg_reg(A_MOV,S_L,hregisterhigh,hregisterlow);
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emit_reg_reg(A_XOR,S_L,hregisterhigh,hregisterhigh);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l2);
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emit_reg_reg_reg(A_SHRD,S_L,r2,hregisterhigh,hregisterlow);
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emit_reg_reg(A_SHR,S_L,r2,hregisterhigh);
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end;
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cg.a_label(exprasmlist,l3);
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rg.ungetregisterint(exprasmlist,hregister2);
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location.registerlow:=hregisterlow;
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location.registerhigh:=hregisterhigh;
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end;
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end
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else
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begin
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{ load left operators in a register }
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location_copy(location,left.location);
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location_force_reg(exprasmlist,location,OS_INT,false);
|
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|
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r2.enum:=R_INTREGISTER;
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r2.number:=NR_CL;
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|
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)}
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emit_const_reg(op,S_L,tordconstnode(right).value and 31,location.register)
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else
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begin
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{ load right operators in a ECX }
|
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if right.location.loc<>LOC_CREGISTER then
|
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location_release(exprasmlist,right.location);
|
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hregister2:=rg.getexplicitregisterint(exprasmlist,NR_ECX);
|
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cg.a_load_loc_reg(exprasmlist,right.location,hregister2);
|
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|
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{ right operand is in ECX }
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emit_reg_reg(op,S_L,r2,location.register);
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rg.ungetregisterint(exprasmlist,hregister2);
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end;
|
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end;
|
||||
end;
|
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{$else}
|
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procedure ti386shlshrnode.pass_2;
|
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var
|
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hregister2,hregister3,
|
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@ -692,6 +852,7 @@ implementation
|
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end;
|
||||
end;
|
||||
end;
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{$endif}
|
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|
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|
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{*****************************************************************************
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@ -1008,7 +1169,11 @@ begin
|
||||
end.
|
||||
{
|
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$Log$
|
||||
Revision 1.46 2003-03-08 13:59:17 daniel
|
||||
Revision 1.47 2003-03-08 20:36:41 daniel
|
||||
+ Added newra version of Ti386shlshrnode
|
||||
+ Added interference graph construction code
|
||||
|
||||
Revision 1.46 2003/03/08 13:59:17 daniel
|
||||
* Work to handle new register notation in ag386nsm
|
||||
+ Added newra version of Ti386moddivnode
|
||||
|
||||
|
||||
@ -28,6 +28,47 @@
|
||||
references and registers which are used by
|
||||
the code generator.
|
||||
}
|
||||
|
||||
{*******************************************************************************
|
||||
|
||||
(applies to new register allocator)
|
||||
|
||||
Register allocator introduction.
|
||||
|
||||
Free Pascal uses a Chaitin style register allocator similair to the one
|
||||
described in the book "Modern compiler implementation in C" by Andrew W. Appel.,
|
||||
published by Cambridge University Press.
|
||||
|
||||
Reading this book is recommended for a complete understanding. Here is a small
|
||||
introduction.
|
||||
|
||||
The code generator thinks it has an infinite amount of registers. Our processor
|
||||
has a limited amount of registers. Therefore we must reduce the amount of
|
||||
registers until there are less enough to fit into the processors registers.
|
||||
|
||||
Registers can interfere or not interfere. If two imaginary registers interfere
|
||||
they cannot be placed into the same psysical register. Reduction of registers
|
||||
is done by:
|
||||
|
||||
- "coalescing" Two registers that do not interfere are combined
|
||||
into one register.
|
||||
- "spilling" A register is changed into a memory location and the generated
|
||||
code is modified to use the memory location instead of the register.
|
||||
|
||||
Register allocation is a graph colouring problem. Each register is a colour, and
|
||||
if two registers interfere there is a connection between them in the graph.
|
||||
|
||||
In addition to the imaginary registers in the code generator, the psysical
|
||||
CPU registers are also present in this graph. This allows us to make
|
||||
interferences between imaginary registers and cpu registers. This is very
|
||||
usefull for describing archtectural constrains, like for example that
|
||||
the div instruction modifies edx, so variables that are in use at that time
|
||||
cannot be stored into edx. This can be modelled by making edx interfere
|
||||
with those variables.
|
||||
|
||||
*******************************************************************************}
|
||||
|
||||
|
||||
unit rgobj;
|
||||
|
||||
interface
|
||||
@ -59,6 +100,14 @@ unit rgobj;
|
||||
tpushedsaved = array[firstreg..lastreg] of tpushedsavedloc;
|
||||
Tpushedsavedint = array[first_supreg..last_supreg] of Tpushedsavedloc;
|
||||
|
||||
Tinterferencebitmap=array[Tsuperregister] of set of Tsuperregister;
|
||||
Tinterferenceadjlist=array[Tsuperregister] of Pstring;
|
||||
Tinterferencegraph=record
|
||||
bitmap:Tinterferencebitmap;
|
||||
adjlist:Tinterferenceadjlist;
|
||||
end;
|
||||
Pinterferencegraph=^Tinterferencegraph;
|
||||
|
||||
{#
|
||||
This class implements the abstract register allocator
|
||||
It is used by the code generator to allocate and free
|
||||
@ -237,6 +286,9 @@ unit rgobj;
|
||||
procedure saveUnusedState(var state: pointer);virtual;
|
||||
procedure restoreUnusedState(var state: pointer);virtual;
|
||||
protected
|
||||
{$ifdef newra}
|
||||
igraph:Tinterferencegraph;
|
||||
{$endif}
|
||||
{ the following two contain the common (generic) code for all }
|
||||
{ get- and ungetregisterxxx functions/procedures }
|
||||
function getregistergen(list: taasmoutput; const lowreg, highreg: Toldregister;
|
||||
@ -259,6 +311,10 @@ unit rgobj;
|
||||
{$ifdef TEMPREGDEBUG}
|
||||
procedure testregisters;
|
||||
{$endif TEMPREGDEBUGx}
|
||||
{$ifdef newra}
|
||||
procedure add_edge(u,v:Tsuperregister);
|
||||
procedure add_edges_used(u:Tsuperregister);
|
||||
{$endif}
|
||||
end;
|
||||
|
||||
const
|
||||
@ -353,6 +409,9 @@ unit rgobj;
|
||||
fillchar(reg_user,sizeof(reg_user),0);
|
||||
fillchar(reg_releaser,sizeof(reg_releaser),0);
|
||||
{$endif TEMPREGDEBUG}
|
||||
{$ifdef newra}
|
||||
fillchar(igraph,sizeof(igraph),0);
|
||||
{$endif}
|
||||
end;
|
||||
|
||||
|
||||
@ -408,6 +467,9 @@ unit rgobj;
|
||||
list.concat(Tai_regalloc.alloc(r));
|
||||
result:=r;
|
||||
lastintreg:=i;
|
||||
{$ifdef newra}
|
||||
add_edges_used(i);
|
||||
{$endif}
|
||||
exit;
|
||||
end;
|
||||
until i=lastintreg;
|
||||
@ -655,27 +717,37 @@ unit rgobj;
|
||||
end;
|
||||
|
||||
|
||||
procedure trgobj.cleartempgen;
|
||||
procedure Trgobj.cleartempgen;
|
||||
|
||||
begin
|
||||
countunusedregsint:=countusableregsint;
|
||||
countunusedregsfpu:=countusableregsfpu;
|
||||
countunusedregsmm:=countusableregsmm;
|
||||
{$ifdef newra}
|
||||
unusedregsint:=[0..255];
|
||||
{$else}
|
||||
unusedregsint:=usableregsint;
|
||||
{$endif}
|
||||
unusedregsfpu:=usableregsfpu;
|
||||
unusedregsmm:=usableregsmm;
|
||||
end;
|
||||
var i:Tsuperregister;
|
||||
|
||||
begin
|
||||
countunusedregsint:=countusableregsint;
|
||||
countunusedregsfpu:=countusableregsfpu;
|
||||
countunusedregsmm:=countusableregsmm;
|
||||
{$ifdef newra}
|
||||
unusedregsint:=[0..255];
|
||||
{$else}
|
||||
unusedregsint:=usableregsint;
|
||||
{$endif}
|
||||
unusedregsfpu:=usableregsfpu;
|
||||
unusedregsmm:=usableregsmm;
|
||||
{$ifdef newra}
|
||||
for i:=low(Tsuperregister) to high(Tsuperregister) do
|
||||
if igraph.adjlist[i]<>nil then
|
||||
dispose(igraph.adjlist[i]);
|
||||
fillchar(igraph,sizeof(igraph),0);
|
||||
{$endif}
|
||||
end;
|
||||
|
||||
|
||||
procedure trgobj.ungetreference(list : taasmoutput; const ref : treference);
|
||||
|
||||
begin
|
||||
ungetregisterint(list,ref.base);
|
||||
ungetregisterint(list,ref.index);
|
||||
if ref.base.number<>NR_NO then
|
||||
ungetregisterint(list,ref.base);
|
||||
if ref.index.number<>NR_NO then
|
||||
ungetregisterint(list,ref.index);
|
||||
end;
|
||||
|
||||
|
||||
@ -1098,6 +1170,48 @@ unit rgobj;
|
||||
state := nil;
|
||||
end;
|
||||
|
||||
{$ifdef newra}
|
||||
procedure Trgobj.add_edge(u,v:Tsuperregister);
|
||||
|
||||
{This procedure will add an edge to the virtual interference graph.}
|
||||
|
||||
procedure addadj(u,v:Tsuperregister);
|
||||
|
||||
begin
|
||||
if igraph.adjlist[u]=nil then
|
||||
begin
|
||||
getmem(igraph.adjlist[u],16);
|
||||
igraph.adjlist[u]^:='';
|
||||
end
|
||||
else if (length(igraph.adjlist[u]^) and 15)=15 then
|
||||
reallocmem(igraph.adjlist[u],length(igraph.adjlist[u]^)+16);
|
||||
igraph.adjlist[u]^:=igraph.adjlist[u]^+char(v);
|
||||
end;
|
||||
|
||||
begin
|
||||
if (u<>v) and not(v in igraph.bitmap[u]) then
|
||||
begin
|
||||
include(igraph.bitmap[u],v);
|
||||
include(igraph.bitmap[v],u);
|
||||
{Precoloured nodes are not stored in the interference graph.}
|
||||
if not(u in [first_supreg..last_supreg]) then
|
||||
addadj(u,v);
|
||||
if not(v in [first_supreg..last_supreg]) then
|
||||
addadj(v,u);
|
||||
end;
|
||||
end;
|
||||
|
||||
procedure Trgobj.add_edges_used(u:Tsuperregister);
|
||||
|
||||
var i:Tsuperregister;
|
||||
|
||||
begin
|
||||
for i:=1 to 255 do
|
||||
if not(i in unusedregsint) then
|
||||
add_edge(u,i);
|
||||
end;
|
||||
{$endif}
|
||||
|
||||
|
||||
{****************************************************************************
|
||||
TReference
|
||||
@ -1228,7 +1342,11 @@ end.
|
||||
|
||||
{
|
||||
$Log$
|
||||
Revision 1.28 2003-03-08 13:59:16 daniel
|
||||
Revision 1.29 2003-03-08 20:36:41 daniel
|
||||
+ Added newra version of Ti386shlshrnode
|
||||
+ Added interference graph construction code
|
||||
|
||||
Revision 1.28 2003/03/08 13:59:16 daniel
|
||||
* Work to handle new register notation in ag386nsm
|
||||
+ Added newra version of Ti386moddivnode
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user