From f11fbe527e4b728813d012a5c7b88be950efc30c Mon Sep 17 00:00:00 2001 From: masta Date: Mon, 18 Jun 2012 16:59:24 +0000 Subject: [PATCH] Improve loading of ARM constant values * use split_into_shifter_const to reduce the MOV/ORR combination to a single check and allow a broader rang of combinations. * Introduce MVN/BIC combination to load values which have more 1 than 0 bits set (like small negative values) git-svn-id: trunk@21646 - --- compiler/arm/cgcpu.pas | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas index 368cedf158..dc899c9615 100644 --- a/compiler/arm/cgcpu.pas +++ b/compiler/arm/cgcpu.pas @@ -253,6 +253,7 @@ unit cgcpu; imm_shift : byte; l : tasmlabel; hr : treference; + imm1, imm2: DWord; begin if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then internalerror(2002090902); @@ -261,20 +262,16 @@ unit cgcpu; else if is_shifter_const(not(a),imm_shift) then list.concat(taicpu.op_reg_const(A_MVN,reg,not(a))) { loading of constants with mov and orr } - else if (is_shifter_const(a-byte(a),imm_shift)) then + else if (split_into_shifter_const(a,imm1, imm2)) then begin - list.concat(taicpu.op_reg_const(A_MOV,reg,a-byte(a))); - list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,byte(a))); + list.concat(taicpu.op_reg_const(A_MOV,reg, imm1)); + list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg, imm2)); end - else if (is_shifter_const(a-word(a),imm_shift)) and (is_shifter_const(word(a),imm_shift)) then + { loading of constants with mvn and bic } + else if (split_into_shifter_const(not(a), imm1, imm2)) then begin - list.concat(taicpu.op_reg_const(A_MOV,reg,a-word(a))); - list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,word(a))); - end - else if (is_shifter_const(a-(dword(a) shl 8) shr 8,imm_shift)) and (is_shifter_const((dword(a) shl 8) shr 8,imm_shift)) then - begin - list.concat(taicpu.op_reg_const(A_MOV,reg,a-(dword(a) shl 8) shr 8)); - list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,(dword(a) shl 8) shr 8)); + list.concat(taicpu.op_reg_const(A_MVN,reg, imm1)); + list.concat(taicpu.op_reg_reg_const(A_BIC,reg,reg, imm2)); end else begin