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+ Allow replace spilling for "opcode register,const" and "opcode const,register"

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git-svn-id: trunk@7183 -
This commit is contained in:
daniel 2007-04-28 19:11:17 +00:00
parent abfa85563f
commit f3660976bc
1 changed files with 86 additions and 63 deletions
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149
compiler/x86/rgx86.pas
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@ -111,6 +111,11 @@ implementation
function trgx86.do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean; function trgx86.do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;
{Decide wether a "replace" spill is possible, i.e. wether we can replace a register
in an instruction by a memory reference. For example, in "mov ireg26d,0", the imaginary
register ireg26d can be replaced by a memory reference.}
var var
replaceoper : longint; replaceoper : longint;
begin begin
@ -146,69 +151,87 @@ implementation
(get_alias(getsupreg(oper[1]^.reg))=orgreg) then (get_alias(getsupreg(oper[1]^.reg))=orgreg) then
replaceoper:=1 replaceoper:=1
else else
internalerror(200410106); internalerror(200704281);
case replaceoper of end;
0 : if (oper[0]^.typ=top_reg) and
begin (oper[1]^.typ=top_const) then
{ Some instructions don't allow memory references begin
for source } if (getregtype(oper[0]^.reg)=regtype) and
case instr.opcode of (get_alias(getsupreg(oper[0]^.reg))=orgreg) then
A_BT, replaceoper:=0
A_BTS, else
A_BTC, internalerror(200704282);
A_BTR : end;
replaceoper:=-1; if (oper[0]^.typ=top_const) and
end; (oper[1]^.typ=top_reg) then
end; begin
1 : if (getregtype(oper[1]^.reg)=regtype) and
begin (get_alias(getsupreg(oper[1]^.reg))=orgreg) then
{ Some instructions don't allow memory references replaceoper:=1
for destination } else
case instr.opcode of internalerror(200704283);
A_MOVZX, end;
A_MOVSX, case replaceoper of
A_MULSS, 0 :
A_MULSD, begin
A_SUBSS, { Some instructions don't allow memory references
A_SUBSD, for source }
A_ADDSD, case instr.opcode of
A_ADDSS, A_BT,
A_DIVSD, A_BTS,
A_DIVSS, A_BTC,
A_SHLD, A_BTR :
A_SHRD, replaceoper:=-1;
A_CVTDQ2PD, end;
A_CVTDQ2PS, end;
A_CVTPD2DQ, 1 :
A_CVTPD2PI, begin
A_CVTPD2PS, { Some instructions don't allow memory references
A_CVTPI2PD, for destination }
A_CVTPS2DQ, case instr.opcode of
A_CVTPS2PD, A_MOVZX,
A_CVTSD2SI, A_MOVSX,
A_CVTSD2SS, A_MULSS,
A_CVTSI2SD, A_MULSD,
A_CVTSS2SD, A_SUBSS,
A_CVTTPD2PI, A_SUBSD,
A_CVTTPD2DQ, A_ADDSD,
A_CVTTPS2DQ, A_ADDSS,
A_CVTTSD2SI, A_DIVSD,
A_CVTPI2PS, A_DIVSS,
A_CVTPS2PI, A_SHLD,
A_CVTSI2SS, A_SHRD,
A_CVTSS2SI, A_CVTDQ2PD,
A_CVTTPS2PI, A_CVTDQ2PS,
A_CVTTSS2SI, A_CVTPD2DQ,
A_IMUL, A_CVTPD2PI,
A_XORPD, A_CVTPD2PS,
A_XORPS, A_CVTPI2PD,
A_ORPD, A_CVTPS2DQ,
A_ORPS, A_CVTPS2PD,
A_ANDPD, A_CVTSD2SI,
A_ANDPS: A_CVTSD2SS,
replaceoper:=-1; A_CVTSI2SD,
end; A_CVTSS2SD,
end; A_CVTTPD2PI,
A_CVTTPD2DQ,
A_CVTTPS2DQ,
A_CVTTSD2SI,
A_CVTPI2PS,
A_CVTPS2PI,
A_CVTSI2SS,
A_CVTSS2SI,
A_CVTTPS2PI,
A_CVTTSS2SI,
A_IMUL,
A_XORPD,
A_XORPS,
A_ORPD,
A_ORPS,
A_ANDPD,
A_ANDPS:
replaceoper:=-1;
end;
end; end;
end; end;
end; end;