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* tcgtypeconvnode.second_int_to_int: reuse 8 and 16-bit-sized register locations on targets with 32-bit-only registers when casting to larger size (except ShortInt to Word cast). This is possible because upper bits of such registers are always kept valid by code generators (see 'maybeadjustresult' method in cgcpu.pas). Removes a lot of useless register moves.

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git-svn-id: trunk@25067 -
This commit is contained in:
sergei 2013-07-08 13:27:03 +00:00
parent faa778b6c7
commit f3a1c749fb
1 changed files with 10 additions and 0 deletions
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10
compiler/ncgcnv.pas
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@ -115,6 +115,16 @@ interface
location.reference.alignment:=newalignment(location.reference.alignment,leftsize-ressize);
end;
end
{ On targets without 8/16 bit register components, 8/16-bit operations
always adjust high bits of result, see 'maybeadjustresult' method in
respective cgcpu.pas. Therefore 8/16-bit locations are valid as larger
ones (except OS_S8->OS_16 which still needs high 16 bits cleared). }
else if (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) and
(tcgsize2size[(reg_cgsize(left.location.register))]=sizeof(aint)) and
(ressize>leftsize) and
(newsize in [OS_32,OS_S32,OS_16,OS_S16]) and
not ((newsize=OS_16) and (def_cgsize(left.resultdef)=OS_S8)) then
location.size:=newsize
else
hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,false);
end