From f3b7f6197b88ebc2bf2461256c720dc3e8873f90 Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Fri, 3 May 2013 20:53:58 +0000
Subject: [PATCH] * arm thumb: generate proper code for rol

git-svn-id: trunk@24414 -
---
 compiler/arm/cgcpu.pas | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas
index e4ad19e994..c7b9c1a94d 100644
--- a/compiler/arm/cgcpu.pas
+++ b/compiler/arm/cgcpu.pas
@@ -3775,7 +3775,8 @@ unit cgcpu;
                 internalerror(2008072801);
               { simulate ROL by ror'ing 32-value }
               tmpreg:=getintregister(list,OS_32);
-              list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,tmpreg,src,32),PF_S));
+              a_load_const_reg(list,OS_32,32,tmpreg);
+              list.concat(taicpu.op_reg_reg(A_SUB,tmpreg,src));
               list.concat(taicpu.op_reg_reg(A_ROR,dst,src));
             end;
           else