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* x86-64: Extended the movl/movq optimisation to cover more distance
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@ -4125,13 +4125,13 @@ unit aoptx86;
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if (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
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begin
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{ %reg1 = %reg3 }
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlAndl)', hp1);
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlAndl 1)', hp1);
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taicpu(hp1).opcode := A_AND;
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end
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else
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begin
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{ %reg1 <> %reg3 }
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlMovl)', hp1);
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlMovl 1)', hp1);
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end;
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if not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs) then
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@ -4332,35 +4332,99 @@ unit aoptx86;
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Internalerror(2019103001);
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end;
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end
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else
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if MatchOperand(taicpu(hp2).oper[1]^, p_TargetReg) then
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begin
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if not CrossJump and
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not RegUsedBetween(p_TargetReg, p, hp2) and
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not RegReadByInstruction(p_TargetReg, hp2) then
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begin
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{ Register is not used before it is overwritten }
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DebugMsg(SPeepholeOptimization + 'Mov2Nop 3a done',p);
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RemoveCurrentp(p, hp1);
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Result := True;
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Exit;
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end;
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else if MatchOperand(taicpu(hp2).oper[1]^, p_TargetReg) then
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begin
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if not CrossJump and
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not RegUsedBetween(p_TargetReg, p, hp2) and
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not RegReadByInstruction(p_TargetReg, hp2) then
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begin
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{ Register is not used before it is overwritten }
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DebugMsg(SPeepholeOptimization + 'Mov2Nop 3a done',p);
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RemoveCurrentp(p, hp1);
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Result := True;
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Exit;
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end;
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if (taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(hp2).oper[0]^.typ = top_const) then
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begin
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if taicpu(p).oper[0]^.val = taicpu(hp2).oper[0]^.val then
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begin
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{ Same value - register hasn't changed }
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DebugMsg(SPeepholeOptimization + 'Mov2Nop 2 done', hp2);
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RemoveInstruction(hp2);
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Result := True;
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if (taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(hp2).oper[0]^.typ = top_const) then
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begin
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if taicpu(p).oper[0]^.val = taicpu(hp2).oper[0]^.val then
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begin
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{ Same value - register hasn't changed }
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DebugMsg(SPeepholeOptimization + 'Mov2Nop 2 done', hp2);
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RemoveInstruction(hp2);
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Result := True;
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{ See if there's more we can optimise }
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Continue;
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end;
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end;
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{$ifdef x86_64}
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end
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{ Change:
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movl %reg1l,%reg2l
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...
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movq %reg2q,%reg3q (%reg1 <> %reg3)
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To:
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movl %reg1l,%reg2l
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...
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movl %reg1l,%reg3l (Upper 32 bits of %reg3q will be zero)
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If %reg1 = %reg3, convert to:
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movl %reg1l,%reg2l
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...
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andl %reg1l,%reg1l
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}
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else if (taicpu(p).opsize = S_L) and MatchInstruction(hp2,A_MOV,[S_Q]) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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MatchOpType(taicpu(hp2), top_reg, top_reg) and
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SuperRegistersEqual(p_TargetReg, taicpu(hp2).oper[0]^.reg) and
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not RegModifiedBetween(p_TargetReg, p, hp2) then
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begin
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TempRegUsed :=
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CrossJump { Assume the register is in use if it crossed a conditional jump } or
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RegReadByInstruction(p_TargetReg, hp3) or
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RegUsedAfterInstruction(p_TargetReg, hp2, TmpUsedRegs);
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taicpu(hp2).opsize := S_L;
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taicpu(hp2).loadreg(0, taicpu(p).oper[0]^.reg);
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setsubreg(taicpu(hp2).oper[1]^.reg, R_SUBD);
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AllocRegBetween(taicpu(p).oper[0]^.reg, p, hp2, UsedRegs);
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if (taicpu(p).oper[0]^.reg = taicpu(hp2).oper[1]^.reg) then
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begin
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{ %reg1 = %reg3 }
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlAndl 2)', hp2);
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taicpu(hp2).opcode := A_AND;
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end
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else
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begin
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{ %reg1 <> %reg3 }
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DebugMsg(SPeepholeOptimization + 'Made 32-to-64-bit zero extension more efficient (MovlMovq2MovlMovl 2)', hp2);
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end;
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if not TempRegUsed then
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begin
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DebugMsg(SPeepholeOptimization + 'Mov2Nop 8a done', p);
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RemoveCurrentP(p, hp1);
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Result := True;
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Exit;
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end
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else
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begin
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{ Initial instruction wasn't actually changed }
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Include(OptsToCheck, aoc_ForceNewIteration);
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{ if %reg1 = %reg3, don't do the long-distance lookahead that
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appears below since %reg1 has technically changed }
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if taicpu(hp2).opcode = A_AND then
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Break;
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end;
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{$endif x86_64}
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end;
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{ See if there's more we can optimise }
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Continue;
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end;
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end;
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end;
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A_MOVZX, A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}:
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if MatchOpType(taicpu(hp2), top_reg, top_reg) and
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MatchOperand(taicpu(hp2).oper[0]^, p_TargetReg) and
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