paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-09-01 15:50:16 +02:00
Code Issues Packages Projects Releases Wiki Activity

* RiscV: check for cpu capabilities before using fmv for loading zero

Browse Source
This commit is contained in:
florian 2025-01-12 18:30:32 +01:00
parent 5bb4049737
commit f417c87ec8
1 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
compiler/riscv/nrvcon.pas
View File

@ -43,6 +43,7 @@ implementation
globals, globals,
aasmcpu,aasmdata, aasmcpu,aasmdata,
defutil, defutil,
cpuinfo,
cgbase,cgobj,cgutils, cgbase,cgobj,cgutils,
ncon; ncon;
@ -55,9 +56,9 @@ implementation
result:=nil; result:=nil;
if is_number_float(value_real) and (value_real=0.0) and (get_real_sign(value_real)=1) and if is_number_float(value_real) and (value_real=0.0) and (get_real_sign(value_real)=1) and
( (
is_single(resultdef) ((CPURV_HAS_F in cpu_capabilities[current_settings.cputype]) and is_single(resultdef))
{$ifdef RISCV64} {$ifdef RISCV64}
or is_double(resultdef) or ((CPURV_HAS_D in cpu_capabilities[current_settings.cputype]) and is_double(resultdef))
{$endif RISCV64} {$endif RISCV64}
) then ) then
expectloc:=LOC_FPUREGISTER expectloc:=LOC_FPUREGISTER
@ -70,9 +71,9 @@ implementation
begin begin
if is_number_float(value_real) and (value_real=0.0) and (get_real_sign(value_real)=1) and if is_number_float(value_real) and (value_real=0.0) and (get_real_sign(value_real)=1) and
( (
is_single(resultdef) ((CPURV_HAS_F in cpu_capabilities[current_settings.cputype]) and is_single(resultdef))
{$ifdef RISCV64} {$ifdef RISCV64}
or is_double(resultdef) or ((CPURV_HAS_D in cpu_capabilities[current_settings.cputype]) and is_double(resultdef))
{$endif RISCV64} {$endif RISCV64}
) then ) then
begin begin