mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-08-11 16:48:12 +02:00
+ Atmega8 support
git-svn-id: trunk@30768 -
This commit is contained in:
florian
parent
9f587625e7
commit
f5edf77a05
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -8230,6 +8230,7 @@ rtl/embedded/arm/stm32f10x_xl.pp svneol=native#text/pascal
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rtl/embedded/arm/stm32f429.pp svneol=native#text/pascal
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rtl/embedded/arm/xmc4500.pp svneol=native#text/pascal
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rtl/embedded/avr/atmega128.pp svneol=native#text/plain
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rtl/embedded/avr/atmega8.pp svneol=native#text/plain
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rtl/embedded/avr/avrcommon.inc svneol=native#text/plain
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rtl/embedded/avr/avrsim.pp svneol=native#text/plain
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rtl/embedded/avr/start.inc svneol=native#text/plain
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@ -58,6 +58,7 @@ Type
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ct_avrsim,
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ct_atmega8,
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ct_atmega16,
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ct_atmega32,
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ct_atmega48,
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@ -133,6 +134,16 @@ Const
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eepromsize:4096;
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),
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(
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controllertypestr:'ATMEGA8';
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controllerunitstr:'ATMEGA8';
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flashbase:0;
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flashsize:$2000;
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srambase:0;
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sramsize:1024;
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eeprombase:0;
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eepromsize:512
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),
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(
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controllertypestr:'ATMEGA16';
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controllerunitstr:'ATMEGA16';
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flashbase:0;
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@ -1,5 +1,5 @@
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#
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# Don't edit, this file is generated by FPCMake Version 2.0.0 [2015-03-17 rev 30250]
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# Don't edit, this file is generated by FPCMake Version 2.0.0 [2015-05-01 rev 30747]
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#
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default: all
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MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-qnx i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-freebsd m68k-netbsd m68k-amiga m68k-atari m68k-openbsd m68k-palmos m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macos powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-dragonfly arm-linux arm-palmos arm-darwin arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android jvm-java jvm-android i8086-msdos aarch64-darwin
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@ -369,7 +369,7 @@ CPU_UNITS=allwinner_a20
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endif
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endif
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ifeq ($(ARCH),avr)
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CPU_UNITS=atmega128 avrsim
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CPU_UNITS=atmega128 atmega8 avrsim
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endif
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ifeq ($(ARCH),i386)
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CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
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@ -84,7 +84,7 @@ endif
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endif
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ifeq ($(ARCH),avr)
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CPU_UNITS=atmega128 avrsim
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CPU_UNITS=atmega128 atmega8 avrsim
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endif
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ifeq ($(ARCH),i386)
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359
rtl/embedded/avr/atmega8.pp
Normal file
359
rtl/embedded/avr/atmega8.pp
Normal file
@ -0,0 +1,359 @@
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{******************************************************************************
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Register definitions and startup code for ATMEL ATmega128
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******************************************************************************}
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unit atmega8;
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{$goto on}
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{$macro on}
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interface
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const
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_SFR_OFFSET = $20; //indirect addressing
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var
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TWBR : byte absolute $00+_SFR_OFFSET;
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TWSR : byte absolute $01+_SFR_OFFSET;
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TWAR : byte absolute $02+_SFR_OFFSET;
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TWDR : byte absolute $03+_SFR_OFFSET;
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ADCW : word absolute $04+_SFR_OFFSET;
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ADC : word absolute $04+_SFR_OFFSET;
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ADCL : byte absolute $04+_SFR_OFFSET;
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ADCH : byte absolute $05+_SFR_OFFSET;
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ADCSRA : byte absolute $06+_SFR_OFFSET;
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ADMUX : byte absolute $07+_SFR_OFFSET;
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ACSR : byte absolute $08+_SFR_OFFSET;
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UBRRL : byte absolute $09+_SFR_OFFSET;
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UCSRB : byte absolute $0A+_SFR_OFFSET;
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UCSRA : byte absolute $0B+_SFR_OFFSET;
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UDR : byte absolute $0C+_SFR_OFFSET;
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SPCR : byte absolute $0D+_SFR_OFFSET;
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SPSR : byte absolute $0E+_SFR_OFFSET;
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SPDR : byte absolute $0F+_SFR_OFFSET;
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PIND : byte absolute $10+_SFR_OFFSET;
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DDRD : byte absolute $11+_SFR_OFFSET;
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PORTD : byte absolute $12+_SFR_OFFSET;
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PINC : byte absolute $13+_SFR_OFFSET;
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DDRC : byte absolute $14+_SFR_OFFSET;
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PORTC : byte absolute $15+_SFR_OFFSET;
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PINB : byte absolute $16+_SFR_OFFSET;
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DDRB : byte absolute $17+_SFR_OFFSET;
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PORTB : byte absolute $18+_SFR_OFFSET;
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EECR : byte absolute $1C+_SFR_OFFSET;
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EEDR : byte absolute $1D+_SFR_OFFSET;
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EEAR : word absolute $1E+_SFR_OFFSET;
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EEARL : byte absolute $1E+_SFR_OFFSET;
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EEARH : byte absolute $1F+_SFR_OFFSET;
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UCSRC : byte absolute $20+_SFR_OFFSET;
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UBRRH : byte absolute $20+_SFR_OFFSET;
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WDTCR : byte absolute $21+_SFR_OFFSET;
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ASSR : byte absolute $22+_SFR_OFFSET;
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OCR2 : byte absolute $23+_SFR_OFFSET;
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TCNT2 : byte absolute $24+_SFR_OFFSET;
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TCCR2 : byte absolute $25+_SFR_OFFSET;
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ICR1 : word absolute $26+_SFR_OFFSET;
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ICR1L : byte absolute $26+_SFR_OFFSET;
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ICR1H : byte absolute $27+_SFR_OFFSET;
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OCR1B : word absolute $28+_SFR_OFFSET;
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OCR1BL : byte absolute $28+_SFR_OFFSET;
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OCR1BH : byte absolute $29+_SFR_OFFSET;
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OCR1A : word absolute $2A+_SFR_OFFSET;
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OCR1AL : byte absolute $2A+_SFR_OFFSET;
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OCR1AH : byte absolute $2B+_SFR_OFFSET;
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TCNT1 : word absolute $2C+_SFR_OFFSET;
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TCNT1L : byte absolute $2C+_SFR_OFFSET;
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TCNT1H : byte absolute $2D+_SFR_OFFSET;
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TCCR1B : byte absolute $2E+_SFR_OFFSET;
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TCCR1A : byte absolute $2F+_SFR_OFFSET;
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SFIOR : byte absolute $30+_SFR_OFFSET;
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OSCCAL : byte absolute $31+_SFR_OFFSET;
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TCNT0 : byte absolute $32+_SFR_OFFSET;
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TCCR0 : byte absolute $33+_SFR_OFFSET;
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MCUSR : byte absolute $34+_SFR_OFFSET;
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MCUCSR : byte absolute $34+_SFR_OFFSET;
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MCUCR : byte absolute $35+_SFR_OFFSET;
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TWCR : byte absolute $36+_SFR_OFFSET;
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SPMCR : byte absolute $37+_SFR_OFFSET;
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TIFR : byte absolute $38+_SFR_OFFSET;
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TIMSK : byte absolute $39+_SFR_OFFSET;
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GIFR : byte absolute $3A+_SFR_OFFSET;
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GICR : byte absolute $3B+_SFR_OFFSET;
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SP : word absolute $3D+_SFR_OFFSET;
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SPL : byte absolute $3D+_SFR_OFFSET;
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SPH : byte absolute $3E+_SFR_OFFSET;
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SREG : byte absolute $3F+_SFR_OFFSET;
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const
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TWINT = 7;
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TWEA = 6;
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TWSTA = 5;
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TWSTO = 4;
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TWWC = 3;
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TWEN = 2;
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TWIE = 0;
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TWA6 = 7;
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TWA5 = 6;
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TWA4 = 5;
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TWA3 = 4;
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TWA2 = 3;
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TWA1 = 2;
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TWA0 = 1;
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TWGCE = 0;
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TWS7 = 7;
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TWS6 = 6;
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TWS5 = 5;
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TWS4 = 4;
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TWS3 = 3;
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TWPS1 = 1;
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TWPS0 = 0;
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XDIVEN = 7;
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XDIV6 = 6;
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XDIV5 = 5;
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XDIV4 = 4;
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XDIV3 = 3;
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XDIV2 = 2;
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XDIV1 = 1;
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XDIV0 = 0;
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ISC11 = 3;
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ISC10 = 2;
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ISC01 = 1;
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ISC00 = 0;
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INT1 = 7;
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INT0 = 6;
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INTF1 = 7;
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INTF0 = 6;
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OCIE2 = 7;
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TOIE2 = 6;
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TICIE1 = 5;
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OCIE1A = 4;
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OCIE1B = 3;
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TOIE1 = 2;
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TOIE0 = 0;
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OCF2 = 7;
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TOV2 = 6;
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ICF1 = 5;
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OCF1A = 4;
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OCF1B = 3;
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TOV1 = 2;
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TOV0 = 0;
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SPMIE = 7;
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RWWSB = 6;
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RWWSRE = 4;
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BLBSET = 3;
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PGWRT = 2;
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PGERS = 1;
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SPMEN = 0;
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COM1A1 = 7;
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COM1A0 = 6;
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COM1B1 = 5;
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COM1B0 = 4;
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COM1C1 = 3;
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COM1C0 = 2;
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WGM11 = 1;
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WGM10 = 0;
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ICNC = 7;
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ICES = 6;
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WGMB3 = 4;
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WGMB2 = 3;
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CSB2 = 2;
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CSB1 = 1;
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CSB0 = 0;
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ICNC1 = 7;
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ICES1 = 6;
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WGM13 = 4;
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WGM12 = 3;
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CS12 = 2;
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CS11 = 1;
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CS10 = 0;
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FOC2 = 7;
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WGM20 = 6;
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COM21 = 5;
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COM20 = 4;
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WGM21 = 3;
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CS22 = 2;
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CS21 = 1;
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CS20 = 0;
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SPIF = 7;
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WCOL = 6;
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SPI2X = 0;
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SPIE = 7;
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SPE = 6;
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DORD = 5;
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MSTR = 4;
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CPOL = 3;
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CPHA = 2;
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SPR1 = 1;
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SPR0 = 0;
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URSEL = 7;
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UMSEL = 6;
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UPM1 = 5;
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UPM0 = 4;
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USBS = 3;
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UCSZ1 = 2;
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UCSZ0 = 1;
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UCPOL = 0;
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RXC = 7;
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TXC = 6;
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UDRE = 5;
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FE = 4;
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DOR = 3;
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UPE = 2;
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U2X = 1;
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MPCM = 0;
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RXCIE = 7;
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TXCIE = 6;
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UDRIE = 5;
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RXEN = 4;
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TXEN = 3;
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UCSZ = 2;
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UCSZ2 = 2;
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RXB8 = 1;
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TXB8 = 0;
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ACD = 7;
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ACBG = 6;
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ACO = 5;
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ACI = 4;
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ACIE = 3;
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ACIC = 2;
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ACIS1 = 1;
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ACIS0 = 0;
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ADEN = 7;
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ADSC = 6;
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ADFR = 5;
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ADIF = 4;
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ADIE = 3;
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ADPS2 = 2;
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ADPS1 = 1;
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ADPS0 = 0;
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REFS1 = 7;
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REFS0 = 6;
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ADLAR = 5;
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MUX3 = 3;
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MUX2 = 2;
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MUX1 = 1;
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MUX0 = 0;
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{$define DOCALL:=call}
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{$define DOJMP:=jmp}
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implementation
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{$i avrcommon.inc}
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procedure Int00Handler; external name 'Int00Handler';
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procedure Int01Handler; external name 'Int01Handler';
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procedure Int02Handler; external name 'Int02Handler';
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procedure Int03Handler; external name 'Int03Handler';
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procedure Int04Handler; external name 'Int04Handler';
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procedure Int05Handler; external name 'Int05Handler';
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procedure Int06Handler; external name 'Int06Handler';
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procedure Int07Handler; external name 'Int07Handler';
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procedure Int08Handler; external name 'Int08Handler';
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procedure Int09Handler; external name 'Int09Handler';
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procedure Int10Handler; external name 'Int10Handler';
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procedure Int11Handler; external name 'Int11Handler';
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procedure Int12Handler; external name 'Int12Handler';
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procedure Int13Handler; external name 'Int13Handler';
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procedure Int14Handler; external name 'Int14Handler';
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procedure Int15Handler; external name 'Int15Handler';
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procedure Int16Handler; external name 'Int16Handler';
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procedure Int17Handler; external name 'Int17Handler';
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procedure Int18Handler; external name 'Int18Handler';
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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// .org 0x00
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jmp _start
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jmp Int00Handler
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jmp Int01Handler
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jmp Int02Handler
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jmp Int03Handler
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jmp Int04Handler
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jmp Int05Handler
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jmp Int06Handler
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jmp Int07Handler
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jmp Int08Handler
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jmp Int09Handler
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jmp Int10Handler
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jmp Int11Handler
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jmp Int12Handler
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jmp Int13Handler
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jmp Int14Handler
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jmp Int15Handler
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jmp Int16Handler
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jmp Int17Handler
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jmp Int18Handler
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{
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all ATMEL MCUs use the same startup code, the details are
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governed by defines
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}
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{$i start.inc}
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.weak Int00Handler
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.weak Int01Handler
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.weak Int02Handler
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.weak Int03Handler
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.weak Int04Handler
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.weak Int05Handler
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.weak Int06Handler
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.weak Int07Handler
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.weak Int08Handler
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.weak Int09Handler
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.weak Int10Handler
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.weak Int11Handler
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.weak Int12Handler
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.weak Int13Handler
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.weak Int14Handler
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.weak Int15Handler
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.weak Int16Handler
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.weak Int17Handler
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.weak Int18Handler
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.set Int00Handler, Default_IRQ_handler
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.set Int01Handler, Default_IRQ_handler
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.set Int02Handler, Default_IRQ_handler
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.set Int03Handler, Default_IRQ_handler
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.set Int04Handler, Default_IRQ_handler
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.set Int05Handler, Default_IRQ_handler
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.set Int06Handler, Default_IRQ_handler
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.set Int07Handler, Default_IRQ_handler
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.set Int08Handler, Default_IRQ_handler
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.set Int09Handler, Default_IRQ_handler
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.set Int10Handler, Default_IRQ_handler
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.set Int11Handler, Default_IRQ_handler
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.set Int12Handler, Default_IRQ_handler
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.set Int13Handler, Default_IRQ_handler
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.set Int14Handler, Default_IRQ_handler
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.set Int15Handler, Default_IRQ_handler
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.set Int16Handler, Default_IRQ_handler
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.set Int17Handler, Default_IRQ_handler
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.set Int18Handler, Default_IRQ_handler
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end;
|
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|
||||
end.
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||||
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Block a user