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+ aliasing of registers, allows to split live ranges
git-svn-id: trunk@22395 -
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@ -171,7 +171,6 @@ unit rgobj;
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{ can be overridden to add cpu specific interferences }
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procedure add_cpu_interferences(p : tai);virtual;
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procedure add_constraints(reg:Tregister);virtual;
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function get_alias(n:Tsuperregister):Tsuperregister;
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function getregisterinline(list:TAsmList;const subregconstraints:Tsubregisterset):Tregister;
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procedure ungetregisterinline(list:TAsmList;r:Tregister);
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function get_spill_subreg(r : tregister) : tsubregister;virtual;
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@ -208,9 +207,6 @@ unit rgobj;
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extended_backwards,
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backwards_was_first : tbitset;
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{$ifdef EXTDEBUG}
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procedure writegraph(loopidx:longint);
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{$endif EXTDEBUG}
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{ Disposes of the reginfo array.}
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procedure dispose_reginfo;
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{ Prepare the register colouring.}
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@ -236,7 +232,6 @@ unit rgobj;
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procedure add_worklist(u:Tsuperregister);
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function adjacent_ok(u,v:Tsuperregister):boolean;
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function conservative(u,v:Tsuperregister):boolean;
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procedure combine(u,v:Tsuperregister);
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procedure coalesce;
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procedure freeze_moves(u:Tsuperregister);
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procedure freeze;
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@ -249,6 +244,13 @@ unit rgobj;
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procedure set_live_end(reg : tsuperregister;t : tai);
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function get_live_end(reg : tsuperregister) : tai;
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public
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{$ifdef EXTDEBUG}
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procedure writegraph(loopidx:longint);
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{$endif EXTDEBUG}
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procedure combine(u,v:Tsuperregister);
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{ set v as an alias for u }
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procedure set_alias(u,v:Tsuperregister);
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function get_alias(n:Tsuperregister):Tsuperregister;
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property live_range_direction: TRADirection read int_live_range_direction write set_live_range_direction;
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property live_start[reg : tsuperregister]: tai read get_live_start write set_live_start;
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property live_end[reg : tsuperregister]: tai read get_live_end write set_live_end;
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@ -543,7 +545,8 @@ unit rgobj;
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ungetcpuregister(list,newreg(regtype,i,defaultsub));
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end;
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const
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rtindex : longint = 0;
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procedure trgobj.do_register_allocation(list:TAsmList;headertai:tai);
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var
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spillingcounter:byte;
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@ -553,6 +556,10 @@ unit rgobj;
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insert_regalloc_info_all(list);
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ibitmap:=tinterferencebitmap.create;
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generate_interference_graph(list,headertai);
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{$ifdef DEBUG_SSA}
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writegraph(rtindex);
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{$endif DEBUG_SSA}
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inc(rtindex);
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{ Don't do the real allocation when -sr is passed }
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if (cs_no_regalloc in current_settings.globalswitches) then
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exit;
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@ -649,12 +656,12 @@ unit rgobj;
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writeln(f,'Interference graph');
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writeln(f);
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write(f,' ');
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for i:=0 to 15 do
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for i:=0 to maxreg div 16 do
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for j:=0 to 15 do
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write(f,hexstr(i,1));
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writeln(f);
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write(f,' ');
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for i:=0 to 15 do
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for i:=0 to maxreg div 16 do
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write(f,'0123456789ABCDEF');
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writeln(f);
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for i:=0 to maxreg-1 do
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@ -895,7 +902,7 @@ unit rgobj;
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spillworklist.add(n)
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else if move_related(n) then
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freezeworklist.add(n)
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else
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else if not(ri_coalesced in flags) then
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simplifyworklist.add(n);
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end;
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sort_simplify_worklist;
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@ -1095,6 +1102,16 @@ unit rgobj;
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conservative:=(k<usable_registers_cnt);
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end;
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procedure trgobj.set_alias(u,v:Tsuperregister);
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begin
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include(reginfo[v].flags,ri_coalesced);
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if reginfo[v].alias<>0 then
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internalerror(200712291);
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reginfo[v].alias:=get_alias(u);
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coalescednodes.add(v);
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end;
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procedure trgobj.combine(u,v:Tsuperregister);
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@ -1613,11 +1630,19 @@ unit rgobj;
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ra_alloc :
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begin
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live_registers.add(supreg);
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write(live_registers.length,' ');
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for i:=0 to live_registers.length-1 do
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write(std_regname(newreg(R_INTREGISTER,live_registers.buf^[i],defaultsub)),' ');
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writeln;
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add_edges_used(supreg);
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end;
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ra_dealloc :
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begin
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live_registers.delete(supreg);
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write(live_registers.length,' ');
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for i:=0 to live_registers.length-1 do
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write(std_regname(newreg(R_INTREGISTER,live_registers.buf^[i],defaultsub)),' ');
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writeln;
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add_edges_used(supreg);
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end;
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end;
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@ -1743,6 +1768,11 @@ unit rgobj;
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with Taicpu(p) do
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begin
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current_filepos:=fileinfo;
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{For speed reasons, get_alias isn't used here, instead,
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assign_colours will also set the colour of coalesced nodes.
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If there are registers with colour=0, then the coalescednodes
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list probably doesn't contain these registers, causing
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assign_colours not to do this properly.}
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for i:=0 to ops-1 do
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with oper[i]^ do
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case typ of
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