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More 68000 restrictions taken into account for fixref and TST instruction

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git-svn-id: trunk@22762 -
This commit is contained in:
pierre 2012-10-19 11:54:05 +00:00
parent b104d9c9e6
commit f81954760b
1 changed files with 32 additions and 3 deletions
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35
compiler/m68k/cgcpu.pas
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@ -440,8 +440,11 @@ unit cgcpu;
begin begin
if (ref.base<>NR_NO) then if (ref.base<>NR_NO) then
begin begin
if (ref.index <> NR_NO) and assigned(ref.symbol) then if (ref.index<>NR_NO) and assigned(ref.symbol) then
internalerror(2002081402); begin
list.concat(taicpu.op_reg_reg(A_ADD,S_L,ref.base,ref.index));
ref.index:=NR_NO;
end;
{ base + reg } { base + reg }
if ref.index <> NR_NO then if ref.index <> NR_NO then
begin begin
@ -463,7 +466,21 @@ unit cgcpu;
ref.offset := 0; ref.offset := 0;
exit; exit;
end; end;
end; end
else
{ Note: symbol -> ref would be supported as long as ref does not
contain a offset or index... (maybe something for the
optimizer) }
if Assigned(ref.symbol) and (ref.index<>NR_NO) then
begin
hreg:=cg.getaddressregister(list);
idxreg:=ref.index;
ref.index:=NR_NO;
list.concat(taicpu.op_ref_reg(A_LEA,S_L,ref,hreg));
reference_reset_base(ref,hreg,0,ref.alignment);
ref.index:=idxreg;
fixref:=true;
end;
end; end;
cpu_Coldfire: cpu_Coldfire:
begin begin
@ -1209,6 +1226,18 @@ unit cgcpu;
begin begin
if a = 0 then if a = 0 then
begin begin
if (current_settings.cputype = cpu_MC68000) and isaddressregister(reg) then
begin
{
68000 does not seem to like address register for TST instruction
}
{ always move to a data register }
hregister := getintregister(list,OS_INT);
list.concat(taicpu.op_reg_reg(A_MOVE,S_L,reg,hregister));
{ sign/zero extend the register }
sign_extend(list, size,hregister);
reg:=hregister;
end;
list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg)); list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg));
end end
else else