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+ RiscV has internal rol/r support

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This commit is contained in:
florian 2025-03-27 22:33:30 +01:00
parent f65994ddcb
commit f8f54dcbcf
2 changed files with 6 additions and 1 deletions
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2
compiler/fpcdefs.inc
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@ -345,6 +345,7 @@
{$define cpu32bit}
{$define cpu32bitaddr}
{$define cpu32bitalu}
{$define cpurox}
{$define cpufpemu}
{$define cputargethasfixedstack}
{$define cpuneedsmulhelper}
@ -372,6 +373,7 @@
{$define cpu64bit}
{$define cpu64bitaddr}
{$define cpu64bitalu}
{$define cpurox}
{$define cpufpemu}
{$define cputargethasfixedstack}
{$define cpuneedsmulhelper}

5
compiler/options.pas
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@ -4832,9 +4832,12 @@ procedure read_arguments(cmd:TCmdStr);
{ these cpus have an inline rol/ror implementaion }
{$ifdef cpurox}
{$ifdef m68k}
{$if defined(m68k)}
if CPUM68K_HAS_ROLROR in cpu_capabilities[init_settings.cputype] then
def_system_macro('FPC_HAS_INTERNAL_ROX');
{$elseif defined(riscv)}
if [CPURV_HAS_ZBB,CPURV_HAS_ZBKB]*cpu_capabilities[init_settings.cputype]<>[] then
def_system_macro('FPC_HAS_INTERNAL_ROX');
{$else}
def_system_macro('FPC_HAS_INTERNAL_ROX');
{$endif}